A Novel Quaternary Decoder Design Utilizing 32nm CMOS
and GNRFET Technology for Enhanced High-Density
Memory Applications
Vishwas P
Anindita Chattopadhyay Pooja Desai Dept. of Electronics and
Dept. of Electronics and Dept. of Electronics and Communication
Communication Communication BMS College of Engineering
BMS College of Engineering BMS College of Engineering Bengaluru, India
Bengaluru, India Bengaluru, India vishwasp.lv21@[Link]
anindita.lvs21@[Link] pooja.lvs21@[Link]
Dr. Vasundhara Patel K.S
Dept. of Electronics and
Communication
BMS College of Engineering
Bengaluru, India
[Link]@[Link]
Abstract— Multi-Valued Logic (MVL) has more than one logic computing. In this paper, a low-complexity voltage-mode
level defined to represent data whereas binary logic has 2 logic multi-valued logic decoder design that translates a quaternary
levels. It has been shown that the MVL circuits use the circuit logic value into binary that is particularly aimed at high-
resources more effectively at different voltage levels with less density memory applications.
circuitry and greater efficiency. Recently, graphene nano-ribbon
field effect transistor (GNRFET) has drawn a lot of interest due Two particular technologies have been chosen to design and
to its higher electron mobility. This paper presents quaternary implement the MVL decoder: CMOS and GNRFET. CMOS,
decoder implemented in GNRFET and analyzed latency, power, because it has high noise immunity and consumes low
performance etc. also compared the power and delay power. GNRFET, because of its high electrical properties
characteristics of the design implemented both in CMOS and and low power applications. The short-channel effects that
Graphene Nano Ribbon Field Effect Transistor (GNRFET) in are common in CMOS smaller than 100 nm can be avoided
the 32nm technology node. using GNRFET. Compared to a CMOS, less Energy Delay
Keywords— Quaternary, CMOS, GNRFET, Multi-Valued
Product (EDP) and Power Delay Product (PDP) are observed
Logic. by GNRFET implementation.
Graphene-Nano Ribbon-Field-Effect-Transistor (GNRFET)
is the most studied carbon-based field-effect transistors. Due
I. INTRODUCTION
to planar structure GNRFET is the most suitable alternative
The Binary logic is widely used in the semiconductor to silicon without the need to replace existing CMOS
industry. MVL circuits need optimization compared to manufacturing technology [11] [6].
binary number representation and ongoing research in this
area is advancing in this area. MVL reduces the amount of The valence band of carbon forms a group 14 elements.
metal connections, which lowers chip size and power Carbon can be of many non-metal forms. when carbon
consumption. The Multi-Valued Logic (MVL) includes atoms are arranged in crystalline configurations and
several special features for resolving the connection combined it can produce a variety of hexagonal rings
problems. Three levels were first introduced by Lukasiewicz resembling benzene [12]. A two-dimensional layer of
[1] ninety years ago, and a large number of logic levels have carbon is called graphene atoms in their steady state with a
been built on his foundation. MVL is the study of discrete N- zero bandgap. A thin strip is known as graphene with a
valued systems when L > 2, L is the domain of digital width of less than 50 nm.
representation . In a broad sense, discrete variables with an The GNR structures can be made in two forms zigzag and
infinite number of values and binary valued variables can armchair. The armchair edged GNR is metallic and it
both be regarded as MVL systems[2]. depends on the width of the ribbon, either semiconducting
When it comes to testing of the integrated circuits (ICs), the or metallic [11][5].
volume of test data in ICs is rising along with their
complexity[14]. The use of Multi-Valued Logic (MVL) is
one approach to address test economics. Because MVL can
have more than two values, MVL-based ATE can broadcast
a number of test data bits simultaneously in a line. Therefore,
the test data can be increased proportionally to the MVL bit
steps even if the test clock speed is the same as that of the
DUT.
MVL circuits can be designed in two modes: current mode Figure 1 – Armchair GNR width in relation to dimer lines
and voltage mode. Current-mode CMOS Multi-Valued Logic
circuits have applications in digital signal processing and
High-grade graphene has excellent electron mobility and
electrical conducting properties, and is strong, light, M1
practically transparent. Its interactions with other materials Vthp
and with light, as well as its inherent two-dimensional
character, give unique characteristics such the bipolar
transistor effect, ballistic charge transfer, and enormous
IN OUT
quantum oscillations. M2
I. QUATERNARY TO BINARY TRANSLATER Vthn
A. Voltage Level Converter
A circuit made up of PMOS and NMOS transistors is known
as a Voltage Level Converter (VLC). To produce the Figure 3 – Circuit diagram of VLC1
necessary outputs, several threshold voltage (Vth)
combinations are used. Voltage Level Converters come in
three different kinds: VLC1, VLC2, and VLC3. A.2 Volatge Level Converter 2 (VLC2)
The Vth values for NMOS and PMOS transistors for VLC2
are 1.2V and -1.2V, respectively. Here, PMOS will be
Di(x) switched ON and NMOS will be OFF for inputs 0 and 1,
Where, i varies from 0 to 2 for VLC1 to VLC3 respectively, resulting in an output of [Link] NMOS will conduct
and transistor PMOS will be OFF for inputs 2V and 3V,
i {0, 1, … r – 2}
hence the output will be 0.
And x is the input which is varying from 0 to 3,
x {0, 1, … r – 1} The second column of table 1 will be verified by this circuit.
The symbolic representation and circuit diagram are shown
In table 1, truth tables for VLC1, VLC2, and VLC3 are in Fig. 4 and Fig. 5 respectively.
displayed.
Input(vo Output(volts)
lts) VLC1 VLC2 VLC3 IN VLC 2 OUT
0 3 3 3
1 0 3 3
2 0 0 3 Figure 4 - Symbolic representation of VLC2
3 0 0 0
Table 1- Truth table of VLC1, VLC2, and VLC3
M1
A.1 Voltage Level Converter 1 (VLC1) Vthp
The PMOS and NMOS transistors in the VLC1 circuit have a
threshold voltage (Vth) of -2.2V and 0.2 V, respectively.
Since NMOS will be switched off for input ‘0’, PMOS will IN OUT
conduct, and 3V is sent to the output in this case. The output M2
will be ‘0’ for the remaining inputs, which are 1V, 2V, and
3V, where PMOS will be inactive and NMOS will be active. Vthn
The first column of table 1 will be verified by this circuit.
The symbolic representation and circuit diagram are shown
in Fig. 2 and Fig. 3 respectively.
Figure 5 - Circuit diagram of VLC2
IN VLC 1 OUT
A.3 Volatge Level Converter (VLC3)
Figure 2 – Symbolic representation of VLC1 With a Vth value of 2.2V for NMOS and -0.2V for PMOS
transistors, the VLC3 circuit is built. The output will be "3V"
for inputs "0," "1," and "2" because transistor PMOS will
conduct and NMOS will be OFF. The output will be "0" for
input "3" since the transistor's NMOS will conduct while the
PMOS is OFF.
The third column of table 1 will be verified by this circuit.
The symbolic representation and circuit diagram are shown
in Fig. 6, and Fig. 7 respectively.
After examining the simulation results of the circuit
schematics and transient responses of the proposed work, we
IN VLC 3 OUT
will now evaluate the performance of the circuits in terms of
power dissipation, delay, rise time, and fall time.
Figure 6 - Symbolic representation of VLC3 The following graphs were obtained by simulating the design
on H-SPICE. The graph show that the circuit could produce
the desired result and the power graph has also been shown.
M1
Vthp
IN OUT
M2
Vthn
Figure 7 - Circuit diagram of VLC3
Figure 9 – simulation result of decoder using CMOS
B. Quternary to Binary Converter
A basic Quaternary to binary converter uses three Voltage
Level converters VLC1, VLC2, VLC3, two XOR gates, and
three inverters.
Figure 10 – simulation result of decoder using GNRFET
Figure 8 - Circuit diagram of quaternary to binary converter III. ANALYSIS OF SIMULATION
The decoder circuit presented in this paper is designed and It has been observed that CMOS consumes 3.0899nW power
simulated on SPICE for a 32nm GNRFET and CMOS while GNRFET consumes 7.029nW. The performance delay
process, and the output has been observed and analyzed to calculation shows that GNRFET performs better than CMOS
compare the parameters such as power and speed. Input has at 32nm technology. It could be said that GNRFET decoders
been varied from 0V to 1.2V in the step of 0.4V. This circuit are have improved performance than the CMOS ones.
operates with four voltage levels corresponding to 0V and
other three power supply lines of 0.4V, 0.8V and 1.2V where
Logic level ‘0’ = 0V, level ‘1’ = 0.4V, level ‘2’ = 0.8V, logic
‘3’ = 1.2V.
II. SIMULATION AND RESULT
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