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3-to-8 Decoder Verilog Code and Testbench

The document describes a 3-to-8 line decoder module in Verilog, which takes a 3-bit input and an enable signal to produce an 8-bit output. The output is set based on the input value when the enable signal is active; otherwise, the output is zeroed. Additionally, a test bench is provided to simulate the decoder's behavior by iterating through possible input combinations and monitoring the output.

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Lukalapu Dileep kumar
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9 views1 page

3-to-8 Decoder Verilog Code and Testbench

The document describes a 3-to-8 line decoder module in Verilog, which takes a 3-bit input and an enable signal to produce an 8-bit output. The output is set based on the input value when the enable signal is active; otherwise, the output is zeroed. Additionally, a test bench is provided to simulate the decoder's behavior by iterating through possible input combinations and monitoring the output.

Uploaded by

Lukalapu Dileep kumar
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd

DECODER :

CODE:

module decoder3_to_8( in,out, en); input [2:0] in; input en; output [7:0] out;
reg [7:0] out; always @( in or en)
begin
if (en) begin out=8'd0; case (in)
3'b000: out[0]=1'b1;
3'b001: out[1]=1'b1;
3'b010: out[2]=1'b1;
3'b011: out[3]=1'b1;
3'b100: out[4]=1'b1;
3'b101: out[5]=1'b1;
3'b110: out[6]=1'b1; 3'b111: out[7]=1'b1;
default: out=8'd0; endcase end else out=8'd0; end endmodule

TEST BENCH :

module decoder_tb; wire [7:0] out; reg en; reg [2:0] in; integer i; decoder3_to_8
dut(in,out,en); initial begin
$monitor( "en=%b, in=%d, out=%b ", en, in, out); for ( i=0; i<16; i=i+1)
begin
{en,in} = i; #1; end end endmodule

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