Introduction to

Sequential Circuits

COE 202
Digital Logic Design

Dr. Muhamed Mudawar

King Fahd University of Petroleum and Minerals
 Presentation Outline

❖ Introduction to Sequential Circuits

❖ Synchronous versus Asynchronous

❖ Latches

❖ Flip-Flops

❖ Characteristic Tables and Equations

Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 2
 Combinational versus Sequential
❖ Two classes of digital circuits
 Combinational Circuits
 Sequential Circuits

❖ Combinational Circuit
 Outputs = F(Inputs)
Combinational
 Function of Inputs only Inputs Outputs
Circuit
 NO internal memory

❖ Sequential Circuit
 Outputs is a function of Inputs and internal Memory
 There is an internal memory that stores the state of the circuit
 Time is very important: memory changes with time
Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 3
 Introduction to Sequential Circuits
A Sequential circuit consists of:

1. Memory elements: Inputs Outputs

Combinational
 Latches or Flip-Flops Logic
Present Next
 Store the Present State
State Memory State
2. Combinational Logic Elements

 Computes the Outputs of the circuit

Outputs depend on Inputs and Current State

 Computes the Next State of the circuit

Next State also depends on the Inputs and the Present State
Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 4
 Two Types of Sequential Circuits
1. Synchronous Sequential Circuit
 Uses a clock signal as an additional input

 Changes in the memory elements are controlled by the clock

 Changes happen at discrete instances of time

2. Asynchronous Sequential Circuit

 No clock signal

 Changes in the memory elements can happen at any instance of time

❖ Our focus will be on Synchronous Sequential Circuits

 Easier to design and analyze than asynchronous sequential circuits

Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 5
 Synchronous Sequential Circuits
Inputs Outputs
Combinational
Logic
Present Next
State Memory State
Elements

Clock
❖ Synchronous sequential circuits use a clock signal
❖ The clock signal is an input to the memory elements
❖ The clock determines when the memory should be updated
❖ The present state = output value of memory (stored)
❖ The next state = input value to memory (not stored yet)
Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 6
 The Clock
Positive Negative
Clock cycle Clock cycle Pulse Pulse

Time

❖ Clock is a periodic signal = Train of pulses (1's and 0's)

❖ The same clock cycle repeats indefinitely over time

❖ Positive Pulse: when the level of the clock is 1

❖ Negative Pulse: when the level of the clock is 0

❖ Rising Edge: when the clock goes from 0 to 1

❖ Falling Edge: when the clock goes from 1 down to 0

Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 7
 Clock Cycle versus Clock Frequency
Clock cycle Clock cycle Clock cycle

Time

❖ Clock cycle (or period) is a time duration

 Measured in seconds, milli-, micro-, nano-, or pico-seconds
 1 ms = 10-3 sec, 1 µs = 10-6 sec, 1 ns = 10-9 sec, 1 ps = 10-12 sec

❖ Clock frequency = number of cycles per second (Hertz)

 1 Hz = 1 cycle/sec, 1 KHz = 103 Hz, 1 MHz = 106 Hz, 1 GHz = 109 Hz

❖ Clock frequency = 1 / Clock Cycle

 Example: Given the clock cycle = 0.5 ns = 0.5 ×10-9 sec
 Then, the clock frequency = 1/(0.5×10-9) = 2×109 Hz = 2 GHz
Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 8
 Memory Elements
❖ Memory can store and maintain binary state (0's or 1's)
 Until directed by an input signal to change state

❖ Main difference between memory elements

 Number of inputs they have

 How the inputs affect the binary state

❖ Two main types:

 Latches are level-sensitive (the level of the clock)

 Flip-Flops are edge-sensitive (sensitive to the edge of the clock)

❖ Flip-Flips are used in synchronous sequential circuits

❖ Flip-Flops are built with latches
Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 9
 Next . . .

❖ Introduction to Sequential Circuits

❖ Synchronous versus Asynchronous

❖ Latches

❖ Flip-Flops

❖ Characteristic Tables and Equations

Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 10
 SR Latch
❖ A latch is a memory element that can store 0 or 1

❖ An SR Latch can be built using two cross-coupled NOR gates

❖ Two inputs: 𝑆 (Set) and 𝑅 (Reset)

❖ Two outputs: 𝑄 and 𝑄

Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 11
 SR Latch Operation
Set Operation Store Operation

R (Reset) 0 1 R (Reset) 0 1
Q Q

0 Q 0 Q
S (Set) 1 S (Set) 0

Reset Operation Store Operation

R (Reset) 1 0 R (Reset) 0 0
Q Q

1 Q 1 Q
S (Set) 0 S (Set) 0

Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 12
 SR Latch Invalid Operation
Invalid Operation Race Condition

R (Reset) 1 0 R (Reset) 1→0 0→1

Q Q

0 Q Q
S (Set) 1 S (Set) 1→0
0→1

S = R = 1 should never be used Unknown State

If S and R change from 1 → 0 R (Reset) 0 0 or 1

Q
simultaneously then race
condition (oscillation) occurs
Final Q and Q are unknown S (Set) 0 Q
1 or 0
Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 13
 Timing Diagram of an SR Latch

Set No change Reset No change Set Undefined Reset No change Set

S 1 0 0 0 1 1 0 0 0 1

R 0 0 1 0 0 1 0 1 0 0

Q 1 1 0 0 1 0 0 0 1

Q 0 0 1 1 0 0 1 1 0
Time
Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 14
 Gated SR Latch with Clock Enable
R (Reset) CR
Q

C (Clock)

CS Q
S (Set)

❖ An additional Clock (enable) input signal C is used

❖ Clock controls when the state of the latch can be changed
❖ When C=0, the S and R inputs have no effect on the latch
The latch will remain in the same state, regardless of S and R
❖ When C=1, then normal SR latch operation
Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 15
 S R Latch with NAND Gates

Known as
the 𝑆 𝑅 Latch

❖ If 𝑆ҧ = 0 and 𝑅ത = 1 then Set (𝑄 = 1, 𝑄 = 0)

❖ If 𝑆ҧ = 1 and 𝑅ത = 0 then Reset (𝑄 = 0, 𝑄 = 1)
❖ When 𝑆ҧ = 𝑅ത = 1, 𝑄 and 𝑄 are unchanged (remain the same)
❖ The latch stores its outputs 𝑄 and 𝑄 as long as 𝑆ҧ = 𝑅ത = 1
❖ When 𝑆ҧ = 𝑅ത = 0, 𝑄 and 𝑄 are undefined (should never be used)
Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 16
 S R Latch Operation
Set Operation Store Operation

S (Set) 0 1 S (Set) 1 1
Q Q

0 Q 0 Q
R (Reset) 1 R (Reset) 1

Reset Operation Store Operation

S (Set) 1 0 S (Set) 1 0
Q Q

1 Q 1 Q
R (Reset) 0 R (Reset) 1
Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 17
 S R Latch Invalid Operation
Invalid Operation Race Condition

S (Set) 0 1 S (Set) 0→1 1→0

Q Q

1 Q Q
R (Reset) 0 R (Reset) 0→1 1→0

S = R = 0 should never be used Unknown State

1
If S and R change from 0 → 1 S (Set) 0 or 1
Q
simultaneously then race
condition (oscillation) occurs
Final Q and Q are unknown Q
R (Reset) 1 1 or 0
Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 18
 Gated SR Latch with Clock Enable
S

❖ An additional Clock (enable) input signal C is used

❖ Clock controls when the state of the latch can be changed
❖ When C=0, the latch remains in the same state
❖ When C=1, then normal latch operation
The NAND gates invert the S and R inputs when C=1
Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 19
 D-Latch with Clock Enable
S

❖ One data input 𝐷

D S
❖ 𝑆 = 𝐷 and 𝑅 = 𝐷 Q

❖ No undefined state
❖ Inverter can be removed Q
C
❖ When 𝐶 = 1, 𝑅 = 𝑆ҧ = 𝐷
ഥ R

Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 20
 Timing of a D-Latch with Clock Enable
D S
Q

D-Latch with
Clock Input
Q
C R

Q
Time
Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 21
 Graphic Symbols for Latches

𝑆 𝑄 𝑆ҧ 𝑄 𝐷 𝑄
𝑆𝑅 𝑆𝑅 𝐷
𝐶 𝐶
𝐿𝑎𝑡𝑐ℎ 𝐿𝑎𝑡𝑐ℎ 𝐿𝑎𝑡𝑐ℎ
𝑅 𝑄 𝑅ത 𝑄 𝐶 𝑄

❖ A bubble appears at the complemented output 𝑄

Indicates that 𝑄 is the complement of 𝑄

❖ A bubble also appears at the inputs of an 𝑆 𝑅 latch

Indicates that logic-0 is used (not logic-1) to set (or reset) the
latch (as in the NAND latch implementation)
Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 22
 Problem with Latches
❖ A latch is level-sensitive (sensitive to the level of the clock)

❖ As long as the clock signal is high …

Any change in the value of input 𝐷 appears in the output 𝑄

❖ Output 𝑄 keeps changing its value during a clock cycle

❖ Final value of output 𝑄 is uncertain

Due to this uncertainty,

latches are NOT used 𝐷 𝑄 𝑄
as memory elements in 𝐿𝑎𝑡𝑐ℎ
synchronous circuits 𝐶𝑙𝑘
𝐶 𝑄 𝑄

Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 23
 Next . . .

❖ Introduction to Sequential Circuits

❖ Synchronous versus Asynchronous

❖ Latches

❖ Flip-Flops

❖ Characteristic Tables and Equations

Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 24
 Flip-Flops
❖ A Flip-Flop is a better memory element for synchronous circuits

❖ Solves the problem of latches in synchronous sequential circuits

❖ A latch is sensitive to the level of the clock

❖ However, a flip-flop is sensitive to the edge of the clock

❖ A flip-flop is called an edge-triggered memory element

❖ It changes it output value at the edge of the clock

High Low Rising Falling Rising Falling

Level Level edge edge edge edge

Time

Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 25
 Edge-Triggered D Flip-Flop
❖ Built using two latches in a master-slave configuration
❖ A master latch (D-type) receives external inputs
❖ A slave latch (SR-type) receives inputs from the master latch
❖ Only one latch is enabled at any given time
When Clk=0, the master is enabled and the D input is latched (slave disabled)
When Clk=1, the slave is enabled to generate the outputs (master is disabled)

𝑄𝑚
Outputs
Master Slave
𝑄𝑚 change when
Clk
Clk changes
from 0 to 1

Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 26
 Negative Edge-Triggered D Flip-Flop
❖ Similar to positive edge-triggered flip-flop
❖ The first inverter at the Master C input is removed
❖ Only one latch is enabled at any given time
When Clk=1, the master is enabled and the D input is latched (slave disabled)
When Clk=0, the slave is enabled to generate the outputs (master is disabled)

𝑄𝑚
Outputs
Master Slave change when
𝑄𝑚
Clk Clk changes
from 1 to 0

Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 27
 D Flip-Flop Timing Diagram
❖ The diagram shows the timing of a positive-edge D Flip-Flop

❖ The master latch changes its output Qm when the clock C is 0

❖ The rising edge of the clock triggers the D Flip-Flop

❖ Notice the slight delay in the output Q after the rising edge

Clk

Qm

Time
Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 28
 Graphic Symbols for Flip-Flops

𝐷𝑎𝑡𝑎 𝐷 𝑄 𝐷𝑎𝑡𝑎 𝐷 𝑄
Flip Flip
Flop Flop
𝐶𝑙𝑘 𝑄 𝐶𝑙𝑘 𝑄

❖ A Flip-Flop has a similar symbol to a Latch

❖ The difference is the arrowhead at the clock input

❖ The arrowhead indicates sensitivity to the edge of the clock

❖ A circle at the Clk input indicates negative edge-triggered FF

Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 29
 Asynchronous Set and Reset
❖ When Flip-Flops are powered, their initial state is unknown
❖ Some flip-flops have an asynchronous Set and Reset inputs
❖ Set forces Q to become 1, independently of the clock
❖ Reset forces Q to become 0, independently of the clock

𝑆𝑒𝑡
Inputs Outputs
𝑆𝑒𝑡 𝑅𝑒𝑠𝑒𝑡 𝐷𝑎𝑡𝑎 𝐶𝑙𝑘 𝑄 𝑄
𝐷𝑎𝑡𝑎 𝐷 𝑄
0 1 X X 1 0
Flip
Flop 1 0 X X 0 1
𝐶𝑙𝑘 𝑄 1 1 0 ↑ 0 1
1 1 1 ↑ 1 0

𝑅𝑒𝑠𝑒𝑡 Function Table

Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 30
 JK Flip-Flop
❖ The D Flip-Flop is the most commonly used type
❖ The JK is another type of Flip-Flop with inputs: J, K, and Clk
❖ When JK = 10 ➔ Set, When JK = 01 ➔ Reset
❖ When JK = 00 ➔ No change, When JK = 11 ➔ Invert outputs
❖ JK can be implemented using two Clocked SR latches and gates

Master Slave
𝑄1
𝑆 𝑆 𝑄
SR Latch

SR Latch
𝐽
𝐶𝑙𝑘 𝐶 𝐶
𝐾 𝑄1
𝑅 𝑅 𝑄

Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 31
 T Flip-Flop
❖ The T (Toggle) flip-flop has inputs: T and Clk

❖ When T = 0 ➔ No change, When T = 1 ➔ Invert outputs

❖ The T flip-flop can be implemented using a JK flip-flop

❖ It can also be implemented using a D flip-flop and a XOR gate

Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 32
 Flip-Flop Characteristic Table
❖ Defines the operation of a flip-flop in a tabular form

❖ Next state is defined in terms of the current state and the inputs

𝑄(𝑡) refers to current state before the clock edge arrives

𝑄(𝑡 + 1) refers to next state after the clock edge arrives

D Flip-Flop JK Flip-Flop T Flip-Flop

D Q(t+1) J K Q(t+1) T Q(t+1)
0 0 Reset 0 0 Q(t) No change 0 Q(t) No change
1 1 Set 0 1 0 Reset 1 Q'(t) Complement
1 0 1 Set
1 1 Q'(t) Complement

Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 33
 Flip-Flop Characteristic Equation
❖ The characteristic equation defines the operation of a flip-flop
❖ For D Flip-Flop: 𝑄 𝑡 + 1 = 𝐷
❖ For JK Flip-Flop: 𝑄 𝑡 + 1 = 𝐽 𝑄 ′ 𝑡 + 𝐾 ′ 𝑄(𝑡)
❖ For T Flip-Flop: 𝑄 𝑡 + 1 = 𝑇 ⨁ 𝑄(𝑡)
❖ Clearly, the D Flip-Flop is the simplest among the three

D Flip-Flop JK Flip-Flop T Flip-Flop

D Q(t+1) J K Q(t+1) T Q(t+1)
0 0 Reset 0 0 Q(t) No change 0 Q(t) No change
1 1 Set 0 1 0 Reset 1 Q'(t) Complement
1 0 1 Set
1 1 Q'(t) Complement
Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 34
 Timing Considerations for Flip-Flops
❖ Setup Time (Ts): Time duration for which the data input must
be valid and stable before the arrival of the clock edge.

❖ Hold Time (Th): Time duration for which the data input must
not be changed after the clock transition occurs.

❖ Ts and Th must be ensured for the proper operation of flip-flops

Rising
Edge Clock

Ts Th

Valid data-in Data Can be Modified after Th

Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 35
 Summary
❖ In a sequential circuit there is internal memory
 Output is a function of current inputs and present state
 The stored memory value defines the present state
 Similarly, the next state depends on current inputs and present state

❖ Two types of sequential circuits:

 Synchronous sequential circuits are clocked (easier to implement)
 Asynchronous sequential circuits are not clocked

❖ Two types of Memory elements: Latches and Flip-Flops

❖ Latches are level-sensitive, flip-flops are edge-triggered
❖ Flip-flops are better memory elements for synchronous circuits
❖ A flip-flop is described using a characteristic table and equation
Introduction to Sequential Circuits COE 202 – Digital Logic Design © Muhamed Mudawar – slide 36