EECS 16B

Introduction to Circuits and Devices

Lecture 13
Prof. Sayeef Salahuddin
Department of Electrical Engineering and Computer Sciences, UC Berkeley,
sayeef@[Link]
 Mid Term 1
• Will cover everything that was discussed upto the class of
2/20/2025
• In class
– 1 hour 20 minutes. Please arrive before 2:05
• One page, one side, 8.5in X 11in size paper notes allowed
• Bring a calculator

EECS 16B Spring 2025 Lecture 1, Slide 2 Instructor: Prof. Salahuddin

 Recap: Capacitors
• Two conductors (usually metal) separated by an insulator

• A capacitor stores charges (Q)

• Complementary charge on two plates creates

an electric field (𝐸) that points from positive
to negative charges

• Capacitance is defined as the rate of change

in charge for a unit change in voltage
C=dQ/dV

• For linear capacitors (most insulators),

charge is proportional to the voltage à Unit: Farad (coulomb/volt)
C=Q/V

EECS 16B Spring 2025 Lecture 1, Slide 3 Instructor: Prof. Salahuddin

 Recap: Capacitors
The potential difference is between two plates is held by
the electric field is equal to the product of the electric field
and the distance of the conductors (thickness of the
insulator)

𝑉 = 𝐸×𝑑 𝑑

𝑞
Then = 𝐸×𝑑
𝐶

The ratio of charge and electric field in an insulator is called the permittivity (𝜖). Unit: Farad/meter

𝜖
Therefore, 𝐶= this equation gives capacitance in Farad/meter2; for Farad multiply by capacitor area
𝑑
EECS 16B Spring 2025 Lecture 1, Slide 4 Instructor: Prof. Salahuddin
 Recap: Capacitors

EECS 16B Spring 2025 Lecture 1, Slide 5 Instructor: Prof. Salahuddin

 Supplementary: General Solution of the
Differential Equation
For a first order, linear differential equation of the form
𝑑𝑦
+ 𝑎𝑦 𝑡 = 𝑏(𝑡) where we assume a to be a constant
𝑑𝑡
Particular Solution (Integrating Factor Method):
Homogeneous/Compl
ementary solution For equation (A) to hold
𝑑𝑦 𝑑𝑦
+ 𝑎𝑦 𝑡 = 0 + 𝑎𝑦 𝑡 = 𝑏(𝑡) 𝑑𝑓 𝑡
𝑑𝑡 𝑑𝑡 = 𝑎𝑓 𝑡
!" 𝑑𝑡
⇒ = −𝑎 We want to find a multiplier function f(t) ⇒ 𝑓 𝑡 = 𝑒 $%
"
⇒ ln 𝑦 = −𝑎𝑡 + 𝐶 such that
⇒ 𝑦 𝑡 = 𝐾𝑒 #$% 𝑑𝑦 Then from (A)
𝑓(𝑡) + 𝑎𝑓(𝑡)𝑦 𝑡 = 𝑏(𝑡)𝑓(𝑡)
𝑑𝑡 1
𝑦 𝑡 = ∫ 𝑏 𝑡 𝑓 𝑡 𝑑𝑡
can be written as 𝑓 𝑡
𝑑 ⇒ 𝑦& 𝑡 = 𝑒 #$% ∫ 𝑒 $% 𝑏 𝑡 𝑑𝑡
[𝑦(𝑡)𝑓(𝑡)] = 𝑏(𝑡)𝑓(𝑡) --(A)
𝑑𝑡

𝑦 𝑡 = 𝐾𝑒 #$% + 𝑒 #$% ∫ 𝑒 $% 𝑏 𝑡 𝑑𝑡 K is determined using initial condition

EECS 16B Spring 2025 Lecture 1, Slide 6 Instructor: Prof. Salahuddin
 Capacitor Transience

EECS 16B Spring 2025 Lecture 1, Slide 7 Instructor: Prof. Salahuddin

 Capacitor Discharge

EECS 16B Spring 2025 Lecture 1, Slide 8 Instructor: Prof. Salahuddin

EECS 16B Spring 2025 Lecture 1, Slide 9 Instructor: Prof. Salahuddin
 2
EE40 Fall Slide 142 Prof. Chang-Hasnain
2006

Digital Signals to a RC circuit

Digital Signals
We compute with pulses.
• Every node in a real circuit has capacitances

voltage
We send beautiful pulses in:

time

• Even if we send in very ‘pure’ square

But we receive lousy-looking

voltage
looking pulses what we actually get is how
it looks pulses at due
in the right the to
output:
capacitor
charging and discharging unless we go
very very slow time

EECS 16B Spring 2025

Capacitor charging Lecture
effects are responsible!
1, Slide 10 Instructor: Prof. Salahuddin

• Every node in a real circuit has capacitance; it’s the charging

of these capacitances that limits circuit performance (speed)
EECS 16B Spring 2025 Lecture 1, Slide 11 Instructor: Prof. Salahuddin
 Pulse Distortion
R
cuit Model for a Logic Gate Pulse Distortion
The input voltage pulse
width must be largePulse Distortion
+ enough; otherwiseR the
+
om Lecture 1) that electronic building blocks The input v
Vin(t)
o as “logic gates” areinput
The used voltage
to implement
pulse
C Vout output pulse is distorted. +
width must
nctions (NAND, NOR, width NOT) in digital ICs enough; oth
– must be large (We need
+
Vin(t) to wait for theCoutputVto output pulse
cal function can be enough; otherwise
implemented thegates.
using these – out
reach a recognizable
– logic level,
te can be modeled pulse
as is distorted
a simple RC circuit: – (We need to w
before changing the input again.) reach a recog
before changi
R
Pulse width = 0.1RC Pulse width = RC PulsePulse
width = width
0.1RC = 10RC
Pulse width = RC Pu
+ 6 6
6 6 6 6

Vin(t) + 5 C Vout 5
5
5 5 5
4
− 4 4

Vout
Vout

Vout
4 4 4

Vout
Vout

Vout

3 3 3
3 – 3 2 3 2 2
1 1 1
2 2 2
0 0 0
en “low” (logic 0) 1 1 0 11 2 3 4 5 0 1 2 3 4 5 0
c 1) voltage states 0 Time Time
0 0
Slide0145 1 2 3 4 0
5 Chang-Hasnain
Prof. 1 2 3 4 5 EE40 Fall0 5 10 15 20 25
Slide 146
Time Time 2006 Time
EECS 16B Spring 2025
EE40 Fall Lecture 1, Slide
Slide 14612 [Link]: Prof. Salahuddin
Chang-Hasnain
2006

Example First Order Circuits: Forced R

oltage pulse of width R + vr(t) -
V V i (t)
 Circuit Model for a Logic Gate
Computers are RC circuits (almost)
• Recall (from Lecture 1) that electronic building blocks
referred to as “logic gates” are used to implement
• Digital logical
circuits are predominantly
functions (NAND,RC circuits
NOR, NOT)(other than the
in digital communication part)
ICs +
• Simplistically
– Anyalogical
logic gate cancan
function be be
model as a RC using
implemented circuitthese gates. Vin(t)
–
• The •speed
A logic gate
of the can beismodeled
computer limited byas
theaRC
simple RC circuit:
time constant
R
Pulse
+ 6

Vin(t) + C Vout
5

− 4

Vout
3
– 2
1
0
switches between “low” (logic 0) 0 1
and “high” (logic 1) voltage states
EE40 Fall Slide 145 Prof. Chang-Hasnain EE40 F
2006 2006
EECS 16B Spring 2025 Lecture 1, Slide 13 Instructor: Prof. Salahuddin

Example F
R
 Capacitors: Power and Energy

EECS 16B Spring 2025 Lecture 1, Slide 14 Instructor: Prof. Salahuddin

EECS 16B Spring 2025 Lecture 1, Slide 15 Instructor: Prof. Salahuddin
EECS 16B Spring 2025 Lecture 1, Slide 16 Instructor: Prof. Salahuddin
EECS 16B Spring 2025 Lecture 1, Slide 17 Instructor: Prof. Salahuddin
 Capacitors
Computer board capacitors
Source[[Link]]

Power line capacitors

[source:[Link]
EECS 16B Spring 2025 Lecture 1, Slide 18 Instructor: Prof. Salahuddin