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MOSFET Circuit Design Tutorial

The document contains a series of tutorial questions related to the design and analysis of analog circuits involving MOSFETs. It covers various aspects such as establishing drain currents and voltages, calculating gate widths, and determining bias currents for specific configurations. Each question provides parameters for different transistor types and requires calculations to achieve desired electrical characteristics.
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0% found this document useful (0 votes)
35 views7 pages

MOSFET Circuit Design Tutorial

The document contains a series of tutorial questions related to the design and analysis of analog circuits involving MOSFETs. It covers various aspects such as establishing drain currents and voltages, calculating gate widths, and determining bias currents for specific configurations. Each question provides parameters for different transistor types and requires calculations to achieve desired electrical characteristics.
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

EC2002E ANALOG CIRCUITS

MODULE 1

TUTORIAL 2

Q1. Design the circuit below to establish a drain current of 1 mA and a drain voltage of 0 V.
The MOSFET has Vt = 1 V, μnCox = 60 μA/V2 , L = 3 μm, and W= 100 μm.

Q2. The PMOS transistor in the circuit has Vt = -0.7 V, μnCox = 60 μA/V2 , L = 0.8 μm, and
A = 0. Find the values required for W and R in order to establish a drain current of
115 μA and a voltage VD of 3.5 V.

Q3. The NMOS transistors in the circuit have Vt = 1 V, μnCox = 120 μA/V2 , A = 0, and L1
= L2 = 1 μm. Find the required values of gate width for each of Q1 and Q2 , and the value of
R, to obtain the voltage and current values indicated.
Q4. The MOSFET has Vt = 1V , kn' = 100 μA/V2 , and A = 0. Find the required values of
W/L and of R so that when vI= VDD = +5 V, rDS = 50Ω, and vo = 50 mV.

Q5a. For each of the circuits shown in fig, find the labelled node voltages. The NMOS
transistors have Vt = 1 V and. kn' W/L = 2 μA/V2 . Assume λ =0.

Q5b. For each of the circuits shown in fig, find the labeled node voltages. The NMOS
transistors have Vt = 1 V and. kn' W/L = 2 μA/V2 . Assume λ =0.
Q6. Various measurements are made on an NMOS amplifier for which the drain resistor R D
is 20 kΩ. First, dc measurements show the voltage across the drain resistor, VRD, to be 2 V
and the gate-to-source bias voltage to be 1.2 V. Then, ac measurements with small signals
show the voltage gain to be -10 V/V. What is the value of Vt for this transistor? If the process
transconductance parameter kn' is 50 μA/V2 , what is the MOSFET's W/L?

Q7. An enhancement NMOS transistor is connected in the bias circuit with VG = 4V and Rs =
1 kΩ. The transistor has Vt = 2 V and kn'(W/L) = 2 mA/V2 . What bias current results? If a
transistor for which kn'(W/L) is 50% higher is used, what is the resulting percentage increase
in ID ?

Q8. The bias circuit of figure below is used in a design with VG = 5 V and Rs = 1 kΩ. For an
enhancement MOSFET with kn'(W/L) = 2 mA/V2 , the source voltage was measured and
found to be 2 V. What must Vt be for this device? If a device for which Vt is 0.5 V less is
used, what does Vs become? What bias current results?
Q9. Design the circuit for an enhancement MOSFET having Vt = 2 V & kn'(W/L) = 2mA/V2.
Let VDD = Vss = 10 V. Design for a dc bias current of 1 mA & for the largest possible voltage
gain (and thus the largest possible RD) consistent with allowing a 2V peak-to-peak voltage
swing at the drain. Assume that the signal voltage on the source terminal of the FET is zero.

Q10. For the circuit with I= 1 mA, RG = 0, RD = 5 k Ω, and VDD = 10 V, consider the
behavior in each of the following two cases. In each case, find the voltages Vs, VD & VDSS
that result
(a)Vt=1V and kn'W/L = 0.5 mA/V2
(b) Vt = 2 V and kn'W/L = 1.25 mA/V2
Q11. Consider the FET amplifier for the case Vt = 2V, kn'(W/L) = 1mA/V2, VGS = 4 V, VDD
= 10V, & RD = 3.6k Ω (a) Find the dc quantities ID and VD. (b) Calculate the value of gm at
the bias point. (c) Calculate the value of the voltage gain. (d) If the MOSFET has λ = 0.01
V-1, find ro at the bias point and calculate the voltage gain.

Q12. Using an enhancement-type PMOS transistor with Vt = -1.5V, kp'(W/L) = 1mA/V2 ,


and λ = 0, design a circuit using a 10V supply design for a gate voltage of +6 V, a drain
current of 0.5mA, and a drain voltage of +5 V. Find the values of Rs and RD .

Q13. Design the circuit so that the transistor operates in saturation with VD biased 1 V from
the edge of the triode region, with ID= 1mA and VD = 3V, for each of the following two
devices (use a 10 μ A current in the voltage divider):
(a) |Vt| = 1 V and kp'W/L = 0.5 mA/V2
(b) |Vt| = 2 V and kp'W/L = 1.25 mA/V2 ; For each case, specify the values of VG , VD , Vs ,
R1 , R2 , Rs , and RD .
Q14. In the circuit, transistors Q1 &Q2 have Vt = 1 V, and the process transconductance
parameter kn' =100μA/[Link] A = 0, find V1, V2 , &V3 for each of the following cases:
(a) (W/L)1 = (W/L)2 = 20
(b) (W/L)1 = 1.5(W/L)2 = 20

Q15. For the circuits μnCox = 2.5 μpCox = 20 μA/V2, |Vt| = 1V, λ = 0, ɣ = 0, L = 10 µm, and
W = 30 µm, unless otherwise specified. Find the labelled currents and voltages.
x--------------------------------------------------x

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