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DFT and MBIST Interview Insights

The document outlines a series of technical questions related to scan insertion, design for test (DFT) processes, memory built-in self-test (MBIST) insertion, and various simulation methodologies. It addresses inputs and requirements for different testing modes, handling clock edge mixing, and the need for both serial and parallel simulations. Additionally, it touches on project experiences, ECO handling, and post-silicon debug practices.

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sharath A
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90 views1 page

DFT and MBIST Interview Insights

The document outlines a series of technical questions related to scan insertion, design for test (DFT) processes, memory built-in self-test (MBIST) insertion, and various simulation methodologies. It addresses inputs and requirements for different testing modes, handling clock edge mixing, and the need for both serial and parallel simulations. Additionally, it touches on project experiences, ECO handling, and post-silicon debug practices.

Uploaded by

sharath A
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

1) What are the inputs required for scan insertion, what are the design requirements?

2) What are the modes inserted during scan?


3) If clock edge mixing occurs, how do you handle? What about posedge, negedge triggered flops?
4) Pattern retarget flow. What kind of drc checks are checked while retarget? Can fault simulation
be done while pattern retarget?
5) Why do we need both serial and parallel simulations? What is it that parallel sims will not cover?
6) Simulation mismatches faced and debug approach
7) What is Low Power ATPG? How did you implement? How did you decide minimum toggle rate?
8) What are the inputs and requirements for MBIST Insertion?
9) What is BISR and BIRA?
10) You have mentioned about handling ECOs .. Can you share more details about it? How and what
did you cover there?
11) Can we have repairable and non-repairable memories together?

12) Can you please provide me an overview of projects worked on?

12) Details of every project – how many blocks worked on .. what was your role?
13) Pick up any projects and explain the flow and steps involved for DFT insertion
14) How many blocks did you work on in that project? What was the average turn around time for
your blocks? Till what steps do you execute the flow before releasing the block?
15) What checks do you do on pnr netlist? Have you done timing simulations? What inputs are
required for timing simulations?
16) What are the inputs required for Scan Insertion?
17) What are the inputs required for MBIST Insertion? What are some of the decisions you had to
make while doing mbist insertion? What about clocking? Did you have memories with different
clocks/clock domains?
18) What are the different modes covered in ATPG?
19) Which patterns do you write out during ATPG? Why are both serial simulations and parallel
simulations required?
20) What is the pattern retarget flow?
21) Did you have a fixed compression ratio? Was the EDT symmetric or asymmetric?
22) Have you worked on post-silicon debug?

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