Subject- VLSI Design

Subject code-BEC-401
Session-2024-25

Presented By
Prof. R. K. Chauhan
Department of Electronics and Communication Engineering
 PROBLEMS IN COMPLEX LOGIC STICK DIAGRAM
Y=AB+CD VDD Incorrect stick diagram

VDD
A A B C D
B Y K
K K
K
C D Y
Y

A C

D GND
B

Here C unnecessarily grounded rather than connected to

output Y. Diffusion break needed

The metal tracks cross which short circuit K with Y

Prof. R K. Chauhan
Deptt of ECE, MMMUT Gorakhpur
Contd….
 Reordering Polysilicon Gate and re-connect metal lines

Y=AB+CD VDD correct stick diagram

A A B D C
B Y
K K K
K
C D
Y

A C

B D

Ques - How we will rearrange polysilicon gate in more complex logic ?

Ans- Using Euler’s Path

Prof. R K. Chauhan
Deptt of ECE, MMMUT Gorakhpur
 EULER’S PATH
 The polysilicon Gate lines follow Euler’s path.
 Euler’s path is a path that is followed through different nodes where transistors are visited only once.
 The sequence of visiting transistors in Euler’s path for pull-down and pull-up if it remain same, then we can rearrange the
polysilicon gate in the order as suggested by the Euler’s path.
Y
VDD
VDD

A B A C
A B
K
K
B D
C D C D

Y
GND
Y
A C
For pull-up path For pull-down path
B D A-VDD-B-K-D-Y-C A-B-GND-D-C-Y

1. Nodes could be visited multiple times but polysilicon Gate should be visited only once.
2. If polysilicon gate order matches then we can draw stick diagram.
Prof. R K. Chauhan
Deptt of ECE, MMMUT Gorakhpur 3. In this case gate order is ABDC
 ANOTHER EXAMPLE
VDD
Y=AB+CD+EF
Euler’s Path M
VDD
For pull-up network A B

A B E F

K
K Gate sequence- A-B-D-C
D
C
Y
C D Gate sequence- E-F

M For pull-down network M

Y
E F
Y

Y A C
E

A C E
B F
D Gate sequence- E-F
Gate sequence- A-B-D-C
B D F GND
GND

Prof. R K. Chauhan Note- In the pull-down network, it is difficult to make a single Euler’s path with transversing polysilicon gate only once.
Deptt of ECE, MMMUT Gorakhpur So two separate Euler’s path drawn for both pull-up and pull-down network.
Contd…..
 The resultant stick diagram
Diffusion break
VDD
A B D C
K K M K M

GND

Conclusion- Euler’s path is useful in designing a layout with minimum diffusion breaks in complex logic circuit.
Prof. R K. Chauhan
Deptt of ECE, MMMUT Gorakhpur