UNIT-4: MSP430 MICROCONTROLLER

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Introduction to MSP430 :

▪ MSP430 family microcontrollers from Texas Instruments (TI), are designed for low
cost, low power and portable embedded applications
▪ MSP430 has 16-bit RISC based processor architecture
▪ It supports different Low power modes

Features of MSP430 :
Although there are variants in devices in the family, a MSP430 microcontroller can be
characterized by:

Device parameters
▪ Flash/ ROM options: 1 KB – 60 KB
▪ RAM options: 128 B– 8 KB
▪ GPIO options: 14 - 80 pins
Clock and Power Specifications
▪ CPU clock : 8/16/25 MHz
▪ Operating voltage : 1.8–3.6 V
▪ Active operation : 160 - 250 µA/MIPS
▪ RTC mode operation : 0.7 µA
▪ RAM retention : 0.1 μA
▪ Fast wake-up from standby mode in less than 1 µs

Other integrated peripherals

* Basic Clock system * 10/12/16-bit ADC
* I/O ports * 12-bit dual DAC
* Serial Port : SPI, I2C, UART * Op-Amp
* Timers * Comparator_A
* WDT (Watch Dog Timer ) * Temp. sensor
* RTC (Real Time Clock)
* Multiplier
* DMA
* LCD driver
* Supply Voltage Supervisor (SVS)
* Brown out Reset
* The emulator and JTAG interface
Advantages of MSP430 family :
▪ 16-bit RISC architecture
▪ High-performance - High speed of execution
▪ Low power consumption
▪ Fast wake-up from standby mode in less than 1 µs
▪ Variety of models with integrated memories, multiple programmable
GPIO and Integrated application-specific peripherals
 ▪ Cost-effective

Applications of MSP430
▪ Low power, hand-held smart devices
▪ Test and measurement equipment
▪ Smart Energy/Smart Grid solutions
▪ Factory automation
▪ Home and commercial site monitoring and control
▪ Medical instrumentation
▪ Fire and security
▪ Intelligent lighting control
▪ Transportation
▪ Motion control
▪ Automobiles
▪ Gaming equipment

Variants MSP430 MSP430 MSP430 MSP430 MSP430x

of x1xx x2xx x3xx x4xx 5xx
MSP430
family
Clock 8 MHz 16 MHz 16 MHz 16 MHz 16 MHz
Iactive 200 μA 200 μA 160 μA 200 μA 165 μA
/MIPS
IRTC mode 0.7 μA 0.7 μA 0.9 μA 0.7 μA 2.5 μA
IRAMret 0.1 μA 0.1 μA 0.1 μA 0.1 μA 0.1 μA
Wake-up < 6 µs < 1 µs < 6 µs < 6 µs < 5 µs
time
Flash/ROM 1-60KB 1-60KB 2-32 KB 4-60 KB up to
512KB
RAM 128 B - 128 B - 512 B - 256 B - up to
2KB 2KB 2KB 2KB 66KB
GPIO 10-48 10-48 14-40 14-80 32-90

MSP430 PART NUMBERING

 BLOCK DIAGRAM OF MSP430 F2013 / F2003

Introduction to MSP430 :
MSP430 family microcontrollers from Texas Instruments (TI), are designed for low
cost, low power and portable embedded applications
MSP430 has 16-bit RISC based processor architecture
It supports different Low power modes
It has 16 registers : R0-R15 . All registers are 16-bit wide
It has 16-bit Address bus and 16-bit data bus
Supports 27 core instructions, 24 emulated instructions and 7 addressing modes .
It is capable of wake-up time below 1 microsecond
Extensive vectored-interrupt capability
A wide range of on-chip peripherals are available

The functional block diagram of the MSP430 F2003/F2013 is shown in figure. The main
blocks are linked by the memory address bus (MAB) and memory data bus (MDB).

CPU :
▪ It consists of 16-bit ALU, set of 16-registers (R0 – R15) and Logic needed to
decode and execute the instructions
▪ The CPU has RISC architecture
▪ Instructions processing on either bits, bytes or words
▪ Supports 27 instructions and 7 addressing modes.
 ▪ It can address the complete address range without paging
Basic Clock system :
The clock module provides the CLK for CPU and peripherals. Three clock signals are
available from the basic clock module:
MCLK : Master clock is used by CPU and system
SMCLK : Subsystem Master clock is distributed to high speed peripherals
ACLK : Auxiliary clock is also distributed to low speed peripherals

The emulator and JTAG interface

The emulation, JTAG interface and Spy-Bi-Wire are used to communicate with a
desktop computer when downloading a program and for debugging.
Flash memory
Flash memory is used to store the programs and constant variables
RAM
RAM is used to store the temporary data (Read/Write memory) . The size of RAM in
MSP430F2003 and F2013 is 128 Bytes
16- bit Sigma Delta ADC : SD16_A
The SD16_A is a high performance 16-bit analog to digital converter used to interface
analog signals with 200 KSPS
I/O ports : P1 & P2
The MSP430 has Two I/O ports: Port-P1 and Port-P2 The Port-P1 has 8- I/O pins and
P2 has 2- I/O pins. Each I/O pin is individually configurable for input (or) output. Each pin
can be configurable for pull-up / pull-down resistors. Ports P1 and P2 have interrupt
capability.
Watch Dog Timer
▪ A watchdog timer (WDT) is an electronic timer that is used to detect and recover
from computer malfunctions. The WDT module restarts the system on occurrence
of a software problem (or) if a selected time interval expires.
▪ During normal operation, the system regularly restarts the WDT to prevent it from
elapsing, or "timing out". If the system fails to restart the WDT due to a hardware
fault (or) program error, the timer will elapse and generate a timeout signal.
▪ The timeout signal is used to initiate corrective actions like placing the system in a
safe state and restoring normal system operation.
Timer_A2
▪ Timers are essential to almost any embedded application
▪ Timers can support multiple capture/compares, PWM outputs, interval timing and
extensive interrupt capabilities
Universal Serial Interface (USI) :
The Universal Serial Interface (USI) module supports multiple serial communication modes
UART : Asynchronous, Full duplex
SPI : Serial Peripheral Interface - Synchronous, Full duplex
I2C: Serial Peripheral Interface -Synchronous, Half duplex
Brown out Reset
▪ The brownout protection comes into action if the supply voltage drops to a dangerous level
▪ The brownout reset circuit detects low supply voltages such as when a supply
voltage is applied to (or) removed from the VCC terminal.
ADDRESS SPACE / MEMORY MAPPING OF MSP430

▪ The MSP430 has Von-Neumann architecture, in which the address space is shared with
special function registers (SFRs), peripherals, RAM, and Flash/ROM memory.
▪ The data is stored in memory as Little-endian ordering, in which the low -byte of data
is stored at lower memory address and high-byte of data is stored at the higher address.

Figure : Memory map of the MSP430F2013

Special Function Registers :
▪ The SFRs are located in the lower 16 bytes of the address space.
▪ Some peripheral functions are configured in the SFRs for enabling and signaling
interrupts from peripherals.

Peripheral registers
▪ Provide the main communication between the CPU and peripherals.
▪ The address space from 0x0010 to 0x00FF is reserved for 8-bit peripheral modules.
The address space from 0x0100 to 0x01FF is reserved for 16-bit peripheral
modules.

Random Access Memory:

▪ RAM is used for storing the data variables.
▪ RAM always starts at address 0x0200 and the end address of RAM depends on the
amount of RAM present on the device.
▪ The F2013 has 128 Bytes of RAM.
Bootstrap loader (Flash devices only) :
 The MSP430 flash devices contain an address space for boot memory, located
 between addresses 0xC00 through to 0x0FFF.
 The “bootstrap loader” can be used to program the flash memory in addition to the JTAG.
 This memory region is not accessible by other applications, so it cannot be
overwritten accidentally.

Information memory (Flash devices only) :

 A 256 B block of flash memory that is intended for storage of nonvolatile data.
 This might include serial numbers to identify equipment, an address for a network,
(or) variables that should be retained even when power is removed. For example, a
printer might remember the settings from when it was last used and keep a count of
the total number of pages printed.
 Flash memory may be written one byte or word at a time, but must be erased in segments.
 The information memory is divided into 2 segments (each 128-bytes) in 4xx
devices, and 4 segments (each 64 bytes) in 2xx devices.

Flash/ROM /Code memory:

 It is used to store the program, including the executable code itself and any constant data.
 The start address of Flash/ROM depends on the amount of Flash/ROM present on
the device. The end address for Flash/ROM is 0x0FFFF for devices with less that
60KB of Flash/ROM.
 The F2013 has 2 KB but the F2003 only 1KB flash memory

Interrupt and Reset Vectors :

 Used to handle “exceptions,” when normal operation of the processor is interrupted
or when the device is reset.
 The interrupt vector table is mapped into the upper 16 words of Flash/ROM address
space, with the highest priority interrupt vector at the highest Flash/ROM word
address (0x0FFFE).

CPU ARCHITECTURE AND REGISTERS OF MSP430

The central processing unit (CPU) fetches the instructions from memory and executes the
instructions. The CPU can run at a maximum clock frequency f(MCLK) of 16MHz.

The features of MSP430 CPU are

 Constant generator provides six most used immediate values and reduces code size.
MSP430 CPU registers

 The CPU incorporates sixteen 16-bit registers:

▪ 4 registers have dedicated functions : R0, R1, R2 and R3
▪ 12 working registers for general use : R4 to R15

 The dedicated registers are

▪ R0 : Program Counter [PC]
▪ R1 : Stack Pointer [SP]
▪ R2 : Status Register [SR]
 ▪ R2/R3: Constant Generator Registers [CG1/CG2]

 The General–Purpose Registers (R4 to R15 ) :

These are used to store data values, address pointers, or index values and can be
accessed with byte or word instructions.

R0: Program Counter (PC) :

 The 16-bit Program Counter (PC/R0) points to the next instruction to be fetched
from memory and executed by the CPU.
 It is important to remember that the PC is aligned at even addresses, because the
instructions are composed of 1-3 words. Hence the LSB of PC is hard-wired to 0.
 The Program counter is incremented by the number of bytes used by the instruction
(2, 4, or 6 bytes, always even).
R1: Stack Pointer (SP) :
 The stack memory is a memory block where the data is stored in LIFO manner.
 The Stack Pointer (SP/R1) holds the address of the stack-top.
  In the MSP430, the stack is allocated at the top of the RAM and grows down
towards low addresses.
 The LSB of the stack pointer is hardwired to 0 in the MSP430, which guarantees
that it always points to valid words.

The purpose of the stack:

● It used by subroutine calls - to store the Return address (PC value)
● It is used by interrupt – to store the Return address (PC value) and Status
information (SR)
● It can be used by compiler for subroutine parameters
● It can be used by user to store data for later use by using PUSH and POP
instructions.
R2: Status Register (SR)
The Status Register (SR/R2) stores the status bits and control bits.

Status Flags: Indicate some condition produced by an instruction execution.

These are changed automatically by the CPU depending on the result of an operation.

C : Carry Flag : It is set to 1 , if a carry is generated in an Addition (or) borrow in Subtraction.

Z : Zero Flag : It is set to 1, if the result of an operation is ZERO.

A common application of Zero flag is to check whether two values are equal or not.

N : Negative Flag : It is used with signed numbers only.

N=1 for negative results and N =0 for positive results.

V: Signed overflow flag : It is used with signed numbers only

It is set to 1, when the result of a signed operation has overflowed.

Enable Interrupts :
Setting the general interrupt enable (GIE) bit enables maskable interrupts.
Clearing the bit disables all maskable interrupts.

Control of Low-Power Modes using Status Register:

The CPUOFF, OSCOFF, SCG0, and SCG1 bits control the mode of operation of
the MSP430MCU.

CPUOFF : When set, turns off the MCLK, which stops the CPU.
OSCOFF (Oscillator OFF ) : When set, turns off the VLO and LF XT1 crystal oscillator
if LFXT1-CLK is not used for MCLK or SMCLK.
SCG0 (System clock generator 0) : When set, turns off the DCO-DC generator
 if DCO-CLK is not used for MCLK.

SMCLK. SCG1 (System clock generator 1) : When set, turns off the SMCLK.
R2/R3: Constant Generator Registers (CG1/CG2)
The registers R2 and R3 are the constant generator registers, which can be used to generate
6- commonly used constants, depends on source addressing mode (As).

Addressing mode for

Regist Constan
Source
er t
operand (As)
R3 Register 0
R3 Indexed +
1
R3 Register Indirect +
2
R3 Indirect with Auto -1
increment (FFFF)
R2 Register Indirect +
4
R2 Indirect with Auto +
increment 8

The advantages of constant generators are:

▪ Reduces the code size
▪ Emulated instructions can be implemented
▪ No additional code for the six constants
▪ No code memory access required to retrieve the constant
The assembler uses the constant generator automatically if one of the 6- constants is
used as an immediate source operand.

Constant Generator - Expanded Instruction Set

The RISC instruction set of the MSP430 has only 27 core instructions.
However, the constant generator allows the MSP430 assembler to support 24 additional,
emulated instructions.
The core instructions are instructions that have unique op-codes decoded by the CPU.
The emulated instructions are instructions that make code easier to write and read, but do
not have op-codes themselves; instead they are replaced automatically by the assembler
with an equivalent core instruction.

For example, the single-operand instruction

clr.w dst is replaced by : mov.w R3, dst
; where R3=0 (Register addressing As =00)
inc.w dst is replaced by : add.w 0(R3), dst
; where 0(R3)=1 (Indexed addressing As =01)
 ADDRESSING MODES OF MSP430
Instruction is a command given to the processor to perform a specific operation on specified data.
Every instruction has 2- parts

Op-code 🡪 The operation to be done

Operand 🡪 The data to be operated

The method of specifying data to be operated by an instruction is called as addressing mode.
The MSP430 supports the following addressing
1. Register mode :
▪ In this addressing mode, the data is available in any one of the registers of CPU.
▪ This is available for both source and destination
Ex: mov.w R5, R6 ; copies word from R5 to R6

2. Register Indirect mode :

▪ In this mode, the address of the data is available in the register.
▪ Indirect register addressing is shown by the symbol @ in front of a register such as
@Rn. In other words, Rn is used as a pointer. This mode is available for only
source operand.
Ex: mov.w @R5, R6 ; load word from address (R5) into R6
If R5 = 0004 then, the content of memory address 0004 is moved to R6

3. Register Indirect with Auto-increment mode:

▪ In this addressing mode, the address of the data is available in the register and it is
automatically incremented by 1 for BYTE operation and by 2 for WORD operation.
▪ This mode is available for only source operand.
Ex: mov.w @R5+, R6 ; load word from address (R5) into R6 and increment R5
by 2.
Eg: If R5 = 0004 then, the content of memory address 0004 is moved to R6
and the pointer R5 is incremented by 2.i.e. 0006.
4. Indexed mode :
▪ In this addressing mode, the address of data is the sum of Register and Displacement
▪ This mode is available for both source and destination
Ex: mov.b 3(R5), R6 ; load byte from address (3+R5) into R6
If R5 = 0004 then, the content of memory address 0007 is moved to R6
5. Absolute mode :
▪ In this addressing mode, the absolute address of the data is available in the instruction.
▪ Absolute addressing is shown by the prefix “ & ”
▪ This mode is similar to indexed mode, in which Status Register is used as Index register.
Ex: mov.b &0245H, R6 ; copy data from memory address 0245 H into R6
The assembler replaces the above instruction by the indexed
form, where SR=0 (Constant generator)
mov.b 0245(SR), R6 ; copy data from address (SR+ 0245) to register R6

6. Symbolic mode / PC Relative :

 ▪ This mode is similar to Indexed mode, where PC is used as index register.
Hence the address of data is the sum of PC and Displacement.
▪ The assembler calculates the Displacement (relative offset address) of the data
Ex: mov.w LABLE, R6 ; load word pointed by LABLE into R6
The assembler replaces the above instruction by the indexed form
mov.w X(PC), R6 ; load word pointed by (PC+X) into R6
where X = Displacement = LABLE – PC

7. Immediate mode :
▪ In this addressing mode, the data is available immediately after the instruction.
▪ The PC is automatically incremented after the instruction is fetched and therefore
points to the following word. Hence it is a special case of Indirect auto-increment
mode.
▪ This mode is available for only source operand.

Ex: mov.w #1234, R6 ; move the immediate constant #1234 into R6.

The assembler replaces the above instruction as

mov.b @PC+, R6 ;
 INSTRUCTION FORMATS OF MSP430

Instruction is a command given to the processor to perform a specific operation on specified data.

Every instruction has 2- parts

Op-code 🡪 The operation to be done

Operand 🡪 The data to be operated

There are 3- core instruction formats of MSP430

Format-I : Instructions with Two-operands Ex: add.w R5, R6

add.w @R5, R6
add.w (R5), R6

Format-II : Instructions with Single Operand Ex: push.w R5

pop.w R6
rrc.w R5

Format-III : Jump Instructions Ex: jmp

LABEL jc
UP

Opcode : These bits represents the type of operation to be performed

S-reg : Source Operand Register [0000 for R0, …… 1111 for R15]
D-reg : Destination Operand Register [0000 for R0, …… 1111 for R15]
As : Addressing mode for Destination Operand
Ad : Addressing mode for Destination Operand
b/w: Byte / Word operation [ 0- Word , 1- Byte]
 INSTRUCTION SET OF MSP430

▪ The complete MSP430 instruction set consists of 27 core instructions and 24 emulated
instructions.
▪ The core instructions are instructions that have unique op-codes decoded by the CPU.
▪ The emulated instructions are instructions that make code easier to write and read, but
do not have op-codes themselves; instead they are replaced automatically by the
assembler with an equivalent core instruction.

1. Movement Instructions (Data Transfer)

2. Arithmetic Instructions
3. Logic Instructions
4. Shift and Rotate Instructions
5. Control Transfer instructions (Branch/Subroutine/Interrupt)

(1) Data transfer / Movement instructions

Instruction Operation Example

mov.w R5,
Copies data from source to destination
R6
1 mov.w src, dst dst 🡨 src
R6 🡨 R5
Push data onto stack
push.w R5
( first the SP is decremented by 2 and the SP 🡨 SP-2
2 push.w src source content is stored at stacktop) @ SP 🡨 R5
SP 🡨 SP-2
@ SP 🡨 src
Pop data from stack
pop.w R6
( first the content of stacktop is R6 🡨 @ SP
3 pop.w dst moved to destination and SP is SP 🡨 SP+2
incremented by 2)
dst 🡨 @ SP
SP 🡨 SP+2

(2) Arithmetic instructions

(a) Binary Arithmetic Instructions with Two operands

Instruction Operation Example

Add the content of source to destination
1 add.w src, dst add.w R5, R6
dst 🡨 dst + src

Add with carry

2 addc.w src, dst addc.w R5, R6
dst 🡨 dst + (src + C)

Add carry bit to the destination

3 adc.w dst adc.w R6
dst 🡨 dst + C

Subtract the content of source from

4 sub.w src, dst destination sub.w R5, R6
dst 🡨 dst - src
Subtract with borrow
5 subc.w src, dst subc.w R5, R6
dst 🡨 dst –( src + C)

Subtract borrow bit from the destination

6 sbc.w dst sbc.w R6
dst 🡨 dst – C
Compares source and destination.
Performs ( dst – src), but Only flags are
7 cmp.w src,dst changed If dst > src cmp.w R5,R6
: C=0, Z=0
If dst < src : C=1, Z=0
If dst = src : C=0, Z=1

(b) Arithmetic Instructions with One operand :

All these instructions are emulated, which means that the operand is always a destination

Instruction Operation Example

Clear destination clr.w R6

1 clr.w dst
dst 🡨 0 R6 🡨 0

The content of destination is decremented by dec.w R6

2 dec.w dst
1 R6 🡨 R6 -
dst 🡨 dst – 1 1
Double decrement
decd.w R6
3 decd.w dst The content of destination is decremented by 2
R6 🡨 R6 –
dst 🡨 dst – 2 2
The content of destination is incremented by 1 inc.w R6
4 inc.w dst
dst 🡨 dst + 1 R6 🡨 R6 +
1
Double increment
incd.w R6
5 incd.w dst The content of destination is incremented by 2
R6 🡨 R6 +
dst 🡨 dst + 2 2
Test ( compare with zero)
Performs ( dst – 0), but Only flags are changed
6 tst.w dst If dst > 0 : C=0, Z=0 tsd.w R6
If dst < 0 : C=1,
Z=0 If dst = 0
: C=0,
Z=1

(c) Decimal Arithmetic Instructions :

These instructions are used to perform BCD addition
Instruction Operation Example
 Performs the decimal addition of
dadd.w R5, R6
1 dadd.w src, destination and source with carry
dst R6 🡨 R6 +
dst 🡨 dst + src + C R5+C
Performs the decimal addition of
dadc.w R6
2 dadc.w dst destination and carry.
R6 🡨 R6 + C
dst 🡨 dst + C

(3) Logic instructions

(a) Logic Instructions with Two operands

Instruction Operation Example
Performs bit-wise logic AND operation
1 and.w src, dst and.w R5, R6
dst 🡨 dst AND src
Performs bit-wise logic Ex-OR operation
2 xor.w src, dst xor.w R5, R6
dst 🡨 dst XOR src
Performs bit-wise Test operation
3 bit.w src, dst It performs Logic AND operation, But Only bit.w R5, R6
flags are affected
Set bits in destination
The source operand and the destination
4 bis.w src, dst operand are logically ORed. The result is bis.w R5, R6
placed into the destination. The source
operand is not affected.
dst 🡨 dst OR src
Clear bits in destination
The inverted source operand and the
5 bic.w src, dst destination operand are logically ANDed. bic.w R5, R6
The result is placed into the destination.
dst 🡨 dst AND ~src

(b) Logic Instructions with ONE operand

Instruction Operati Example
on
Invert destination
1 inv.w dst Performs bit-wise NOT operation (1’s inv.w R6
complement)
dst 🡨 ~dst

(c) Byte manipulation

Instruction Operation Example
Swap upper and lower bytes
The high and the low byte of the
1 swpb dst swpb
operand are exchanged R6
dst.15:8 ↔ dst.7:0
Extend sign of lower byte
The sign of the low byte of the operand is
 extended into the high byte
2 sxt dst sxt
dst. 15:8 🡨 dst.7 R6
If dst.7 = 0: high byte = 00 H afterwards
If dst.7 = 1: high byte = FF H afterwards
(d) Operations on Bits in Status Register
These instructions are used to set or clear the flags in Status
Register. All these instructions are emulated instructions.

Instruction Operation Example

1 clrc Clear Carry bit C=0
2 clrn Clear Negative bit N=0
3 clrz Clear Zero bit Z=0
4 setc Set Carry bit C=1
5 setn Set Negative bit N=1
6 setz Set Zero bit Z=1
7 dint Disable General Interrupts GIE
=0
8 eint Enable General Interrupts GIE
=1

(4) Shift and Rotate instructions

Instructio Description Operation
n

rla dst Arithmetic shift

Left

Arithmetic
rra dst shift Right

rlc dst Rotate Left

through Carry

Rotate Right
rrc dst
through Carry

(5) Control Transfer instructions

 Instruction Operatio Example
n
1 br Branch ( go to) PC 🡨 src
src
SP 🡨 SP-2
2 call src Call Subroutine
@ SP 🡨 PC

PC 🡨 @ SP
3 ret Return from Subroutine
SP 🡨 SP+2
SR 🡨 @ SP
Return from Interrupt SP 🡨 SP+2
4 reti
PC 🡨 @ SP
SP 🡨 SP+2
No operation
5 nop
( consumes single cycle )
JUMP Instructions Condition

Jump to specified
1 jmp label Unconditional Jump
location

2 jc / jlo label Jump if carry / Jump if lower Jump if C =1

3 jnc / jhs label Jump if not carry / Jump higher or same Jump if C =0

4 jz / jeq label Jump if zero / Jump if equal Jump if Z =1

5 jnz / jne label Jump if not zero / Jump if not equal Jump if Z =0

6 jn label Jump if negative Jump if N =1

7 jge label Jump if greater or equal (signed values) Jump if (N xor V)

=0

8 jl Jump if less than (signed values) Jump if (N xor V)

labe =1
l
 I/O PORTS (GPIO PINS)

▪ MSP430x5xx devices have up to 12 digital I/O ports : P1 to P12

▪ Most ports have 8- I/O pins, however some ports may contain less.

▪ Each I/O pin is individually configurable for input (or) output direction, and each
I/O line can be individually read or written to.
▪ Ports P1 and P2 always have interrupt capability.

▪ All ports have individually configurable pull-up (or) pull-down resistors

▪ Individual ports can be accessed as Byte wide ports (or) can be combined into Word
wide ports i.e PA= P1&P2, PB = P3&P4 …etc
Each port is assigned several 8-bit registers that control the function of the pins

Port Control Description

Register
PxSEL Selects either digital I/O (or) an alternate function
(Port Selection) 0 - digital I/O 1- Alternate function
PxDIR Configures the pin for input mode (or) output mode
(Port Direction) 0 - input mode 1- output mode
PxIN
(Port Input) Read data from input port pins, if they are configured as
GPIO
PxOUT
(Port Output) Send data to output port pins, if it is configured as GPIO
Enables pull-up / pull-down resistors on input pins.
PxREN
(Port Resistor 1 → Enables pull-up / pull-down resistors
Enable) 0 → Disables pull-up / pull-down resistors

If the pin is configured in input mode and PxREN is enabled then,

PxOUT register selects whether the resistors are pull-up (1) or pull-down (0)

PxDIR PxRE PxOUT I/O Configuration

N
0 0 x Input
0 1 0 Input with Pull-down
0 1 1 Input with Pull-UP
1 x x Output

Some GPIO pins of MSP430 have interrupt capability, typically on Ports 1 and Port 2 pins.
The registers controlling these options are as follows

Port Control Register Description

Enable or Disables the interrupt for that particular pin
PxIE (Interrupt Enable)
1 – Enable 0- Disable the Interrupt
Selects either falling-edge (or) rising-edge interrupt
PxIES (Interrupt Edge
Select) 1 – falling edge 0- rising edge
Set whenever the interrupt is detected
PxIFG (Interrupt Flag)
on a particular pin

PULL-UP & PULL-DOWN RESISTORS CONCEPTS

▪ The Pull-up and Pull-down resistors are used to maintain proper logic levels at input
pins under all conditions.
▪ When no external devices are connected to an input pin, it doesn't mean that it is a
logical ‘ZERO'. Hence, Pull-up and Pull-down resistors ensure that the inputs to the
micro-controller settle at expected logic levels, if external devices are disconnected (or)
high-impedance.

✔ Pull-up resistors are used to pull-up the logic level at the input pin to logic ‘HIGH’
state, as shown in the Fig.(a). If there was no pull-up resistor, the MCU’s input
would be floating when the switch is open.

✔ Pull-down resistors are used to pull-down the logic level at input pin to logic
‘LOW’ state, as shown in the Fig.(b). If there was no pull-down resistor, the MCU’s
input would be floating when the switch is open.

✔ Pull-up and pull-down resistors are often used when interfacing a switch or some
other input with a microcontroller. Hence, most microcontrollers have internal pull
up/down resistors to reduce the no. of external components.
 Pull-up or pull-down resistors can be activated by setting bits in the PxREN registers,
provided that the pin is configured as an input.

Application of Pull up/down Resistors:

(1) Interfacing of switches / other input devices with microcontrollers
(2) Interfacing of A/D converters
(3) I2C protocol bus

BASIC TIMER_1

The Basic Timer1 supplies LCD timing and low frequency time intervals. The Basic Timer1 is two
independent 8-bit timers that can also be cascaded to form one 16-bit timer function.

Some of the features of Basic Timer1 include:

▪ Real-time clock (RTC) function
▪ Software time increments
▪ Selectable clock source
▪ Two independent, cascadable 8-bit timers
▪ Interrupt capability
▪ LCD control signal generation

Basic Timer1 Operation

✔ The Basic Timer1 module can be configured as two 8-bit timers with the BTCTL register.
✔ The BTCTL is an 8-bit read/write Basic Timer Control Register. Any read or write
access must use byte instructions.
✔ The Basic Timer1 controls the LCD frame frequency with BTCNT1.
 BTCNT1 ( Basic Timer Counter-1) :

✔ BTCNT1 is an 8-bit timer/counter directly accessible by software.

✔ BTCNT1 is incremented with ACLK and provides the frame frequency
for the LCD controller.
✔ BTCNT1 can be stopped by setting the BTHOLD and BTDIV bits.

BTCNT2 ( Basic Timer Counter-2) :

✔ BTCNT2 is an 8-bit timer/counter directly accessible by software.
✔ BTCNT2 can be sourced from ACLK or SMCLK, or from ACLK/256 when
cascaded with BTCNT1.
✔ The BTCNT2 clock source is selected with the BTSSEL and BTDIV bits.
✔ BTCNT2 can be stopped to reduce power consumption by setting the HOLD bit.
✔ BTCNT2 sources the Basic Timer1 interrupt, BTIFG.
✔ The interrupt interval is selected with the BTIPx bits

16- Bit
Counter Mode :
✔ The 16-bit timer/counter mode is selected when control the BTDIV bit is set.
✔ In this mode, BTCNT1 is cascaded with BTCNT2.
✔ The clock source of BTCNT1 is ACLK, and the clock source of BTCNT2 is ACLK/256.

Basic Timer1 Control Register ( BTCTL) :

7 6 5 4 3 2 1 0
BTSSEL BTHOL BTDI BTFREQx BTIPx
D V
 This bit, together with the BTDIV bit,
Bit 7 BTSSEL BTCNT2 clock
select selects the clock source for BTCNT2.

Bit 6 BTHOL Basic Timer1 Stops BTCNT1 & BTCNT2

D hold
Bit 5 BTDIV Basic Timer1 This bit together with the BTSSEL bit,
clock divide selects the clock source for BTCNT2.
These bits control the LCD update frequency
0 🡪 fACLK/32
Bits 4- BTFRFQ fLCD frequency 01 🡪 fACLK/64
3 x 10 🡪 fACLK/128
11 🡪 fACLK/256
0 🡪 fCLK2/2
01 🡪 fCLK2/4

Basic Timer1 010 🡪 fCLK2/8

Bits 2- BTIPx interrupt 011 🡪 fCLK2/16
0 interval 100 🡪 fCLK2/32
101 🡪 fCLK2/64
110 🡪 fCLK2/128
111 🡪 fCLK2/256

BTSEL BTDIV Clock source

0 0 ACLK
0 1 ACLK/128
1 0 SMCLK
1 1 ACLK/256
 TIMER_A/B

1. Timer_A is a 16-bit timer/counter with 4- operating modes

2. Supports multiple capture/compare registers ( up to 7 CC registers)
3. Timer_A also has extensive interrupt capabilities.
4. Selectable and configurable clock source
5. Configurable outputs with 8 – output modes
6. PWM capability
7. Interrupt vector register for fast decoding of all Timer_A interrupts

Timer block:
▪ Timer block consists of 16-bit counter named as Time_A register (TAR) which
increments or decrements (depending on mode of operation) with each
rising edge of the clock signal.
▪ Selectable clock sources - TACLK, ACLK, SMCLK, INCLK
▪ The timer can generate an interrupt TAIFG when it overflows.
▪ TAR may be cleared by setting the TACLR bit.
▪ It is controlled by the Timer_A control register TACTL.

Timer Modes :

The timer has 4- modes of operation, can be selected with the MCx bits of TACTL.
 MC Mode Description
x
00 Stop The timer is halted
01 Up Counts from zero to TACCR0.
10 Continuo Counts from zero to 0FFFFh
us
11 Up/down Counts from zero to TACCR0 and back down to
zero

Stop mode (MCx = 00):

▪ The timer is halted.

▪ All registers, including TAR, retain their values so that the timer can be restarted
later where it left off.

Up Mode (MCx = 01):

▪ The timer repeatedly counts from zero to the value of TACCR0.

▪ The period is (TACCR0+1) counts.
▪ For ex., if TACCR0 = 4, the sequence of counts is 0, 1, 2, 3, 4, 0, 1,2,3,4,0,1,2....
▪ The TACCRx CCIFG interrupt flag is set when the timer counts to the TACCRx value.
▪ The TAIFG interrupt flag is set when the timer counts from TACCRx to zero.

Continuous Mode (MCx = 10):

▪ The timer repeatedly counts from zero to 0FFFFh.

▪ The period is 65,536 counts
▪ The TAIFG interrupt flag is set when the timer counts from 0FFFFh to zero.
Up/Down Mode (MCx = 11):

▪ The timer repeatedly counts from zero up to the value of TACCR0 and back down to zero.
▪ The period is 2*TACCR0 counts.
▪ For example, if TACCR0=4, the sequence of counts is 0, 1, 2, 3, 4, 3, 2, 1, 0,1, 2,. .. .
▪ The TACCR0 CCIFG flag is set when the timer counts from TACCR0-1 to
TACCR0, and TAIFG is set when the timer completes counting down from
0001h to 0000h.
▪ The up/down mode is used, if symmetrical pulse generation is needed.

Capture/compare channels :
The times have capture /compare channels, which can be used
1. Capture an input, which means recording the “time” (the value in TAR) at
which the input changes in TACCRn; the input can be either external or
internal from another peripheral or software.
2. Compare the current value of TAR with the value stored in TACCRx and
update an output when they match; the output can again be either external
or internal.
3. Request an interrupt by setting its flag CCIFG on either of these events;
this can be done even if no output signal is produced.
4. Sample an input at a compare event; this special feature is useful if Timer_A
is used for serial communication in a device that lacks a dedicated interface.

Capture Mode

▪ The capture mode is selected when CAP = 1.

▪ Capture mode is used to record time events.
▪ It can be used for speed computations or time measurements.
▪ The CMx bits select the capture edge of the input signal as rising, falling, or both.
▪ The capture inputs CCIxA and CCIxB are connected to external pins or internal
signals and are selected with the CCISx bits.
▪ If a capture occurs:
✔ The timer value is copied into the TACCRx register
✔ The interrupt flag CCIFG is set
▪ Overflow logic is provided in each capture/compare register to indicate if a second
capture was performed before the value from the first capture was read. Bit
COV is set when this occurs.

▪ The capture signal can be asynchronous to the timer clock and cause a race
condition. Setting the SCS bit will synchronize the capture with the next timer
clock. Setting the SCS bit to synchronize the capture signal with the timer clock is
recommended. This is illustrated in the following figure.

Compare Mode
 ▪ The compare mode is selected when CAP = 0.
▪ The compare mode is used to generate PWM output signals or interrupts at
specific time intervals.
▪ When TAR counts to the value in a TACCRx:
✔ Interrupt flag CCIFG is set
✔ EQUx affects the output according to the output mode
✔ The input signal CCI is latched into SCCI

Output Unit
▪ Each capture/compare block contains an output unit.
▪ The output unit is used to generate output signals such as PWM signals.
▪ Each output unit has 8- operating modes, defined by the OUTMODx bits.

OUTMODx Mode Description

000 Outp The output signal OUTx is defined by the OUTx bit.
ut
The output is set when the timer counts to the TACCRx value. It
001 Se remains set until a reset of the timer, or until another output
t mode is selected.
The output is toggled when the timer counts to the TACCRx
010 Toggle/ value.
Reset It is reset when the timer counts to the TACCR0 value.
The output is set when the timer counts to the TACCRx value.
011 Set/Reset
It is reset when the timer counts to the TACCR0 value.
The output is toggled when the timer counts to the TACCRx
100 Toggl
e value. The output period is double the timer period.
The output is reset when the timer counts to the TACCRx value.
101 Res
et It remains reset until another output mode is selected.
The output is toggled when the timer counts to the TACCRx value.
110 Toggle/ It is set when the timer counts to the TACCR0 value.
Set
The output is reset when the timer counts to the TACCRx value.
111 Reset/Set
It is set when the timer counts to the TACCR0 value
 Output Example — Timer in Up Mode
The OUTx signal is changed when the timer counts up to the TACCRx value, and rolls from
TACCR0 to zero, depending on the output mode. An example is shown in Figure 12-12 using
TACCR0 and TACCR1.

Output Example — Timer in Continuous Mode

The OUTx signal is changed when the timer reaches the TACCRx and TACCR0 values,
depending on the output mode. An example is shown in Figure 12-13 using TACCR0 and
TACCR1.
 Output Example — Timer in Up/Down Mode

The OUTx signal changes when the timer equals TACCRx in either count direction and
when the timer equals TACCR0, depending on the output mode. An example is shown in
Figure 12-14 using TACCR0 and TACCR2.
Timer_A Registers :

Register Short Register

Form Type
Timer_A control TACTL Read/write
Timer_A counter T Read/write
A
R
Timer_A capture/compare control x ( x= 0,1,2…) TACCTL Read/write
x
Timer_A capture/compare x ( x= 0,1,2…) TACCRx Read/write
Timer_A interrupt vector TAIV Read only
TACTL (Timer_A control register)

Bit 15- UNUSE

10 D
0 TACLK
Timer_A 01 ACLK
Bits 9-8 TASSEL
x clock 10 SMCLK
source 11 INCLK
select
00🡪 /1
Bits 10-9 IDx Input divider 01🡪 /2
10 🡪 /4
11 🡪 /8
0 🡪 Stop mode (halt)
01 🡪 Up mode ( 0 to TACCR0)
Bits 5-4 MCx Mode control 10 🡪 Continuous mode (0 to 0FFFF)
11 🡪 Up/down mode (the timer counts
up to TACCR0 then down to 0000)
Setting this bit resets TAR, the clock
Bit 2 TACLR Timer_A clear.
divider, and the count direction
Timer_A 0 🡪 Interrupt disabled
Bit 1 TAIE interrupt 1 🡪 Interrupt enabled
enable
Timer_A 0 🡪 No interrupt pending
Bit 0 TAIFG interrupt flag 1 🡪 Interrupt pending
 PWM OUTPUT

▪ The idea behind PWM is very simple: The load is switched on and off periodically
so that the average voltage has the desired value.
▪ The fraction of the time while the load is active is called the duty cycle D.
▪ The duty cycle is almost always varied by keeping the period constant and changing
the width of the pulses, hence the name of PWM.

▪ The period of Timer_A is set by TACCR0 in the Up mode.

▪ TAR counts from 0 up to the value in TACCR0, and returns to 0 to for the next clock
▪ The period is therefore TACCR0 + 1

▪ The flag CCIFG0 is set when TAR counts to TACCR0 and the TAIFG flag is
set when TAR returns to 0, one cycle later.
▪ The flag CCIFG1 is set when TAR counts to TACCR1, which is 60 here.

▪ There are two main parameters be chosen for PWM output.

(a) The time period of the output PWM waveform T0 = [TACCR0 +1] TCLK
Pulse width Time Period =
(b) Duty cycle
TAC
CR1
of PWM

TAC
output D =

CR0
+1
▪ Now, the average voltage across the output is given by

VAvg 𝐓𝐀𝐂𝐂𝐑𝟏
𝐓𝐀𝐂𝐂𝐑𝟎+𝟏
=D VCC
VCC =
This means that, by changing the value in TACCR1, we can change the duty cycle. The
above Figure shows that, the Reset/Set output mode (7) is used for active high loads, called
as positive PWM and the Set/Reset mode (3) is used for active low loads, called as negative
PWM.

MEASUREMENT OF TIME & FREQUENCY IN CAPTURE MODE

The Capture mode is used to take a time stamp of an event, and to note the time at which it
occurred. The timer usually runs in the Continuous mode for captures because this makes
it easy to calculate differences of times when TAR has rolled over between them.

(a) Measurement of duration and Time period :

▪ In most cases the timer clock is either ACLK or SMCLK, whose frequency is
known, and the unknown signal is applied to the capture input.
▪ To measure the duration of the pulse, we should capture both rising and falling
edges and subtract the captured times.
▪ To measure the time period of the signal, we might capture only the rising edges
(or falling if preferred) and the difference gives the period directly.

(b) Measurement of frequency :

▪ The signal is used as the timer clock (TACLK) and the edges of ACLK are
captured whose frequency is known.
▪ The difference between the captured value gives the number of cycles of the
signal in one cycle of ACLK. This gives the frequency rather than the period.

Here are a few examples of the use of the Capture mode:

▪ Many speed sensors produce no. of pulses per revolution. The Capture mode is used
 to measure the period between pulses to determine the speed.
▪ Some sensors encode their outputs as a frequency, length of a pulse, or the duty
cycle of a square wave, the fraction of the time during which the signal is high.
▪ The delay between transmission and reception of an ultrasonic pulse is measured in
the range finder application -Ultrasonic Distance Measurement with the MSP430.
▪ Similarly, the inverting input V− can be connected to external signals CA1–CA7 or
left unconnected, according to bits P2CA3 – P2CA1.
▪ The output of the comparator can be used with or without internal filtering. When
control bit CAF is set, the output is filtered with an on-chip RC-filter to reduce
oscillations in the signal.
▪ The output is brought to an external pin CAOUT. It is also connected internally to
capture input CCI1B of Timer_A, which allows precise timing without delays.
▪ The flag CAIFG is raised on either a rising or falling edge of the comparator output,
selected with the CAIES bit. This can in turn request an interrupt if CAIE is set.
Comparator_A has its own interrupt vector and the flag is cleared automatically
when the interrupt is serviced.

COMPARATOR_A CONTROL REGISTER (CACTL)

Comparator This bit exchanges the comparator inputs

Bit 7 CAEX
_A and inverts the comparator output.
exchange

Comparator This bit selects terminal for Reference

Bit 6 CARSEL voltage 0 🡪 VCAREF is applied to the +
_A reference
terminal
select
1 🡪 VCAREF is applied to the – terminal
These bits select the reference voltage VCAREF.
00 🡪 Internal reference off.
An external reference can be applied.
Bits 5-4 CAREF Comparator
01 🡪 0.25*VCC
_A
10 🡪 0.5 *VCC
reference
11 🡪 Diode reference is selected
0 🡪 Comparator OFF : ; 1 🡪 Comparator ON
Bit 3 CAON Comparator_A on.
Comparator_A 0 🡪 Rising
Bit 2 CAIES
interrupt edge edge 1 🡪
select Falling edge
Comparator_ 0 🡪 Disabled , 0 🡪 Enabled
Bit 1 CAIE
A interrupt
enable
The 0 🡪 No interrupt pending
Bit 0 CAIFG
Comparator_A 1 🡪 Interrupt pending
interrupt flag
 THE ADC10 : SUCCESSIVE APPROXIMATION ADC

▪ The ADC10 module supports fast, 10-bit analog-to-digital conversions.

▪ The module implements a 10-bit SAR core, sample select control, reference
generator, and data transfer controller (DTC).
▪ The DTC allows ADC10 samples to be converted and stored anywhere in memory
without CPU intervention.

ADC10 features include:

✔ Greater than 200 Ksps maximum conversion rate

✔ Sample-and-hold with programmable sample periods
✔ Conversion initiation by software or Timer_A
✔ Software selectable internal or external reference
✔ Software selectable on-chip reference voltage generation (1.5 V or 2.5 V)
✔ Up to 12- external input channels
✔ Conversion channels for internal temperature sensor, VCC, and external references
✔ Selectable conversion clock source
✔ Single-channel, repeated single-channel, sequence, & repeated sequence conversion modes.
✔ ADC core and reference voltage can be powered down separately
✔ Data transfer controller (DTC) for automatic storage of conversion results
10- Bit ADC Core :
The ADC core converts an analog input to its 10-bit digital representation and
stores the result in the ADC10MEM register. Conversion results may be in straight
binary format or 2’s complement format. The conversion formula for the ADC
result when using straight binary format is:

Conversion Clock Selection

The ADC10CLK is used both as the conversion clock and to generate the sampling
period. The ADC10 source clock is selected using the ADC10SSELx bits and can
be divided from 1-8 using the ADC10DIVx bits.
Possible ADC10CLK sources 🡪 SMCLK, MCLK, ACLK , internal oscillator ADC10OSC.

ADC10 Inputs and Multiplexer

The 8-external and 4-internal analog signals are selected for the conversion by the
analog input multiplexer (INCHx). The input multiplexer is a break-before-make
type to reduce input-to-input noise injection resulting from channel switching

Voltage Reference Generator

The ADC10 module contains a built-in voltage reference with two selectable
voltage levels. Setting REFON = 1 enables the internal reference.
When REFOUT =0, externally on pin VREF+.

Sample and Conversion Timing

An analog-to-digital conversion is initiated with a rising edge of sample input
signal, selected with the Sample and Hold source (SHSx) bits - ADC10SC,
Timer_A outputs OUT1, OUT2, OUT3.

Conversion Sequence Modes :

CONSE Mo Operati
Qx de on
00 Single channel single- Single channel is converted once.
conversion
01 Sequence of channels Sequence of channels is converted once
10 Repeat single channel Single channel is converted repeatedly
11 Repeat sequence of channels Sequence of channels is converted
repeatedly

ADC10 Data Transfer Controller

The ADC10 includes a data transfer controller (DTC) to automatically transfer
conversion results from ADC10MEM to other on-chip memory locations.
 Within a micro-computer system, the data transfer is in parallel because it is the
INTRODUCTION TO SERIAL COMMUNICATION
fastest method. But transferring the data over long distances, the parallel data transmission
requires too many wires and it is complicated and expensive. Therefore, the data to be sent
for long distances is converted into serial form so that it can be sent on a single wire. At the
destination, the received serial data is converted into parallel form so that it can be easily
transferred on the micro-computer buses.

Methods of serial data transmission:

(i) Simplex :

In this mode, the data is transmitted only in one

direction over a single communication channel.

Ex: CPU to CRT display, Key board to CPU, Radio signal

(ii) Half-duplex :

In this mode, the data is transmitted in both

directions, but only one direction at a time.
i.e., simultaneous data transfer is not possible.

Ex: Walkie Talkie

(iii) Full-duplex :

In this mode, the data transmission takes place in

both directions simultaneously.
It requires two channels.

Ex: Telephone communication

Synchronous Vs Asynchronous data transfer modes:

Synchronous data transmission Asynchronous data transmission

Transmitter and Receiver are Transmitter and Receiver can

operated with same CLK frequency. operated with different CLK
frequency.
SYNC pulses are required
START and STOP bits are required
A group of characters can be
transmitted after sending the SYNC For each character, the START &
pulses STOP bits are required.

It is used in high speed data transmission. It is used in low speed data transmission.

Generally used between CPU and It is used to exchange data with

other devices on the same PCB, as the other equipment such as PC.
same power supply and CLK are used.

Ex: SPI, I2C Ex: UART

Serial Communication Protocols :

The universal serial communication interface (USCI) module of MSP430 supports

multiple serial communication modes. The THREE common types of serial
communication protocols are
▪ Asynchronous serial communication (UART)
▪ Serial peripheral interface (SPI).
▪ Inter-integrated circuit (I²C) bus.

Universal Asynchronous Receiver / Transmitter (UART)

▪ It is an Asynchronous - Full duplex Serial communication protocol
▪ No CLK signal is transmitted along with data
▪ UART requires 2- signal lines for communication
▪ TxD - Transmit data, RxD – Receive data

Serial Peripheral Interface (SPI) :

▪ It is a Synchronous - Full duplex Serial communication protocol
▪ CLK signal is transmitted along with data
▪ It is a 4-wire communication ( 3-pin SPI mode and 4-pin SPI modes)
▪ SPI requires 4- signal lines for communication: MOSI - Master out slave in
MISO - Master in slave out
SCLK – Serial Clock
SS - Slave select

Inter Integrated Circuit (I2C) :

▪ It is a Synchronous - Half duplex Serial communication protocol
▪ CLK signal is transmitted along with data
▪ It is often called as 2-wire interface
▪ The I²C bus uses only two bidirectional lines for communication SDA -
Serial data
SCL – Serial Clock

✔ SPI and I²C have similar applications. SPI and I²C are often used to communicate with

▪ Port expanders to increase the effective no. of pins for digital I/O.
▪ ADCs and DACs.
▪ Sensors with digital outputs, such as thermometers.
▪ External memory (data flash, EEPROM).
▪ Real-time clocks.
▪ Interfacing of other processors.
 INTER INTEGRATED CIRCUIT (I2C) BUS

Inter Integrated Circuit (I2C) :

▪ It is a Synchronous - Half duplex Serial communication protocol
▪ CLK signal is transmitted along with data
▪ It is often called as 2-wire interface
▪ The I²C bus uses only two bidirectional lines for communication
SDA - Serial data
SCL – Serial Clock

Hardware for I²C

▪ The electronic interface to the I²C bus is shown in figure for a master and two slaves.
▪ The transfers on the bus take place between a master and selected slave.
▪ Each slave has a unique address, which is usually 7 bits long.
▪ The master starts the transfer, provides the clock, addresses a particular slave,
manages the transfer, and finally terminates it.
▪ There may be more than one master on the bus, but only one can be in control at a time.

▪ The pull-up resistor RP holds the line at VCC when there is no activity.
▪ Hence, both the clock and data lines are at HIGH. If a single n-MOSFET is
turned on, its line is pulled down to logic 0.
USCI - I2C Mode

▪ In I2C mode, the USCI module provides an interface between the MSP430 and I2C-
compatible devices connected by way of the two-wire I2C serial bus.
▪ External components attached to the I2C bus serially transmit and/or receive serial
data to/from the USCI module through the 2-wire I2C interface.
▪ The I2C mode features include:
1. 7-bit and 10-bit device addressing modes
2. Multi-master transmitter/receiver mode
3. Slave receiver/transmitter mode
4. Standard mode up to 100 kbps and fast mode up to 400 kbps support
5. Programmable UCxCLK frequency in master mode
6. Designed for low power
7. Slave receiver START detection for auto-wake up from LPMx modes
8. Slave operation in LPM4
USCI Operation: I2C Mode

▪ The I2C mode supports any slave or master I2C-compatible device.

▪ Each I2C device is recognized by a unique address and can operate as either a
transmitter or a receiver.
▪ The master initiates a data transfer and generates the clock signal SCL. Any
device addressed by a master is considered a slave.
▪ I2C data is communicated using the serial data pin (SDA) and the serial clock pin (SCL).
▪ Both SDA and SCL are bidirectional, and must be connected to a positive supply
voltage using a pull-up resistor.
▪ The clock source can be selected from ACLK, SMCLK, and UC1CLK

A simple example of a transfer on I²C is shown in above, where the master reads a single
byte from the slave. Transfers consist of a sequence of 8-bit bytes, which are sent with the
MSB first and must be acknowledged to confirm successful reception.

The steps involved in a simple transfer over I2C bus

1. The master sends a start condition (S) by pulling SDA low while SCL is high.
2. The master sends the 7-bit slave address to select a slave
3. The master sends the control bit to select the Read(1) / Write(0) operation.
4. The selected slave will send the acknowledgment (A)
5. After receiving ACK from selected slave, the data transfer takes place for next 8-clock pulses.
6. After the transfer of 8-bits, the receiver sends the ACK
7. Finally, the master sends the stop condition (P) by pulling SDA high while SCL is high.
UCAxCTL0 (USCI_Ax Control Register 0) in I2C mode :

7 6 5 4 3 2 1 0

UCA UCSL UCM -- UCM UCMODEx = UCSYN

10 A10 M ST 11 C=1

Own 0 🡪 Own address is a 7-bit

Bit UCA10
7 Address address 1 🡪 Own address is a
mode 10-bit address
select
Slave 0 🡪 Address slave with 7-bit
Bit UCSLA1 addressing address 1 🡪 Address slave with
6 0
mode 10-bit address
select
Multi- 0 Single master environment.
Bit UCMM master
5 1 Multi- master environment
environment
select

Bit NOT USED

4
Master 0 🡪 Slave mode
Bit UCMST mode
3 1 🡪 Master mode
select
If UNSYNC = 1
then 00 🡪 3-pin
Bit UCMODE USCI mode. SPI
2-1 x
01🡪 4-pin SPI with UCSTE active high
10 🡪 4-pin SPI with UCSTE active high
11🡪 I2C
Synchron 0 🡪 Asynchronous mode
Bit UCSYN
0 C ous mode 1 🡪 Synchronous mode
enable