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Hi-Skew and Lo-Skew Gate Analysis

The document outlines a tutorial for CMOS VLSI Design, focusing on various design tasks including delay calculations using the Elmore delay model, estimating gate delays, and designing circuits with specific requirements. It includes exercises on creating schematics for gates, optimizing transistor sizes for minimal delay, and analyzing logical efforts of different gate configurations. The tutorial emphasizes practical design considerations for a 64-bit datapath and various gate types.

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Yashaswini M
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79 views1 page

Hi-Skew and Lo-Skew Gate Analysis

The document outlines a tutorial for CMOS VLSI Design, focusing on various design tasks including delay calculations using the Elmore delay model, estimating gate delays, and designing circuits with specific requirements. It includes exercises on creating schematics for gates, optimizing transistor sizes for minimal delay, and analyzing logical efforts of different gate configurations. The tutorial emphasizes practical design considerations for a 64-bit datapath and various gate types.

Uploaded by

Yashaswini M
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

Tutorial – 4

CMOS VLSI Design (EC53)


2023 - 2024

1.

Using the Elmore delay model, calculate the delay from A to each of the outputs. Thereby
determine the critical path and its delay.
2. Some designers define a “gate delay” to be a fanout-of-3 2-input NAND gate rather
than a fanout-of-4 inverter. Using Logical Effort, estimate the delay of a fanout-of-3 2-input
NAND gate.
3. A control unit generates a signal from a unit-sized inverter. The signal must drive
unit-sized loads in each bitslice of a 64-bit datapath. The designer can add inverters to
buffer the signal to drive the large load. Assuming polarity of the signal
does not matter, what is the best number of inverters to add and what delay can
be achieved?
4. Sketch a schematic for a 12-input OR gate built from NANDs and NORs of no
more than three inputs each.
5. Design a static CMOS circuit to compute F = (A + B)(C + D) with least delay. Each
input can present a maximum of 30 λ of transistor width. The output must drive a
load equivalent to 500 λ of transistor width. Choose transistor sizes to achieve least
delay and estimate this delay in Tau.
6. Sketch HI-skew and LO-skew 3-input NAND and NOR gates. What are the logical efforts of
each gate on its critical transition?
7. Design an asymmetric 3-input NOR gate that favors a critical input over the other two.
Choose transistor sizes so the logical effort on the critical input is 1.5. What is the logical
effort of the noncritical inputs?
8. Sketch pseudo-nMOS 3-input NAND and NOR gates. Label the transistor
widths. What are the rising, falling, and average logical efforts of each gate?

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