RAJ KUMAR GOEL INSTITUTE OF

TECHNOLOGY , Ghaziabad
Computer Organization And Architecture
BCS-302

Unit: V

COA

Dr. Vinish Kumar

B Tech :3th Sem Professor
CSE(AI&ML)
 Course Outcomes
Course outcome: After completion of this course students will be able
to:

Study of the basic structure and operation of a

CO 1 K1, K2
digital computer system.
Analysis of the design of arithmetic & logic unit
CO 2 and understanding of the fixed point and floating- K2, K4
point arithmetic operations.
Implementation of control unit techniques and the
CO 3 K3
concept of Pipelining
Understanding the hierarchical memory system,
CO 4 K2
cache memories and virtual memory
Understanding the different ways of
CO 5 communicating with I/O devices and standard K2, K4
I/O interfaces
 CO 5

Understanding the different ways of

communicating with I/O devices and standard
I/O interfaces
 Input-Output Interface
The differences with CPU & Peripherals:-
– Peripherals are often electromechanical devices whose manner of operation is
different. A conversion of signal values may be required.
– The data transfer rare is different from the clock rate of the CPU. A
synchronization mechanism may be needed.
– Data codes and formats differ from the word format in CPU.
– The operating modes of peripherals differ from each other.
Due to the above differences between CPU and Peripherals for
smooth data and information transfer Interface is required i.e
Interface Transfer information between internal storage and
external peripherals and Resolves the difference between CPU and
peripherals
• Interfaces supervise and synchronize transfers
• Lies between processor bus and peripheral device (or its controller)

4
 O/I Bus and Interface Modules
• I/O bus consists of
– Data lines
– Control lines
– Address lines
• Each peripheral is associated with its interface unit
– Decode address and control received
– Interrupts for the device
– Provide signals for device
– Synchronize and supervise data flow
• I/O Bus configuration are of two Types
– Memory-mapped: Use common data, address, and control busses
for both memory and I/O
– Isolated: Share a common address and data but, but use different
control lines.
5
 O/I Bus and Interface Modules
CPU Memory
Independent I/O Bus memory
bus

Interface Interface Separate I/O instructions (in,out)

Peripheral Peripheral

CPU Lines distinguish between

common memory I/O and memory transfers
& I/O bus
40 Mbytes/sec
VME bus optimistically
Multibus-II
Memory Interface Interface Nubus 10 MIP processor
completely
saturates the bus!
Peripheral Peripheral
6
 I/O Bus and Interface Modules
• Each interface has own address
• Processor places address on address lines
• Corresponding peripheral responds while others are
deactivated
• Same time processor provides function code on control
lines
• Interface executes function on peripheral
• 4 main command types
– Control commands, status, output data, input data

7
 I/O vs. Memory Bus
• 3 ways to communicate with I/O and memory
– Use two separate buses
• Uses separate I/O processor
• Memory communicate with both IOP and CPU via
memory bus
• IOP has separate set of data, address and control lines
with peripheral interfaces
– Use common bus but separate control lines
– Common bus and control lines

8
 Isolated vs. Memory-Mapped I/O
• Uses common bus for data transfer
• Isolated I/O
– Uses separate Memory or I/O R/W lines
– Separate I/O instruction set
– Own address spaces for memory and I/O
– Complex but high flexible
• Memory mapped I/O
– Uses same address space with memory
– Only one set of R/W signals
– Interface registers considered as a part of memory system
– Reduces memory address space available
– Same instruction set

9
 Example of I/O Interface (I/O port)

Bidirectional Port A I/O Data

Data bus Bus buffer
register
Chip Select
Port B I/O Data

Internal bus
Register register
Timing
select
And Control Control
I/O Read control register
I/O Write
Status Status
register

To I/O CPU To I/O Devices

10
 Asynchronous Data Transfer
• Internal operations in a computer are synchronize with
internal clock pulse generator
– Applied to all registers
– All data transfer among registers happen at the same time with
the occurrence of the clock pulse
• But the CPU and I/O interfaces are independent
– They run on their own clocks
– If I/O shares common clock with CPU two units said to be
synchronize.
– Otherwise asynchronous

11
 Asynchronous Data Transfer
• Asynchronous data transfer
– Requires control signals to indicate time at which
transmission occurs
• Main methods of indicate data transfer time
– Strobe - Giving a signal by one unit to indicate transfer
time
– Handshaking - Transfer on agreement
• Data transfer with a control signal indicating the presence of data
• Data receiver sends an acknowledge receipt of data
• Timing diagrams are commonly used to show the
relationship between control signals
• Sequence of control signals depends whether transfer
initiated by source or destination
12
 Strobe Control
• Uses a control line to time each transfer
• Strobe is activated either by source or destination
• Strobe says when there is valid data on data bus
• Generally strobes activated by clock signals
• CPU is always in control of the transfer (i.e. strobe is
always from CPU)
• This method is mainly applicable in memory R/W
operations.
• Most of I/O operations use handshaking

13
 Source initiated data transfer
• Source places data on the bus
• Have a brief delay to settle data on the bus
• Source activate the strobe pulse
• Then destination reads data to internal register (Often uses
falling edge)
• Source removes data after brief delay (Not necessary)

Data bus
Source Unit Strobe Destination Unit

Data Valid Data

Strobe

14
 Destination initiated data transfer
• Initiated by destination
• Destination activates strobe
• Source places data on the bus
• Keeps data until accept them by destination
• Reads data to a register (Generally at falling edge of the strobe)
• Destination disable strobe
• Source removes data after predetermined time

Data bus
Source Unit Strobe Destination Unit

Data Valid Data

Strobe

15
 Handshaking
• Strobe disadvantage
– In source initiation - Source doesn’t know whether
destination got the data
– In destination initiation – Destination doesn’t know
whether source has placed the data on the bus
• Handshaking introduce a reply method to solve
this problem

16
 Two wired handshaking
• 1st control line
– Same direction as the data flow
– Use by the source
– Indicates whether it has valid data
• 2nd control line
– From destination to source
– Uses by the destination
– Indicates whether it can accept data
• Sequence of control used depends on the unit initiate
transfer
• In a fault at one end timeout uses to detect the error

17
 Source Initiated Transfer

Data bus
Data valid Block
Source Unit Destination Unit Diagram
Data accepted

Data bus

Data valid Timing

Diagram

Data accepted

Place data on bus

Enable data valid Accept data from bus
Enable data accept
Sequence of
Disable data valid Initial stage events
Invalidate data on bus Disable data accepted
Ready to accept data 18
 Destination Initiated Transfer

Data bus
Data valid Block
Source Unit Destination Unit Diagram
Ready for data

Ready for data

Data valid Timing

Diagram

Data bus

Ready to accept data

Enable ready for data
Place data on bus
Enable data valid Sequence of
Accept data from bus events
Disable data valid Disable ready for data
Initial stage
Invalidate data on bus 19
 Asynchronous Serial Transfer
• Parallel transmission
– Each bit of message has its own path
– Total message transmitted at the same time
– N bit message requires N conduction paths
– Faster/expensive
– Short distance transmission
• Serial transmission
– Each bit in message sent in sequence one at a time
– Uses only one pair of conductors (or one conductor with a
common ground
– Slower/cheaper
– Uses for long distance transmission

20
 Asynchronous Serial Transfer
• Synchronous
– Uses common clock frequency
– Transmits bits continuously
– For long distance transmission
• Use separate clocks with same frequency
• Keep clocks in step via synchronization signals send periodically
– Periodic synchronization signals should transfer even no data
to transmit
• Asynchronous
– Transmits only when data available to transmit
– Otherwise keeps in idle
– Uses start and stop bits at the both ends of the character code
– Transmission line rests at state 1 while idle
– Start bit is always 0
– Stop bit can be 1 or more 1s
21
 Transmission Rules
1. When a character is not send line keeps in 1 state
2. Start of transmission of a bit is determined by the
start bit (usually 0)
3. Character bits always follows start bit
4. After the last character bit stop bit is detected when
the line returns to the state 1 for at least one bit
time

22
 How it works
• Using transmission rules receiver detects start bit when
line goes 1 to 0
• Receiver knows
– Bit transmission rate
– Number of bits in character
• After a character transmission line keeps at state 1 for at
least one or two bits for resynchronization at both
transmitter and receiver
• Ex: Transmission rate 10 characters/sec (at 1 start bit, 8
info bits and 2 stop bits)  (1+8+2)*10 bit/s  110
bit/s
• i.e. baud rate  110 baud
23
 Definitions
• Baud rate – Rate at which serial information is
transmitted and equivalent to the data transfer in
bits per second
• UART – Universal Asynchronous Receiver-
Transmitter (Asynchronous Communication
Interface)
– An interface which accept 8 bit character code from
a computer and forward corresponding 11 bit serial
code to the device or does the function other way
around

24
 Asynchronous Communication Interface
Bidirectional
Data Bus Transmit Data
Transmitter
Bus Buffer Shift Register
Register

Transmitter
Clock
Chip Select Transmitter
CS Control Register
Control & clock

Internal Bus
Register Select
RS
Receiver Clock
Timing & Status Receiver
Controlling Register Control & Clock
I/O Read
RD

Receive Data
I/O Write Receiver
WR Shift Register
Register

25
Asynchronous Communication Interface
• Can function as both transmitter and receiver
• Initial mode is setup by control byte loaded to control
register
• CPU load and retrieve data via interface registers
while shift registers are used for data serialization
• Register selection function shows bellow

CS RS Operation Register selected

0 X X None: data bus in high impedance

1 0 WR Transmitter Register

1 1 WR Control Register

1 0 RD Receiver register

1 1 RD Status register
26
 Operation
• Start by CPU by sending a byte to control register
specifying
– Mode of operation
– Baud rate to use
– Bits in each character
– No of stops bits should append
– Whether to use parity check
• Status register
– 2 bit Flags
• Transmit register is empty
• Receiver register is full

27
 Operation
• Transmitter
– CPU reads status register
– Check flag to know whether transmit register is empty
– If empty CPU transfer character to transmit register &
interface marks register full
– Set 1st bit of shift register to 0, transfer character there and
append appropriate no of stop bits
– Mark transmit register empty
– Character is transmitted bit at a time in specified baud rate
– CPU can load another character after checking flag
– This is a double buffered interface, since new character can
be loaded as soon as previous one start transmission
• Receiver ?
28
 Operation
• Receiver
– Receive data input line is in state 1 when line is idle
– Receiver controller monitors input line for occurrence of a 0
– Once start bit detected incoming bits of character are shifted to
register at prescribed baud rate
– Then it checks for parity and stop bits
– Character without start and stop bits transfer in parallel to the
receiver register
– Flag in status register set to indicate receiver register is full
– CPU checks flag and if data available read data and clears
receiver register full flag
• Possible receiving error
– Parity error – Failure in parity bit checking
– Framing error – Invalid stop bits
– Overrun error – Write next character before read previous by
CPU
29
Modes of Transfer

30
 Modes of Transfer
• CPU merely execute instruction and accept data
temporally from I/O devices
• Ultimate source and destination is memory
– Receiving data from input devices  stores in memory
– Sending data to output devices  from memory
• I/O handling modes
– Programmed I/O
– Interrupt-initiated I/O
– Direct Memory Access (DMA)

31
 Programmed I/O
• I/O instructions are executed according to a program in
CPU
• I/O instruction transfers from and to CPU registers
• A memory load instruction used to load it memory
• Another instruction used to verify data and count the
number of words transferred
• Constant I/O monitoring is required by CPU
• CPU stays in a program loop until I/O unit indicate data
ready
• This waste CPU time

32
 Programmed I/O – Input Device
Data bus
Data Register Data bus
Address bus
Interface
Data valid
CPU I/O Device
I/O Read
Status Data accepted
F
I/O Write Register

• I/O device and Interface use handshaking for data transfer

• Once data available on Data Register Interface sets flag bit (F)
indicating data availability
• Interface do not reset data accepted line until CPU reads data and
clear the flag
• CPU needs 3 instruction for each byte transfer
– Read the status register
– Check the flag bit
– Read data register when data available
33
• Transfer can be done in blocks for efficiency
Flow Chart For CPU Program To Input Data
Read status register
• Useful small low-speed
Check flag bit
computers dedicate monitor
device continuously
=0
Flag • Difference transfer rates
=1
between CPU and I/O makes it
Read data register
inefficient
• Ex:
Transfer data to memory – Assumes a system read and check
flag in 1µs
Operation no – Device transfer rate = 100
Complete
characters/s
yes
– i.e. 1 byte per 10000µs
Continue
With –  Only 1 transfer for 10000
program checking 34
 Interrupt Initiated I/O
• Instead of continues monitoring at CPU interface
inform when data ready
• Uses interrupts
• CPU deviated from current program and take
care of data transfer
– Save return address from program counter to stack
– Then control branches to service routing
• Non vectored interrupts
• Vectored interrupts
• After completing I/O transfer it returns back to
previous program
35
 Software Consideration
• In addition to h/w computer should have s/w
routings to control interface and transfer data
• Ex: Control commands – activate peripheral,
check data state, stop tape, print character, issue
interrupt
• I/O control software is fairly complex
• Standard I/O routing provided by the
manufacturer and included with OS
• I/O routings available as OS procedures; do not
need to go to assembly level details

36
Priority Interrupts

37
 Priority Interrupts
• Generally I/O data transfer is initiated by CPU
• But device must be ready first
• Device readiness for data transfer can be identify by the
interrupt signal
• How CPU responds to the interrupt request
– Push return address to the memory stack
– Branch to the interrupt service routing
• Priority Interrupt system
– Deals with simultaneous interrupts and determine which one to
serve first (critical situation / fast I/O)
– Determine in which conditions allow interrupting while
executing another interrupt service routing

38
 Polling (Software)
• Priority identification mechanism in software
• For all interrupts has a common branch address
• Then polls the interrupt devices in sequence
• The order at which it polls determine the priority
– Higher priority device is tested first.
– If its interrupt signal is on serves the device
– Then test for the next device
– Proceed on until last device
• Disadvantage: When there are multiple interrupts polling
time might exceed time available to service the I/O
device
• Solution: Hardware priority interrupts unit
39
 Hardware Priority Interrupt Units
• Accepts interrupts from many sources
• Determine which one has higher priority
• Issue interrupt accordingly to the CPU
• Further each interrupt source has its own interrupt
vector to access its own service routing directly
• No polling required
• 2 major establishments of hardware priority
function
– Serial Connection (Daisy-chain)
– Parallel Connection

40
 Daisy Chain

Priority data bus

VAD VAD VAD

PI Device1 P0 PI Device2 P0 PI Device3 P0
To Next
Device

INT
Interrupt request CPU
INTACK
Interrupt acknowledge

• Serial connection of all interrupt devices

• Higher priority one places first
• Interrupt request line is common (wired logic)
• CPU responds interrupt via Interrupt Acknowledge line
• If Device 1 has pending interrupt disable P1 and place its own
Interrupt vector. Otherwise pass it to the next device via P0
41
 Parallel Priority Interrupt
Interrupt
Register VAD
Disk I0 To CPU
Y
Printer I1 X
Priority 0
Reader I2 Encoder 0
0
Keyboard I3 0
0
0
IEN IST
Enable

Interrupt to CPU

INTACK from CPU

Mask 42
Register
 Parallel Priority Interrupt
• Uses a register to set interrupt bits by each device
• Uses Mask Register change the sequence of servicing
• Priority encoder generates Interrupt Vector
• CPU interrupt is generated only when InterruptENable and
InterruptSTate are set
• IEN can be set by the program
• With the INTACK from CPU VAD is put on to the bus

43
 Priority Encoder
• Implements the priority function

Inputs Outputs
Boolean function
I0 I1 I2 I3 x y IST

1 x x x 0 0 1

0 1 x x 0 1 1
x = I0’ I1’
0 0 1 x 1 0 1 x = I0’ I1 + I0’ I2’
(IST) = I0 + I1 + I2 + I3
0 0 0 1 1 1 1

0 0 0 0 1 1 0

44
 Interrupt Cycle
• IEN uses by the program to enable or disable interrupts
while running
• At the end of each instruction cycle CPU checks IEN and
if enabled checks IST
• Sequence of micro operations follows as receive an
interrupt:
– SP  SP – 1
– M[SP]  PC
– INTACK  1
– PC  VAD
– IEN  0
– Go to fetch next instruction

45
 Software Routing
• Priority interrupt system is a combination of Hardware and
Software techniques
• Computer has software routing to service interrupt requests and to
control interrupt hardware registers

I/O service program

Address KBD
Memory Program to service
0 JMP DISK Magnetic disk
1 JMP PTR
2 JMP RDR KBD
Program to service
3 JMP KBD
Line printer

Main Program KBD

750 Program to service
Character reader
Stack KBD
Program to service
256 256 Keyboard 46
750
 Initial and Final Operations
• Initial
– Clear lower-level mask register bits
– Clear interrupt status bit IST
– Save contents of processor registers
– Set interrupt enable bit IEN
– Proceed with service routine
• Final
– Clear interrupt enable bit IEN
– Restore contents of processor registers
– Clear the bit in the interrupt register belonging to the source
that have been serviced
– Set lower-level priority bits in the mask register
– Restore return address into PC and set IEN
47
DMA (Direct Memory Access)

48
 Direct Memory Access - DMA
• CPU limits the data transfer speed for fast I/O devices
• DMA removes CPU and allow peripherals to handle
memory bus
• During the transfer CPU does not have the control over
the bus
• CPU idling the bus can be done through the control
signals “Bus Request” & “Bus Grant”
– DMA controller enables BR,
– then CPU finishes current operation and puts its address and
data buses in high impedance
– CPU sets BG line
– DMA transfers data and resets BR for the CPU to use the
memory bus
• DMA data transfer can either happen as
– Burst transfer or
49
– Cycle stealing
 DMA Controller

Address bus

Data bus
Address bus buffers
buffer

Address Register

Internal bus
DMA select
Register select Word count register
Read
Write Control
logic Control register
Bus request
Bus grant DMA Request
Interrupt DMA Acknowledge To I/O device
50
 DMA Controller
• Interfaces with CPU and I/O devices
• Further DMA controller has
– Address Register – used for direct communication with memory
– Set of Address Lines – used for direct communication with
memory
– Word Count Register – specifies the number of words to be
transferred
– Control register – Specifies the mode of transfer
• Data transfer is done directly between device and memory
under DMA control
• RD/WR signals are bidirectional
– When BG is set DMA can use them for memory RD/WR
– Otherwise CPU uses it DS and RS to write and read from DMA
• DMA uses Req and Ack signals with handshaking to
communicate with external peripheral devices
• CPU treat all DMA registers as I/O interface registers and
51

can be read and write under program control

 DMA Controller
• DMA is initialized by CPU
• Then DMA continues transfer an entire block of
data between memory and peripheral
• CPU sends following information on DMA
initialization
– Starting address for memory read or write
– Word count the number of words to be transferred
– Control to specify mode of transfer
– Control to start transfer
• CPU communicates with DMA after transfer
initialization only if
– It receives an interrupt
– It wants to know how many words have been 52
transferred
 DMA Transfer

• CPU communicates with DMA through address

and data bus as with any other interface unit
• DMA has its own address by which DS & RS
activates
• CPU initialize DMA through data bus
• DMA can start data transfer between memory and
peripheral device as it gets the control command

53
 DMA Transfer

Interrupt
Random-access
BG CPU
Memory (RAM)
BR
RD WR Address Data RD WR Address Data
Read Control
Write Control
Address bus
Data Bus

Address
select
RD WR Address Data
DS
Direct memory DMA Acknowledge
RS I/O
Access (DMA)
BR Peripheral
controller DMA Request
BG device
Interrupt
54
 DMA Transfer - Sequence
• Peripheral device sends DMA request
• DMA controller activates BR
• CPU finishes current bus cycle and grant the bus by
activating BG
• DMA puts current address to the address bus and
activate RD or WR accordingly
• And acknowledges peripheral
• Then peripheral puts data to (or reads data from) the bus
• Thus peripheral directly read or write memory
• For each word transferred DMA increment address and
decrement word count register
55
 DMA Transfer – Sequence (Cont.)
• If word count is not zero DMA checks request line
coming from peripheral
– If active (fast devices) initiate the second transfer immediately
– Otherwise disable BR
• If word count is zero
– DMA stop transfer, disable BR and inform CPU the
termination of data transfer
• Zero value in word count indicates successful data
transfer
• DMA can have even more than one channel
• DMA commonly used in devices like magnetic disks
and screen display
56
I/O Processor (IOP)

57
 I/O Processing
• Instead of each interface communicating with the CPU
• One or more external processors assigned to communicate
directly with I/O devices
• IOP has both direct memory access and I/O communication
capabilities
• IOP releases the CPU from the housekeeping the chores
involved in I/O transfer
• Processors handling serial communication with remote terminal
are called Data Communication Processors (DCP)
• IOP is similar to CPU except its handles only I/O processing
• Unlike DMA controller totally setup by the CPU, IOP can fetch
and executes its own instructions
• Additionally IOP can perform other tasks like arithmetic, logic,
branching and code translation
58
 Computer with I/O Processor

Central
processing unit
(CPU)

Memory unit Memory bus Peripheral devices

PD PD PD PD

Input-output
Processor
I/O bus
(IOP)

59
 Responsibilities of IOP
• Memory at the centre can communicate with both processors
via DMA
• CPU responsible for data processing and computational tasks
• IOP transfers data between peripheral devices and memory
• CPU is usually assigned the task of initiating the I/O
program, there after IOP operates independently
• IOP take care of data format difference and structure
mapping between memory and various I/O devices
• Communication between CPU and IOP is similar to
programmed I/O
• Communication between Memory and IOP is done as DMA
• IOP can be independent or slave processors depending on the
sophistication of the system
• Instructions for IOP generally refers as commands

60
 CPU-IOP Communication

Send instruction Transfer status word

To test IOP path To memory location

If status OK… send

Access memory for
Start I/O instruction
IOP program
To IOP
CPU Operations

IOP Operations
Conduct I/O transfers
CPU continues with
Using DMA; prepare
Another program
Status report

I/O transfer completed;

Request IOP status
Interrupt CPU

Check status word Transfer status word

For correct transfer To memory location
61
Continue
Serial Communication

62
 Data Communication Processor
• DCP distribute and collect data from remote
terminals
• Specialized I/O processor for communicating
with data communication network
• Network can have any device like printers,
interactive display devices, digital sensors,
remote computers
• Can serve many uses at a time using time-sharing
• Main difference with IOP is DCP uses single pair
of wires while IOP uses a common bus with
control lines 63
 Connection Methods
• Commonly connected via telephone or other public communication
network
• Telephone network was originally designed for voice communication
and commuter uses modem for modulating and demodulating signals
• Communication line may connected to synchronous or asynchronous
interface depending on remote terminal
• Synchronous transmission
– doesn’t required start and stop bits
– more efficient in transmission
– uses by high speed devices (modems)
• Modem uses frequency synchronization
– i.e. extract clock signals from the communication line at both ends
– Modems transfers and receives data with the clock signals to keep the
synchronization at both ends
– Transmitter and receiver clocks are adjusted continuously according incoming
bit stream
• Asynchronous transmission
– sends each character and block separately with start and stop bits
64
– No need of continuous messages for synchronization
 Error Detection
• Error detection is the one of functions in DCP
• Using parity bits – checks at each character
• echo character – prints to the terminal
• LRC – Longitudinal Redundancy Check
– LRC is one more characters with the party over the entire
block
– sends following each block
• CRC – Cyclic Redundancy Check
– A polynomial code
– Obtained by passing through a feedback register
– Suitable for detecting burst errors

65
 Transmission Modes
• Simplex
– Line carry information in one direction only
– Receiver can not feedback or acknowledge
– Rarely used in data communication
• Half-duplex
– Used a single pair of wires
– Transmit data only one direction at a time
– In modems one act as the transmitter and other the receiver
– When transmission completed reverse the role
– Switching time is called turnaround time
• Full-duplex
– 2 pair of wires
– Even single pair can do full duplex transmission using frequency
spectrum
66
 Protocols
• Data links – communication lines, modems and other
equipments used between two or more stations
• Protocol – set of rules followed by interconnected
computers and terminals
– Establish connection
– Identify sender and receiver
– Ensure error free transmission
– Handle all control functions
– Categorized according to the framing techniques
• Character oriented – based on binary code of
characters
• Bit oriented – do not use characters in control fields
67
 Character Oriented Protocol
• Used ASCII
• Communication Control Characters – characters used for
transmission control
Code Symbol Meaning Function
0010110 SYN Synchronous idle Establishes synchronism
0000001 SOH Start of heading Heading of block message
0000010 STX Start of text Precedes block of text
0000011 ETX End of text Terminates block of text
0000100 EOT End of transmission Concludes transmission
0000110 ACK Acknowledge Affirmative acknowledgement
0010101 NAK Negative acknowledge Negative acknowledgement
0000101 ENQ Inquiry Inquire if terminal is on
0010111 ETB End of transmission block End of block of data
0010000 DLE Data link escape Special control character (binary transmission)

SYN SYN SOH Header STX Text ETX BCC 68

 Typical transmission
Code Symbol Comments
00010110 SYN First sync character
00010110 SYN Second sync character
00000001 SOH Start of heading
01010100 T Address of terminal is T4
00110100 4
00000010 STX Start of text transmission
01010010
01000101 Request Text sent is a request to respond with
Balance the balance of account number 1234
Of account
No. 1234
10110011
00110100
10000011 ETX End of text transmission
01110000 LRC Longitudinal parity character

69
 Bit-Oriented Protocol
• Do not use characters in control fields
• No character boundaries – any length of serial bits can transfer
• Messages are organized into frames
• Frame contains information field, address, control and error checking
• Primary station – has the control over the link and issues commands
• Secondary station – other stations (can have more than one)
• Zero insertion – transmitting additional 0 after every 5 transmission bits to
avoid occurring start/stop flag in the transmission data
• Examples
– SDLC – Synchronous Data Link Control (IBM)
– HDLC – High-level Data Link Control (International Standards Organization)
– ADCCP – Advanced Data Communication Control Procedure (American National
Standard Institution)

Flag Address Control Information Frame check Flag

01111110 8 bits 8 bits Any number of bits 16 bits 01111110
70
 Control Field
• Ns – Sender’s frame count
• Nr – Received confirmation
• P/F - Poll bit (primary station) / Final frame (secondary station)
• Code – Commands
• Supervisory – assists transfer information (confirm acceptance of
frames, ready/busy messages)
• Unnumbered – 32 commands (initializing link functions, reporting
procedural errors, placing stations in disconnecting mode)

1 2 3 4 5 6 7 8
0 Ns P/F Nr Information transfer

1 0 Code P/F Nr Supervisory

1 1 Code P/F Code Unnumbered 71