INDIAN INSTITUTE OF TECHNOLOGY - INDORE
EE 206: ELECTRICAL MACHINES AND POWER ELECTRONICS
MID-SEMESTER EXAMINATION
Date: 27th February 2024
Maximum Time: 2.00 Hrs. Maximum Marks: 35
This question paper consists of 3 printed sides.
Ensure that the waveforms are neatly drawn using a pencil for at least 2 cycles.
Mention relevant units for each quantity wherever applicable.
1) Consider the following source voltage and current in a single-phase AC system:
vs (t) = 1.25 + 240√2 cos (ωt) + B√2 cos (3ωt - 400) + 12√2 cos (5ωt - 100) V
is (t) = A + 8√2 cos (ωt - 400) + 5√2 cos (3ωt - 550) + 0.8√2 cos (5ωt - 200) A
The apparent and reactive powers were measured to be 2750.0 VA and 1310.0 var respectively.
Compute: a) the values of A and B, b) average active power, c) ratio of distortion to non-active power,
d) displacement and overall power factor values and e) the distortion factor. (5 marks)
2) Determine the trigonometric Fourier series coefficients for a periodic Trapezoidal (symmetrical)
current signal shown in the figure below. If the amplitude A is 10 A and 1/T is 100 Hz, using the
coefficients compute: a) the RMS value of the fundamental, b) the distortion factor (DF) and c) the total
harmonic distortion (THD) values. Also sketch the harmonic spectrum of the waveform. (6 marks)
Fig. Q2: Symmetrical Trapezoidal Current waveform
3) The IRF540N is a fifth generation power MOSFET from IR, having a continuous drain current of
27 A and blocking voltage of 100 V. The input and output capacitances of this device are 1400 pF and
330 pF respectively. The gate drive designed to turn on this device, supplies a constant current of
0.29 A. If the current through the miller capacitance is measured to be 0.14 A, calculate the values of:
a) the reverse transfer capacitance Crss, b) the gate to source CGS and drain to source CDS capacitances,
and c) the power required to turn on the device. Given that the gate to sink voltage VGS increases
linearly from 0V to 15 V in 118 ns. (3 marks)
4)a) With a neat circuit diagram and corresponding waveforms, realize AC-AC conversion using the
generic power electronic (H bridge) circuit. The output frequency is to be 1/3rd the input frequency.
Indicate the switching sequence clearly in your plot. (2 marks)
b) The 3 phase AC input to a power electronic rectifier is 415 V, 50 Hz, 10 A at a power factor of 0.92
(lag). The relative loss of this converter is 7.63%. If the weight and volume of the rectifier (including
the heatsink are 2.789 kg and 1.325 dm3 respectively, calculate: i) the output power, ii) the specific
power and power density metrics of the converter. (2 marks)
5) Stating your assumptions clearly and using the principle of volt-sec balance, obtain the expression for
Vo/Vg in terms of the duty cycle D for the non-isolated (transformer-less) DC-DC converter circuit
(Configuration II in the reference paper) shown in the figure on the next page.
Switches S1 and S2 are switched ON simultaneously only during 0 < t < DTs and S3 is complimentary:
ON for DTs < t < Ts in each switching cycle duration of Ts.
1
[Hint: assume that diode S4 is ON for 0 < t < DTs and OFF for DTs < t < Ts; exactly identical inductors
L1 and L2 and hence vL1 = vL2] (4 marks)
Fig. Q5: DC-DC converter from: L.-S. Yang, T.-J. Liang, and J.-F. Chen, “Transformer-less DC–DC converters
with high step-up voltage gain,” IEEE Trans. Ind. Electron., vol. 56, no. 8, pp. 3144-3152, Aug. 2009.
6) Switch Realization: The circuit shown in the figure below which has two exactly identical switches
S1, S2 and a third switch S3. Note the polarity assigned to the switches. Switches S1 and S2 turn ON
simultaneously for a duration DTs and are OFF for the remaining period in Ts. The switching of S3 is
complementary to that of S1 and S2. On the V(x) - I(y) plane mark the operating points of the three
switches. Also suggest suitable PE semiconductor switches for S1, S2 and S3 respectively and redraw
the circuit including these switches. Given: Vg is 20 V, I1 and I2 are 10A each and Vo is 60 V. (3 marks)
Fig. Q6: DC-DC converter – Switch Realization (from the same reference)
7) The HGTG30N120D2 is a robust IGBT. Four of these are
mounted on a common Aluminium heatsink, as shown in the
figure alongside, to realize an inverter. The maximum junction
temperature (TJmax) and junction-to-case thermal resistance
(Rθ-jc) for each device are given from the datasheet to be
150 0C and 0.5 0C/W respectively. Devices S1 and S4 are
attached to the heatsink using thermal paste, while S2 and S3
are attached using thermal pads.
Assume that all four devices conduct in a switching cycle
and they are exactly identical, and the heat sink temperature to
be uniform (steady state) at 83.70C. The thermal paste has a
resistance of 0.07 0C/W, while the pad has a resistance of Fig. Q7: Four IGBTs mounted on a
0.125 0C/W. common heat sink
2
a) Draw the equivalent circuit of the thermal model with proper labeling.
b) If the ambient temperature is 27.50C, compute the heatsink thermal resistance Rθ-sa if each device
generates a loss of 65 W. Also calculate the junction temperatures for the switches.
c) For the exact identical conditions, if a Copper heatsink of same dimensions is used instead, recompute
the heat sink temperature and Rθ-sa for this case. (λAl = 220 W/ m0C and λCu = 385 W/ m0C).
(4 marks)
8) The switching transitions for one IGBT of Q7 are shown in the figure below. Sketch the current and
voltage waveforms as functions of time and write down the integration expressions for the energy loss
during the ON and OFF transitions. Calculate the ON state loss in the switch. (3 marks)
Fig. Q8: Switching Transitions
9) The columns below show the various features of Power Electronic semiconductor switches. Match the
correct set of combinations for each switch (only one best fit per column) and write only the answers in
your sheet: {Ans format example: 7 – F) – vi) – h) – VII.}
Only complete rows will be graded. (3 marks)
Switch PN junction, Control aspect Characteristic Applications
Layers Count features
1. GTO A) 1, 2 i) Fully + voltage a) Low switching loss I. UPS upto
2. Power MOSFET B) 2, 3 controlled & high conduction loss 20 kHz.
3. IGBT C) 2, 4 ii) Fully + current b) Low conduction loss II. SMPS upto
4. Power Diode D) 3, 4 controlled & high switching loss a MHz.
5. Thyristor E) 3, 3 iii) Semi + controlled c) Secondary breakdown, III. HVDC,
6. Power BJT with current negative temp. controlled
iv) Uncontrolled coeff. of R rectification.
v) Semi + controlled d) Inter-digitization of IV. Inverters
with voltage anode and gate upto 50 kHz.
e) Turn on di/dt and V. Uncontrolled
dv/dt limits rectifiers, DC-
f) Tail voltage/ current, DC converters.
conductivity modulation VI. Choppers,
g) Reverse recovery Inverters.
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