Page 1 of 8 AUTHOR SUBMITTED MANUSCRIPT - draft

IOP Publishing Journal Title

1
Journal XX (XXXX) XXXXXX [Link]
2
3
4
5
6
7
8
On the Impact of Spacer Asymmetricity and SRAM
9
10 Performance Optimization of a 10 nm Dual
11
12
13
Material Gate JL FinFET
14
15
16 Udayan Chakraborty1, Tanmoy Majumder2, Sudeb Dasgupta3, Narottam Das4 and
17 Abhishek Bhattacharjee1
18
19 1 Department of Electronics and Communication Engineering, Tripura Institute of Technology,
20 Agartala, 799015, India
21 2 School of Electronics Engineering (SENSE), VIT, Chennai, 600127, India

22 3 Department of Electronics and Communication Engineering, IIT Roorkee, Roorkee, 247667, India

23 4 School of Engineering and Technology, Central Queensland University, Melbourne, VIC 3000,

24 Australia
25
26 E-mail: abhishek89@[Link]
27
Received xxxxxx
28
Accepted for publication xxxxxx
29
Published xxxxxx
30
31 Abstract
32
33 This paper presents a comprehensive analysis of the impact of spacer positioning and channel
34 material on the performance and circuit behavior of a junctionless (JL) dual-material gate Fin-
35 Field Effect Transistor (FinFET). The findings reveal that germanium-based transistors
36 outperform silicon in many device and circuit parameters but experience higher off-state
37 current. Additionally, a symmetric dual-κ spacer configuration enhances on-state current, as
38 well as the read and write static noise margins (RSNM and WSNM), for six-transistor (6T)
39 static random access memory (SRAM). However, this configuration results in inferior short
40 channel effect (SCE) control and a 2% reduction in hold static noise margin (HSNM) due to
41 increased parasitic capacitance compared to an asymmetric dual-κ source-side spacer
42 structure. Furthermore, a higher work function in the source-side gate material improves read
43 current and noise margin by enhancing gate control over the channel. While increasing the
44 inner side high-κ spacer length initially boosts drive current and SRAM performance by
45 intensifying electric field coupling, the benefit diminishes past an optimal length due to
46
higher outer fringe capacitance.
47
48
Keywords: Junctionless, Spacer, SRAM, DIBL, FinFET.
49
50
51
52
53 reconfigurable nanowire FET (RFET) which was reported in
54 1. Introduction our earlier works [6-10]. But as the technology node has
55 gone down below 20 nm, with the aggressive integration of
As scaling of conventional CMOS field effect transistors
56 huge number of transistors in a chip, forming sharp source
(FETs) has reached its fundamental limits [1], structure
57 engineering has led to the exploration of a wide range of
and drain junctions in planar MOS is becoming an
58 electron devices. Some of them include FDSOI NCFET [2],
increasingly difficult task [11].
59 CNTFET [3], MBCFET [4], nanowire FETs [5] and
60

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Journal XX (XXXX) XXXXXX Author et al

1
2
3 (a) (c) (both Si and Ge) on device electrostatics as well as circuit
4 behavior (mainly 6T SRAM cell) for a dual material (DM)
High κ spacer
5 Low κ spacer gate JL FinFET. Dual gate material is mainly selected since
6 it has potential benefit of reducing SCEs as reported by Long
S
7 et al. [17].
8
9 Lg
(a) (b)
10 (b) (d)
11
12 1E−6

Drain Current (A/mm)

VDS=0.7V

13 1E−8
ND=1018/cm-3
data in ref [19]

14
our simulation
1E−10

15 1E−12
16
17 1E−14
−0.4 −0.2 0.0 0.2 0.4 0.6 0.8 1.0 (c) (d)
18
Gate Voltage (V)

19
Figure 1. (a) 3-D view (b) Top view (c) 2-D cut-plane view of the
20
symmetric dual-κ spacer (SymD-κ) JL-FinFET structure (d) Model
21
calibration for JL FinFET at VDS=0.7 V against the experimental
22 results in [5].
23
24 A JL transistor having identical doping type and
25 Figure 2. (a) No spacer (b) Asymmetric dual-κ spacer at source
concentration in source, channel and drain regions shows
26 (AsymD-κS) (c) Asymmetric dual-κ spacer at drain (AsymD-κD)
great potential as a possible solution to this problem. Since
27 (d) SymD-κ JL FinFET architectures.
PN junctions are not present, JL transistors provide better
28
immunity against SCEs at sub nanometer regime. It is also
29 The rest of the paper is organized as follows. In section 2,
observed that JL FinFETs offer lower leakage current, better
30 we describe the device architectures, calibration with
31 subthreshold swing (S/S) and reduced drain induced barrier
lowering (DIBL) as compared to a conventional FinFET at experimental data and simulation set up used. Section 3
32 compares the device as well as circuit performance of
33 similar technology node [12]. Mangal et al. proposed a fully
gate-covered JL FinFET which has a better switching ratio various JL FinFET structures based on spacer engineering
34 for both Si and Ge channel materials. In section 4, we present
35 and temperature resilience [13]. Kaur et al. investigated the
impact of dual-κ symmetric spacers on the performance of a the performance optimization for varying spacer length,
36
underlap length, supply voltage and gate material work
37 JL FinFET [11] and found significant improvement in device
function. Finally, a conclusion is drawn in section 5.
38 electrostatics as compared to its other counterparts. A multi-
39 gas sensing device using JL FinFET with higher gas response
2. Device structure and Simulation Setup
40 was proposed by Mehrdad et al. [14]. The improvement was
41 based on work function modulation of the conducting The 3-D schematic, top view and 2-D cross section of
42 polymer gate, Poly(p-phenylene). the SymD-κ JL-FinFET is shown in Figure 1 (a), (b) and (c)
43 Enhancement in digital and analog circuit performance respectively. The various device architectures based on
44 with JL transistors was explained by Han et al. [15]. The spacer engineering and asymmetricity can be seen in Figure
45 advantages of germanium (Ge) as channel material in JL 2. It may be noted that, unless otherwise mentioned, for all
46 FinFETs was reported by Sil et al. [16]. Significant the devices under consideration (having spacers); inner high-
47 improvements in mixed mode circuit performance for an κ spacer is HfO2, κ = 25 and an outer low-κ spacer is SiO2, κ
48 inverter and 3 stage ring oscillator was seen as compared to = 3.9. The work function of the source and drain side gate
49 an equally sized silicon (Si) counterpart. materials (ΦM1 and ΦM2) are kept as 4.66 eV and 4.28 eV
50 In spite of the works reported by various research groups respectively. ΦM1 is kept greater than ΦM2 as it results in
51 on this interesting class of nano devices over the years, a lot better suppression of SCEs [18]. The total gate length
52 is still unexplored especially the impact of spacer (LM1+LM2), fin height (Hfin), fin width (Wfin), gate oxide
53 asymmetricity and variation in channel material on the thickness (tox), buried oxide thickness (tbox) are kept as 10 nm
54 device as well as mixed mode circuit performance of a JL (5 nm+5 nm), 5 nm, 5 nm, 3 nm, 10 nm with a channel
55
FinFET. In this paper, we provide a detailed investigation on doping concentration of 1018 cm-3.
56
the effect of symmetric as well as asymmetric dual-κ spacer
57
(both at source and drain side) and channel material variation
58
59
60

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3 (a) (b) 3. Performance Comparison for Various JL-FinFET
4 8.0×10−4
0.2

Conduction band energy (eV)

Si SymD-k VDS=0.7V Si no spacer
Architectures
5
Si SymD-k VDS=0.7V Si AsymD-kS
Drain Current (A/mm)

Ge SymD-k 0.0 Si AsymD-kD

6.0×10−4
6
Ge SymD-k
Si SymD-k
VDS=0.3V −0.2 Ge no spacer 3.1 Device Electrostatics
7 4.0×10−4 Ge AsymD-kS

8
Ge AsymD-kD
VDS=0.7V −0.4 Ge SymD-k Figure 3 (a) to (f) compares the device attributes for
9 2.0×10−4
various JL-FinFET structural designs considering both Si and
−0.6
10 0.0
VDS=0.3V Source
Ge as channel materials. It can be clearly seen that the
Drain
11 0.0 0.2 0.4 0.6 0.8 1.0
−0.8 devices having spacers outperform the one without spacer
0.00 0.01 0.02 0.03
12 Gate Voltage (VGS) Distance along channel x(nm) oxide in almost all the occasions, while SymD-κ and
13 8.0×10−4
(c) (d) AsymD-κS stands out in the queue.
14 7.0×10 −4
Si
Ge
VDS=0.7V Si
VDS=0.7V
15 6.0×10−4
1E−9 Ge
(a) (b)
16
ION (A/mm)

IOFF (A/mm)

5.0×10−4
1E−10
17 4.0×10−4

18 3.0×10−4

2.0×10−4 1E−11
19
1.0×10−4
20 0.0 1E−12
21 No spacer AsymD-kS AsymD-kD SymD-k No spacer AsymD-kS AsymD-kD SymD-k
(e) (f)
22 90
Si Si
(c) (d)
VDS=0.7V 80 VDS=0.7V
23 75
Ge Ge

24 60
60
DIBL (mV/V)

25
S/S (mV/dec)

26 45 40

27 30

28
20
15

29 0 0 (e) (f)
30 No spacer AsymD-kS AsymD-kD SymD-k No spacer AsymD-kS AsymD-kD SymD-k

31
32 Figure 3. Comparison of (a) ID-VGS characteristics of SymD-κ
JL-FinFET at varying VDS for both Si and Ge (b) conduction band
33
energy along channel (c) ION (d) IOFF (e) DIBL and (f) S/S for
34
various Si as well as Ge JL-FinFET architectures at VDS=0.7 V.
35
36 (g) (h)
All dimensions are in accordance with the current
37
International Roadmap for Devices and Systems (IRDS)
38
39 requirements [1]. All the devices and mixed mode circuit
40 simulations including 6T-SRAM were carried out using
41 Sentaurus 3D numerical device simulator. Quantum Enhanced fringe field

42 Mechanical Drift Diffusion model (LG=10nm), field

43 dependent mobility model, generation-recombination model,
44 band-to-band tunneling model, high-field saturation,
Figure 4. Electric field contour comparisons for (a)-(b) No
45 quantum density gradient, Shockley–Read–Hall (SRH)
spacer (c)-(d) AsymD-κS (e)-(f) AsymD-κD (g)-(h) SymD-κ JL-
46 recombination, and band gap narrowing models are used in
FinFET architectures (left-side Si and right-side Ge devices).
47 our simulations. To validate the accuracy of our simulation
48 set up we have calibrated it by reproducing the experimental
The transfer characteristic of Ge SymD-κ transistors for
49 results published in [19]. A good agreement between the
both VDS (0.3V and 0.7V) shows significant improvement in
50 simulated characteristics and experimental device data is
terms of on-state current [Figure 3 (a)] which is due to higher
51 observed in Figure 1 (d).
electron mobility in Ge than Si. The values at our detection
52
53 limits are 7.67×10-4 A/µm (Ge) and 1.36×10-4 A/µm (Si).
54 When gate potential is applied, conduction band edge at the
55 source/channel region reduces more [Figure 3 (b)] in SymD-
56 κ (Ge) as compared with the other device architectures,
57 hence ON-current rises. The slightly higher off state leakage
58 for all devices in Ge as compared to Si [Figure 3 (d)] is
59
60

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1
2
3 mainly attributed to its lower bandgap. SCE is apparent in all transistors M5 and M6 are turned ON by enabling WL and
4 the devices in terms of DIBL in the range of 65-83 mV/V. the bit lines BL and BLʹ are pre-charged to supply voltage
5 (a) (b) (VDD). RSNM indicates the stability of the SRAM during
6 read operations.
7
8 VIN VOUT (a) (b)
9 160
Si
Ge
VDD=0.7V 300
Si VDD=0.7V
10 250
Ge

11 Stage-1 Stage-2 Stage-3

Read SNM (mV)

Write SNM (mV)

120 200
12 150
13 80

14
100
40
15 (c)
109
(d) 50

16 3.0 Si
VDD=0.7V
90 0 0
Ge No spacer AsymD-kS AsymD-kD SymD-k No spacer AsymD-kS AsymD-kD SymD-k
17
Total delay of 3-stage RO

2.5 ION/IOFF 85
10 8
(c) (d)
Normalized Value of

(TD=TD1+TD2+TD3)

18 2.0
S/S (mV/dec) 80
300 Si VDD=0.7V
15
Si VDD=0.7V
19 1.5 107 75
Ge
12
Ge

250
20

Hold SNM (mV)

Read Delay (ps)

70
21
1.0 200 9
106
65
22 0.5
60
150
6
23 0.0
No spacer AsymD-kS AsymD-kD SymD-k
105
Si AsymD-κS [20] [21]
100

24 50
3

25 Figure 5. (a) 6T-SRAM cell configuration during Read operation 0 0

26 with different leakage current contributions (b) 3-stage RO
No spacer AsymD-kS AsymD-kD SymD-k No spacer AsymD-kS AsymD-kD SymD-k
(e) (f)
27 schematic (c) Comparison of normalized 3 stage RO delay for Si Si
VDD=0.7V
28 VDD=0.7V 300 Ge
Ge
various device configurations (VDD=0.7V) (d) Comparison of

Read Power Dissipation (pW)

29
30 250
ION/IOFF and S/S for AsymD-κS with published data.
Write Delay (ps)

30 200

31
20
Better SCE control in terms of DIBL for both Si and Ge is 150

32 demonstrated by AsymD-κS as compared to SymD-κ due to 100

10
33 higher parasitic capacitance in the symmetric structure. The 50
34 S/S characterizing the steepness of switching does not show 0
0
35 significant difference and reaches 60 mV/dec (55 mV/dec) No spacer AsymD-kS AsymD-kD SymD-k No spacer AsymD-kS AsymD-kD SymD-k

36 (g) (h)
for AsymD-κS device Si (Ge) and 64 mV/dec (58 mV/dec) 0.5
37 for the SymD-κ one. To better elucidate the charge transport
Si
Ge
VDD=0.7V Si
VDD=0.7V
Write Power Dissipation (pW)

300 Ge
38 0.4
Read Current (mA)

behavior and electrostatics of the device we show the 2-D

39
electric field contours for all the devices (both Si and Ge) in 200 0.3
40
Figure 4. It can be observed that the impact of inner high-κ
41 0.2
spacer (HfO2) is most predominant in case of the SymD-κ
42 100

structure followed by AsymD-κS which results in an increase 0.1

43
in fringe field coupling between gate and the underlap region
44 0
No spacer AsymD-kS AsymD-kD SymD-k
0.0
No spacer AsymD-kS AsymD-kD SymD-k
45 which is also known as gate fringe-induced barrier lowering
46 (GFIBL) [22]. This results in more current flow than
Figure 6. Comparison of (a) RSNM (b) WSNM (c) HSNM (d)
47 conventional (no spacer) and AsymD-κD devices when
Read delay (e) Write delay (f) Read power (g) Write power (h)
48 potential at the drain terminal is applied.
Read current for various Si as well as Ge JL-FinFET architectures
49 at VDD=0.7V.
50 3.2 Mixed Mode Circuit Behavior
51 The schematics of the 6T JL-FinFET SRAM and 3 For the write 1 (0) operation to take place WL goes high,
52 stage ring oscillator (RO) used in Sentaurus 3D-TCAD mixed BLʹ is reset to 0 (1) and BL is set to 1 (0). The stability of
53 mode simulations (performed at 0.7V supply voltage) are write operation is reflected by WSNM. Comparison of
54 shown in Figure 5 (a) (Read mode) and 5 (b). During hold normalized values of total gate delay (TD) (sum of gate
55 delays per stage) for a 3-stage RO is depicted in Figure 5 (c).
mode, Q store 0 and Qʹ store 1 by disabling word line (WL).
56 A significant improvement for AsymD-κS device is observed
HSNM defines the retention stability in preserving the stored
57 arising out of higher ION and lower effective gate capacitance
data. During read operation of the SRAM cell access
58
59
60

4
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1
2
3 Cgg. The better SCE immunity and off state performance of 4. Device Optimization for Circuit Design
4 the AsymD-κS structure (only Si channel) is further evident
5 from the comparison with crucial performance benchmark of The variation in SNM’s, read current and delay in
6 other state-of-the-art JLFETs [20, 21] as shown in Figure 5 SymD-κ and AsymD-κS devices with varying gate metal
7 (d). work function difference for Si (Ge) is shown in Figure 7 (a)
8 The comparison of 6T-SRAM performance between the to (c). It is observed that both read current and SNM
9 devices under consideration (both Si and Ge channel) is performance is better for devices with positive ΔΦM (ΦM1>
10 portrayed in Figure 6 (a)-(h). For all the static noise margins ΦM2) [Figure 7 (a) to (b)] though the impact on delay is
11 (SNMs) (read, write and hold) AsymD-κS and SymD-κ minimal [Figure 7 (c)]. Higher ΦM1 causes a relatively
12 stronger depletion in the channel region near the source and a
devices show comparable figures though it is slightly better
13 better screening of the channel from drain bias by M 2 thus
for the former one. There is a 11.7% (9.2%) and 8.9% (7.8%)
14 reducing SCEs (DIBL) and increasing the overall gate
increase in RSNM [Figure 6 (a)], 5.3% (8%) and 3.6%
15 control over the channel [18, 26].
(7.2%) increase in WSNM [Figure 6 (b)] and 8.07% (9.02%)
16 SNM’s, read current and delay variations in SymD-κ and
and 10.3% (10.5%) increase in HSNM [Figure 6 (c)] in
17 AsymD-κS structures with varying high-κ spacer length for
18 SymD-κ and AsymD-κS architectures as compared to the
conventional (no spacer) one for Si (Ge). Although the Si (Ge) is shown in Figure 8 (a) to (c).
19
20 higher current driving capability in SymD-κ transistor helps
(a) (b)
21 to enhance the read and write margin as compared to the 200 RSNM, AsymD-kS, Ge
290 0.8
Read Current, AsymD-kS, Ge
330
VDD=0.7V VDD=0.7V Read Current, SymD-k, Si

asymmetric one, the marginal ͠2% increase in HSNM in

RSNM, SymD-k, Si

22
Read Current, AsymD-kS, Si
RSNM, AsymD-kS, Si
Read Current, SymD-k, Ge
RSNM, SymD-k, Ge
190 WSNM, AsymD-kS, Si 280 HSNM, AsymD-kS, Si
HSNM, SymD-k, Si
320
WSNM, SymD-k, Si

23 AsymD-κS device is due to better SCEs [23-25].

Read Current (mA)

WSNM, AsymD-kS, Ge 0.6 HSNM, AsymD-kS, Ge

Hold SNM (mV)

Write SNM (mV)
Read SNM (mV)
WSNM, SymD-k, Ge HSNM, SymD-k, Ge

180 270 310

24 The delay performance is almost comparable in all of 300
25 the cases though the SymD-κ and AsymD-κS devices shows 170 260 0.4
290
26 slightly better read and write delay performances 160 250
280
27 respectively [Figure 6 (d) and (e)]. This can be explained as 150 240
0.2
270
28 follows. Delay mainly depends on ION and Cgg [22]. The −0.4 −0.2 0.0 0.2 0.4 0.6 −0.4 −0.2 0.0 0.2 0.4 0.6
29 performance gains obtained by the SymD-κ and AsymD-κS (fM1-fM2) (eV) (fM1-fM2) (eV)

30 FinFETs in terms of higher on state current is neutralized by (c)

40
31 an increase in outer fringe capacitance component (Cof) in VDD=0.7V

32 spacer-based structures which in turn increases the overall 30 30

Write Delay (ps)

Read Delay (ps)

33 gate capacitance (Cgg) (please note Cgg=Cif+Cof, where Cif is

34
Read Delay, AsymD-kS, Ge
Read Delay, SymD-k, Si
20
the inner fringe capacitance). Though SRAM power Read Delay, AsymD-kS, Si
Read Delay, SymD-k, Ge

35
20 Write Delay, AsymD-kS, Si

consumption (dynamic+leakage) depends on a lot of factors Write Delay, SymD-k, Si

Write Delay, AsymD-kS, Ge

36
Write Delay, SymD-k, Ge
10
like, supply voltage, process variations, temperature
37 fluctuations etc., but we are not going into the minute details 10
38
0
−0.4 −0.2
regarding all these in the current study. SymD-κ device 0.0 0.2 0.4 0.6

39 shows slightly better read (write) power characteristics

(fM1-fM2) (eV)

40 [Figure 6 (f) and (g)] mainly due to lower leakage (current)

41 Figure 7. Comparison of (a) RSNM-WSNM (b) Read current-
power, less discharge activity on the read/write bit lines and HSNM (c) Read delay-Write delay for AsymD-κS and SymD-κ
42
less swing voltage at the PD (pull down) transistors (in case (both Si and Ge) JL-FinFET architectures at VDD=0.7V with
43
of read operation). The read current of an SRAM increases varying gate metal work function difference.
44
with the drain current primarily due to the influence of the It is observed that when inner high-κ (HfO2) spacer length
45
access transistors in the SRAM cell. During read operation, is increased (keeping underlap length fixed), all the
46
the access transistors are activated to allow the stored data to performance metrices shows improvement up to an optimal
47
48 be accessed through the bit lines. A higher drain current in point (close to the junction) after which it is saturated. With
49 the access transistors results in a stronger driving capability, an increase in high-κ spacer length, due to increase in electric
50 allowing for faster and more reliable read operations. This is field coupling between gate and the underlap portion, ION
51 further reflected in the results as shown in Figure 6 (h) where increases which causes betterment in terms of SNM, read
52 the SymD-κ structure outperforms its AsymD-κS counterpart current and delay behavior. But after a certain length, the
53 by 6.8% (20%) for Si (Ge). spacer induced improvements is diluted by an increase in
54 outer fringe capacitance Cof which in turn causes an overall
55 increase in G-S/D parasitic capacitances.
56
57
58
59
60

5
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1
2
3 200
(a) 300
(b) overall perfromance. This is mainly becauase a large voltage
0.8
4 VDD=0.7V Read Current, AsymD-kS, Ge
Read Current, SymD-k, Si
Read Current, AsymD-kS, Si
330 drop across underlap length reduces the drive current,
5 190 290 Read Current, SymD-k, Ge
HSNM, AsymD-kS, Si
HSNM, SymD-k, Si 320 thereby causing the performance degradation.

Read Current (mA)

0.6

Write SNM (mV)

6
HSNM, AsymD-kS, Ge
Read SNM (mV)

Hold SNM (mV)

180 280 HSNM, SymD-k, Ge

310 Finally, from the 6T-SRAM metrics variatrion for

7 170
270
0.4
300 SymD-κ and AsymD-κS devices with varying VDD for Si
8 RSNM, AsymD-kS, Ge
RSNM, SymD-k, Si 260 290 (Ge) displayed in Figure 10 (a) to (c), it is observed that
160
9
RSNM, AsymD-kS, Si
RSNM, SymD-k, Ge
WSNM, AsymD-kS, Si
WSNM, SymD-k, Si 250 0.2 280 SRAM performance gets better in super-threshold region and
10 VDD=0.7V
WSNM, AsymD-kS, Ge
150 WSNM, SymD-k, Ge

240 270 show steady improvement at higher VDD. This is due to the
11 1.0 1.5 2.0 2.5 3.0 3.5
High Spacer Length (Lsp)
4.0 1.0 1.5 2.0 2.5 3.0 3.5
Spacer Length (Lsp)
4.0
increase in gate coupling through inner high-k spacer that
12 (c) decreases source side resistance with an increase in VDD.
13 VDD=0.7V
14
30
30
(a) (b)
15
Write Delay (ps)
220 0.50
Read Delay (ps)

Read Delay, AsymD-kS, Ge

Read Delay, SymD-k, Si 320 340
16 Read Delay, AsymD-kS, Si
Read Delay, SymD-k, Ge
Write Delay, AsymD-kS, Si
20
200 0.45
300
17
20 Write Delay, SymD-k, Si
320

Write SNM (mV)

Hold SNM (mV)

Write Delay, AsymD-kS, Ge

Read Current (mA)

Read SNM (mV)
Write Delay, SymD-k, Ge
180 0.40
18 10 280
300

19 10
160 260 0.35
280
20
RSNM, AsymD-kS, Ge
0 RSNM, SymD-k, Si 240 0.30
Read Current, AsymD-kS, Ge

1.0 1.5 2.0 2.5 3.0 3.5 4.0 140 RSNM, AsymD-kS, Si
Read Current, SymD-k, Si
Read Current, AsymD-kS, Si

21
RSNM, SymD-k, Ge
High Spacer Length (Lsp) WSNM, AsymD-kS, Si
Read Current, SymD-k, Ge
260
WSNM, SymD-k, Si 220 HSNM, AsymD-kS, Si
HSNM, SymD-k, Si
120 WSNM, AsymD-kS, Ge 0.25 HSNM, AsymD-kS, Ge

22
WSNM, SymD-k, Ge HSNM, SymD-k, Ge
200 240
0.4 0.8 1.2 1.6 2.0 0.4 0.8 1.2 1.6 2.0
23 Figure 8. Comparison of (a) RSNM-WSNM (b) Read current- Supply Voltage (VDD) Supply Voltage (VDD)

24 HSNM (c) Read delay-Write delay for AsymD-κS and SymD-κ

(c)
(both Si and Ge) JL-FinFET architectures at VDD=0.7V with
25 16 Read Delay, AsymD-kS, Ge

varying high-κ spacer length.

Read Delay, SymD-k, Si

26
Read Delay, AsymD-kS, Si
Read Delay, SymD-k, Ge
Write Delay, AsymD-kS, Si
30
(a) (b) Write Delay, SymD-k, Si

27
Write Delay, AsymD-kS, Ge
14

Write Delay (ps)

Read Delay (ps)
Write Delay, SymD-k, Ge
RSNM, AsymD-kS, Ge
0.5 28
28 VDD=0.7V 295
RSNM, SymD-k, Si
168 VDD=0.7V RSNM, AsymD-kS, Si 290
RSNM, SymD-k, Ge
12
29
WSNM, AsymD-kS, Si
WSNM, SymD-k, Si 290 26
Read Current (mA)

WSNM, AsymD-kS, Ge
0.4
Write SNM (mV)

Hold SNM (mV)

WSNM, SymD-k, Ge
280
30
164
Read SNM (mV)

285 10
31 160 270 0.3
280
24

32 Read Current, AsymD-kS, Ge

Read Current, SymD-k, Si
8
0.4 0.8 1.2 1.6 2.0
275
33
260 0.2 Read Current, AsymD-kS, Si
156 Read Current, SymD-k, Ge Supply Voltage (VDD)
HSNM, AsymD-kS, Si

34
HSNM, SymD-k, Si
HSNM, AsymD-kS, Ge
270 Figure 10. Comparison of (a) RSNM-WSNM (b) Read current-
250 HSNM, SymD-k, Ge
152 0.1
35 8 10 12 14 8 10 12 14
265 HSNM (c) Read delay-Write delay for AsymD-κS and SymD-κ
36 Underlap Length (LUND) Underlap Length (LUND) (both Si and Ge) JL-FinFET architectures at VDD=0.7V with VDD.
37 (c)
38 16
Read Delay, AsymD-kS, Ge
Read Delay, SymD-k, Si
VDD=0.7V 5. Conclusion
Read Delay, AsymD-kS, Si 32
39
Read Delay, SymD-k, Ge
Write Delay, AsymD-kS, Si
Write Delay, SymD-k, Si
In this paper, we provide a detailed investigation of the
40
Write Delay, AsymD-kS, Ge
Write Delay (ps)

Write Delay, SymD-k, Ge

Read Delay (ps)

14 30
device electrostatics, current characteristics, SCE metrics and
41
mixed mode circuit behavior in the form of 6T-SRAM and 3
42
28
12
stage RO for conventional, dual-κ symmetric spacer,
43 26
asymmetric dual-κ source and drain side spacer; dual
44 10
material gate JL-FinFET architectures for both Si and Ge
45 24
channel materials. Optimization of important SRAM
46 8 10 12
Underlap Length (LUND)
14

47 performance parameters with respect to gate metal work

48 function, high-κ spacer length, underlap length and supply
Figure 9. Comparison of (a) RSNM-WSNM (b) Read current- voltage is also presented. It is found that in general the Ge
49 HSNM (c) Read delay-Write delay for AsymD-κS and SymD-κ
50 devices outperform their Si counterparts in most of the
(both Si and Ge) JL-FinFET architectures at VDD=0.7V with
51 occasions owing to higher channel mobility of Ge, although
varying underlap length.
52 a trade off must be made with higher off state leakage in Ge
53 Variation in FinFET SRAM cell’s performance
due to its lower bandgap. The SymD-κ device shows better
54 parameters in SymD-κ and AsymD-κS transistors with
performance in terms of drive current and SNM but shows a
55 varying underlap length for Si (Ge) is shown in Figure 9 (a)
degraded control over SCE as compared to the AsymD-κS
56 to (c). It may be noted from Figure 9 that with an increase in
structure because of increase in parasitic capacitance. On a
57 whole higher work function of source side gate material, a
underlap length there is a significant deterioration in SRAMs
58
59
60

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1
2
3 high optimized value of inner high-κ spacer length and lower [5] Singh S and Chaudhary T 2022 Performance and comparative
4 underlap length is found to be the most suitable combination analysis of heterojunction structure based GAA-NWTFET for
5 for providing lower read/write delay and improved SRAM low power applications Silicon 14 9813–20
6 noise margins. [6] Bhattacharjee A, Saikiran M, Dutta A, Anand B and Dasgupta
7 S 2015 Spacer engineering-based high-performance
8 reconfigurable FET with low OFF current characteristics
Acknowledgements IEEE Electron Device Lett. 36 520–2
9
[7] Bhattacharjee A and Dasgupta S 2016 Optimization of design
10 This research is supported by the Department of
parameters in dual-k spacer-based nanoscale reconfigurable
11 Electronics and Communication Engineering, Tripura
FET for improved performance IEEE Trans. Electron Devices
12 Institute of Technology, Narsingarh, Tripura, India, School
63 1375–82
13 of Electronics Engineering, Vellore Institute of Technology, [8] Bhattacharjee A and Dasgupta S 2017 Impact of gate/spacer-
14 Chennai, India, Department of Electronics and channel underlap, gate oxide EOT, and scaling on the device
15 Communication Engineering, IIT Roorkee, Roorkee, India, characteristics of a DG-RFET IEEE Trans. Electron Devices
16 and The School of Engineering and Technology, Central 64 3063–70
17 Queensland University, Melbourne Campus, VIC 3000, [9] Bhattacharjee A, Saikiran M and Dasgupta S 2017 A first
18 Australia. insight to the thermal dependence of the DC, analog and RF
19 performance of an S/D spacer engineered DG-ambipolar FET
20 Author contributions IEEE Trans. Electron Devices 64 4327–34
21 [10] Bhattacharjee A and Dasgupta S 2018 A compact physics-
22 A.B., T.M., S.D., and N.D. were involved in supervision and based surface potential and drain current model for an S/D
project administration. UC. was formulated experimental spacer-based DG-RFET IEEE Trans. Electron Devices 65
23
manipulation and data processing. U.C. and A.B. was 448–55
24
involved in investigation and writing the paper. [11] Kaur N, Gill S S and Kaur P 2022 Performance Evaluation of
25 Junctionless FinFET using Spacer Engineering at 15 nm Gate
26 Length Silicon 14 10989–1000
27 Funding
[12] Jeon D-Y, Mouis M, Barraud S and Ghibaudo G 2020
28 No Funding. Channel width dependent subthreshold operation of tri-gate
29 junctionless transistors Solid State Electron. 171 107860
30 Data availability [13] Mangal G, Tyagi A and Chaujar R 2022 Numerical
31 investigation and temperature-based analysis of the analog
32 All data can be made available to interest readers upon performance of fully gate-covered junctionless FinFET
33 request. Comput. Electr. Eng. 101 108071
34 [14] Mehrdad F and Ahangari Z 2022 Design and simulation of a
35 Declarations gas sensitive junctionless FinFET based on conducting
polymer as the gate material Phys. Scr. 97 075805
36
Conflict of interest The authors declare no conflict of [15] Han M-H, Chang C-Y, Chen H-B, Cheng Y-C and Wu Y C
37
interest for the research presented. 2013 Device and circuit performance estimation of JL bulk
38
Ethical approval No experiments involved human tissue. Fin-FETs IEEE Trans. Electron Devices 60 1807–13
39 [16] Sil M, Guin S, Nawaz S M and Mallik A 2019 Performance
40 of Ge p-channel junctionless FinFETs for logic applications
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