Metallization
Critical Components of a Multilevel
Metallization Circuit
Outline
Interconnects
• Metal lines (within one or
several layers) routed for
sending signals between
devices, distributing clocks,
power and ground
• Metal via plugs for
connecting two metal layers
on different planes
• Inter Metal Dielectric
(IMD) separating the metal
lines
• Pads for input/output of
signals
• Ohmic contact to silicon
Short interconnect delays are desired i. e. minimum resistance
and minimum capacitance
Interconnect Metallization
• Six layers of Cu metallization
– Lower layers are finer and are
used for “local” interconnection
between cells
– Middle layers are wider and are
used for global interconnection
between blocks
– Upper layers are wider and are
used for clocks, ground and power
distribution
– Oxide is the Inter Metal
Dielectric (etched)
Interconnect RC Time Delay
CT = CV + 2CL
• Need low ρ to minimize RC delay
• Need low εox to minimize RC delay
Interconnect Requirements
• Low ohmic resistance
– Interconnects material has low resistivity
• Low contact resistance to semiconductor device
• Reliable long-term operation
Possible Interconnect Materials
• Metal (Low resistivity)
– for long interconnects
• Highly doped Poly-Si (Medium resistivity)
–for short interconnects
• Highly doped diffused regions in Si substrate (Medium
resistivity)
–for short interconnects
Metal Contact to Si
Metal Semiconductor
Contact Resistance Rc
Approaches to lowering of contact resistance:
1) Use highly doped Si as contact semiconductor
2) Choose metal with lower Schottky barrier height
Which Metal(s)?
• Al used to be the pre-dominant metal for VLSI
• Why Al?
• Low resistivity Al at room temperature (2-3µΩcm).
•It adheres (hold fast or stick by) well to Si and SiO2
•It makes good electric Ohmic contact to heavily doped Si
• It react with SiO2 even at low T, forming a thin layer of
Al2O3 at the interface, which act as a glue layer to bind the
Al to the SiO2.
• In case of Al-to-Si contact, the Al reduce any native oxide
on top of Si, which could prevent ohmic contact
• Its presence assist the annealing out of interface traps at
the Si-SiO2 interface.
Al Spiking Problem
• Solubility of Si in Al is high
– 0.5 atomic % @ 450°C
– 1 atomic % @500 °C
• A large amount of Si is
drawn up into Al creating
voids
• Voids filled by Al leading to
spiking (0.2-1µm) that can
cause high leakage or shorts
in shallow junctions.
Methods Used to Reduce Spiking
• Add ~ 2% Si to Al to prevent Si outdiffusion
• Widely used, but Si can precipitate when cooling down, leaving
Si nodules that increase contact resistance.
Better solution: Use diffusion
barrier layer to block Al/substrate
interaction
Example: Ti or TiSi2 for good
contact and adhesion, AND TiN for
diffusion barrier
TiSi2/TiN is not the only choice, various barrier options are available.
Hillocks, Voids and Electromigration
• Hillocks and voids form because of
stress and diffusion in Al films.
• Heating places Al under
compression hillocks.
• Cooling back down can place Al
under tension voids.
• Adding few % Cu stabilizes grain
boundaries and minimizes hillock
formation.
Electromigration
Migration of Al atoms under electric currents due to the momentum
transfer from electrons to atoms (electron wind force).
•Electromigrated metal atoms move along the same direction of
electrons
Electromigration Effects
• Voids or hillocks form at the sites of flux divergences.
• Growth of voids or hillock causes open circuit failure or
short circuit failure of interconnects
⇒ Reliability problem
EM-Induced Failures
At the line
• During electromigration, atoms move in the direction of the
electron flow.
• Voids form at the cathode and hillocks form at the anode.
EM-Induced Failures (contd.)
2) At the vias (materials are discontinuous due to W via or barrier
layer (TiN, Ta))
=> Most dominant failure site
Solution: Al Alloying
• The yield strength and electromigration resistance of
pure Al can be improved with alloy additions, such as Cu,
Ti, Sc, Vd, Pd, Cr, Mg, Ni, etc.
• Draw back of alloying: 1) increase Al resistivity
2) difficult to etching
• Cu has found to be the best choice among other
alloying elements.
• Interconnects mostly used:
Al - (1-2 wt%) Si - (0.5-1 wt%) Cu alloy
Al - (0.5-1 wt%) Cu alloy
Al Stacks
• Modern interconnect is not a single layer of Al(Cu). It has top and bottom
layers with Ti, TiN (or both).
• Multilayer Interconnect = Underlayer + Conductor + Overlayer
• Underlayer : Ti, TiN, Ti/TiN
- This is an adhesion layer that alters grain size and crystallographic
orientation of Al
- Ti contact with Al, it forms TiAl3.
• Overlayer: Ti ,TiN, graded TiN
- Serves as an Anti-Reflective Coating (ARC) for lithography
and influences the via resistance
• Underlayer and overlayer serve as a shunt layer if a void should form in the Al
conductor due to electromigration.
Next Development: Metal Silicides
Formed by reaction of metal with Si e.g. TiSi2, TaSi2, MoSi2, CoSi2, WSi2, PtSi2 etc
Applications:
• Gate Metallization (Polycide) - 1
• Ohmic Contact/Barrier technology – 2
• Local Interconnects - 3
Silicide offers:
• Low electric resistivity
• Stable at high temperature
• Easy to plasma etch
• Provide good contact to
other material
• Do not exhibit much
electromigration
Multilevel Metallization
Two or more layers of interconnects are necessary for highly
integrated circuits
• Nonplanar topography leads
to lithography, step coverage,
filling issues.
• Nonplanar topography result
in nonuniform resist thickness,
which can result in nonuniform
exposure and development.
• These issues get worse with
additional levels of interconnect
and required a change of
structure!
Example of Nonplanar Topography
Planarization
Reducing the step heights and achieving more planer technology
through processing technique is called planarization. The degree
of planarization (DOP) is defined as,
W Plugs for Contact and Vias
• One planarization technique is the use of W plug for contacts and vias.
• W plug fabrication process sequences
Multilayer Interconnect Structures
• W plug resulting good planarity
• TiSi2 is used to make good electric
contact with Si.
• TiN surrounds the W, promoting
adhesion to the oxide.
• Cu in the Al suppresses
electromigration and hilllock formation.
• Ti improves the grain texture of the Al
for better electromigration protection
and promotes adhesion.
• TiN is a barrier between the Al and Ti to
limit TiAl3 formation.
• TiN layer on the top also acts as an
antireflective layer for lithography.
Historical Evolution
Historical Evolution
Interlayer Dielectrics (ILD)
• Dielectric provides electrical insulation between metal
layers and lines. It also provides physical protection.
• Deposited SiO2 has been used, but recently others are being
considered.
• Requirement of Dielectrics
- Low dielectric constant
- High break down field strength (>5MV/cm)
- Low leakage, No Moisture absorption
- Good adhesion
- Stable up to 500°C
- High resistance of crack
Interlayer Dielectrics (ILD) (contd.)
First level dielectrics:
Before Al deposition Can process at higher temperature
• Silane based LPCVD (low pressure CVD)
• Doped Silicate Glass (PSG, BPSG) + anneal (800-1000°C) give
smooth topography over steps.
Intermetal dielectric:
• Should be deposited <500°C.
• Can form voids.
• LPCVD cannot fill narrow gaps. For conformal and smoother deposition,
PECVD, HDP-CVD have been used.
- PECVD combines a plasma with CVD
- HDP oxide is a high-density plasma and provides best gap fill.
• Planarization is necessary