Different Types of Instruction Fields

A computer performs a task based on the instructions provided. Instructions in computers are
comprised of groups called fields. These fields contain different information for computers
which are all written in 0s and 1s. Each field has a different significance or meaning, based
on which a CPU decides what to perform.
The most common fields are:
The operation field specifies the operation to be performed, like addition.
Address field which contains the location of the operand, i.e., register or memory location.
Mode field which specifies how operand is to be founded.
An instruction is of variable length depending upon the number of addresses it contains.
Generally, CPU organization is of three types based on the number of address fields:
Single Accumulator organization: In this, the operation is performed using a special
register called the accumulator.
General register organization : In Register Organization, multiple registers are used for the
computation purpose.
Stack organization: In the third organization, the work on stack basis operation due to which
it does not contain any address field.
Types of Instructions
Based on the number of addresses, instructions are classified as:
NOTE: We will use the X = (A+B)*(C+D) expression to showcase the procedure.
Zero Address Instructions
These instructions do not specify any operands or addresses. Instead, they operate on data
stored in registers or memory locations implicitly defined by the instruction. For example, a
zero-address instruction might simply add the contents of two registers together without
specifying the register names.

Zero Address Instruction

A stack-based computer does not use the address field in the instruction. To evaluate an
expression, it is first converted to reverse Polish Notation i.e. Postfix Notation.
Expression: X = (A+B)*(C+D)
Postfixed : X = AB+CD+*
TOP means top of stack
M[X] is any memory location

Operation Instruction Stack (TOP Value After Execution)

Push A PUSH A TOP = A
Push B PUSH B TOP = B
Add ADD TOP = A + B
Push C PUSH C TOP = C
Push DPUSH D TOP = D
Add ADD TOP = C + D
Multiply MUL TOP = (C + D) * (A + B)
Pop X POP X M[X] = TOP

One Address Instructions

These instructions specify one operand or address, which typically refers to a memory
location or register. The instruction operates on the contents of that operand, and the result
may be stored in the same or a different location. For example, a one-address instruction
might load the contents of a memory location into a register.
This uses an implied ACCUMULATOR register for data manipulation. One operand is in the
accumulator and the other is in the register or memory location. Implied means that the CPU
already knows that one operand is in the accumulator so there is no need to specify it.

One Address Instruction

Expression: X = (A+B)*(C+D)
AC is accumulator
M[] is any memory location
M[T] is temporary location
Operation Instruction Stack / Register (AC / M[])
Load A AC = A AC = A
Add B AC = AC + B AC = A + B
Store M[T] M[T] = AC M[T] = A + B
Load C AC = C AC = C
Add D AC = AC + D AC = C + D
Store M[] M[] = AC M[] = C + D
Multiply M[T]AC = AC * M[T] AC = (A + B) * (C + D)
Store X M[X] = AC M[X] = (A + B) * (C + D)

Two Address Instructions

These instructions specify two operands or addresses, which may be memory locations or
registers. The instruction operates on the contents of both operands, and the result may be
stored in the same or a different location. For example, a two-address instruction might add
the contents of two registers together and store the result in one of the registers.
This is common in commercial computers. Here two addresses can be specified in the
instruction. Unlike earlier in one address instruction, the result was stored in the accumulator,
here the result can be stored at different locations rather than just accumulators, but require
more number of bit to represent the address.

Two Address Instruction

Here destination address can also contain an operand.
Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location

Operation Instruction Registers / Memory (R1, R2, M[])

Load A R1 = A R1 = A
Add B R1 = R1 + B R1 = A + B
Store M[T] M[T] = R1 M[T] = A + B
Load C R2 = C R2 = C
Add D R2 = R2 + D R2 = C + D
Store M[] M[] = R2 M[] = C + D
Multiply M[T] R1 = R1 * M[T] R1 = (A + B) * (C + D)
Store X M[X] = R1 M[X] = (A + B) * (C + D)

Three Address Instructions

These instructions specify three operands or addresses, which may be memory locations or
registers. The instruction operates on the contents of all three operands, and the result may be
stored in the same or a different location. For example, a three-address instruction might
multiply the contents of two registers together and add the contents of a third register, storing
the result in a fourth register.

This has three address fields to specify a register or a memory location. Programs created are
much short in size but number of bits per instruction increases. These instructions make the
creation of the program much easier but it does not mean that program will run much faster
because now instructions only contain more information but each micro-operation (changing
the content of the register, loading address in the address bus etc.) will be performed in one
cycle only.

Three Address Instruction

Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location

Operation Instruction Registers / Memory (R1, R2, M[])

Load A R1 = A R1 = A
Add B R1 = R1 + B R1 = A + B
Store M[T] M[T] = R1 M[T] = A + B
Load C R2 = C R2 = C
Add D R2 = R2 + D R2 = C + D
Store M[] M[] = R2 M[] = C + D
Multiply M[T] R1 = R1 * M[T] R1 = (A + B) * (C + D)
Store X M[X] = R1 M[X] = (A + B) * (C + D)

Advantages of Zero-Address, One-Address, Two-Address and Three-Address

Instructions
Zero-address instructions
Stack-based Operations: In stack-based architectures, where operations implicitly employ the
top items of the stack, zero-address instructions are commonly used.
Reduced Instruction Set: It reduces the complexity of the CPU design by streamlining the
instruction set, which may boost reliability.
Less Decoding Complexity: Especially helpful for recursive or nested processes, which are
frequently used in function calls and mathematical computations.
Efficient in Nested Operations: Less bits are required to specify operands, which simplifies
the logic involved in decoding instructions.
Compiler Optimization: Because stacks are based on stacks, several algorithms can take use
of this to improve the order of operations.
One-address instructions
Intermediate Complexity: Strikes a balance between versatility and simplicity, making it
more adaptable than zero-address instructions yet simpler to implement than multi-address
instructions.
Reduced Operand Handling: Compared to multi-address instructions, operand fetching is
made simpler by just needing to handle a single explicit operand.
Implicit Accumulator: O ften makes use of an implicit accumulator register, which can
expedite up some operations’ execution and simplify designs in other situations.
Code Density: S maller code in comparison to two- and three-address instructions, which
may result in more efficient use of memory and the instruction cache.
Efficient Use of Addressing Modes: Can make use of different addressing modes (such
indexed, direct, and indirect) to improve flexibility without adding a lot of complexity.
Two-address instructions
Improved Efficiency: Allows for the execution of operations directly on memory or registers,
which reduces the amount of instructions required for certain activities.
Flexible Operand Use: Increases programming variety by offering more options for operand
selection and addressing modes.
Intermediate Data Storage: May directly store interim results, increasing some algorithms’
and calculations’ efficiency.
Enhanced Code Readability: Produces code that is frequently easier to read and comprehend
than one-address instructions, which is beneficial for maintenance and troubleshooting.
Better Performance: Better overall performance can result from these instructions because
they minimize the amount of memory accesses required for certain processes.
Three-address instructions
Direct Representation of Expressions: Reduces the need for temporary variables and extra
instructions by enabling the direct representation of complicated expressions.
Parallelism: Allows for the simultaneous fetching and processing of several operands, which
facilitates parallelism in CPU architecture.
Compiler Optimization: Makes it possible for more complex compiler optimizations to be
implemented, which improve execution efficiency by scheduling and reordering instructions.
Reduced Instruction Count: May increase execution performance even with bigger instruction
sizes by perhaps lowering the overall number of instructions required for complicated
processes.
Improved Pipeline Utilization: More information in each instruction allows CPU pipelines to
be used more efficiently, increasing throughput overall.
Better Register Allocation: Permits direct manipulation of several registers inside a single
instruction, enabling more effective usage of registers.
Disadvantages of Zero-Address, One-Address, Two-Address and Three-Address
Instructions
Zero-address instructions
Stack Dependency: In contrast to register-based architectures, zero-address instructions might
result in inefficiencies when it comes to operand access because of their heavy reliance on the
stack.
Overhead of Stack Operations: Performance might be negatively impacted by the frequent
push and pop actions needed to maintain the stack.
Limited Addressing Capability: The processing of intricate data structures may become more
difficult since they do not directly support accessing memory regions or registers.
Difficult to Optimize: Because operand access is implied in stack-based designs, code
optimization might be more difficult.
Harder to Debug: When compared to register-based operations, stack-based operations might
be less obvious and more difficult to debug.
One-address instructions
Accumulator Bottleneck: Often uses an accumulator, which can act as a bottleneck and
reduce efficiency and parallelism.
Increased Instruction Count: Multiple instructions may be needed for complex processes,
which would increase the overall number of instructions and code size.
Less Efficient Operand Access: There is just one operand that is specifically addressed, which
might result in inefficient access patterns and extra data management instructions.
Complex Addressing Modes: The instruction set and decoding procedure get more
complicated when several addressing modes are supported.
Data Movement Overhead: Moving data between memory and the accumulator could need
more instructions, which would increase overhead.
Two-address instructions
Operand Overwriting: Usually, the result overwrites one of the source operands, which might
lead to an increase in the number of instructions needed to maintain data.
Larger Instruction Size: Because two-address instructions are bigger than zero- and one-
address instructions, the memory footprint may be increased.
Intermediate Results Handling: It is frequently necessary to handle intermediate outcomes
carefully, which can make programming more difficult and result in inefficiencies.
Decoding Complexity: The design and performance of the CPU may be impacted by the
greater complexity involved in decoding two addresses.
Inefficient for Some Operations: The two-address style could still be inefficient for some
tasks, needing more instructions to get the desired outcome.
Three-address instructions
Largest Instruction Size: Has the highest memory requirements per instruction, which can put
strain on the instruction cache and increase code size.
Complex Instruction Decoding: Three addresses to decode adds complexity to the CPU
architecture, which might affect power consumption and performance.
Increased Operand Fetch Time: Each instruction may execute more slowly if obtaining three
operands takes a long period.
Higher Hardware Requirements: Has the potential to raise cost and power consumption since
it requires more advanced hardware to handle the higher operand handling and addressing
capabilities.
Power Consumption: Higher power consumption is a crucial factor for devices that run on
batteries since it can be caused by more complicated instructions and increased memory
utilization.
Overall, the choice of instruction format depends on the specific requirements of the
computer architecture and the trade-offs between code size, execution time, and flexibility.
RISC and CISC in Computer Organization
RISC is the way to make hardware simpler whereas CISC is the single instruction that
handles multiple work. In this article, we are going to discuss RISC and CISC in detail as
well as the Difference between RISC and CISC, Let’s proceed with RISC first.
Reduced Instruction Set Architecture (RISC)
The main idea behind this is to simplify hardware by using an instruction set composed of a
few basic steps for loading, evaluating, and storing operations just like a load command will
load data, a store command will store the data.
Characteristics of RISC
Simpler instruction, hence simple instruction decoding.
Instruction comes undersize of one word.
Instruction takes a single clock cycle to get executed.
More general-purpose registers.
Simple Addressing Modes.
Fewer Data types.
A pipeline can be achieved.
Advantages of RISC
Simpler instructions: RISC processors use a smaller set of simple instructions, which
makes them easier to decode and execute quickly. This results in faster processing times.
Faster execution: Because RISC processors have a simpler instruction set, they can
execute instructions faster than CISC processors.
Lower power consumption: RISC processors consume less power than CISC
processors, making them ideal for portable devices.
Disadvantages of RISC
More instructions required: RISC processors require more instructions to perform
complex tasks than CISC processors.
Increased memory usage: RISC processors require more memory to store the
additional instructions needed to perform complex tasks.
Higher cost: Developing and manufacturing RISC processors can be more expensive
than CISC processors.
Complex Instruction Set Architecture (CISC)
The main idea is that a single instruction will do all loading, evaluating, and storing
operations just like a multiplication command will do stuff like loading data, evaluating, and
storing it, hence it’s complex.
Characteristics of CISC
Complex instruction, hence complex instruction decoding.
Instructions are larger than one-word size.
Instruction may take more than a single clock cycle to get executed.
Less number of general-purpose registers as operations get performed in memory
itself.
Complex Addressing Modes.
More Data types.
Advantages of CISC
Reduced code size: CISC processors use complex instructions that can perform
multiple operations, reducing the amount of code needed to perform a task.
More memory efficient: Because CISC instructions are more complex, they require
fewer instructions to perform complex tasks, which can result in more memory-efficient
code.
Widely used: CISC processors have been in use for a longer time than RISC
processors, so they have a larger user base and more available software.
Disadvantages of CISC
Slower execution: CISC processors take longer to execute instructions because they
have more complex instructions and need more time to decode them.
More complex design: CISC processors have more complex instruction sets, which
makes them more difficult to design and manufacture.
Higher power consumption: CISC processors consume more power than RISC
processors because of their more complex instruction sets.
CPU Performance
Both approaches try to increase the CPU performance

RISC: Reduce the cycles per instruction at the cost of the number of instructions per program.

CISC: The CISC approach attempts to minimize the number of instructions per program but
at the cost of an increase in the number of cycles per instruction.
Earlier when programming was done using assembly language, a need was felt to make
instruction do more tasks because programming in assembly was tedious and error-prone due
to which CISC architecture evolved but with the uprise of high-level language dependency on
assembly reduced RISC architecture prevailed.
Example:
Suppose we have to add two 8-bit numbers:
CISC approach: There will be a single command or instruction for this like ADD which will
perform the task.
RISC approach: Here programmer will write the first load command to load data in registers
then it will use a suitable operator and then it will store the result in the desired location.
So, add operation is divided into parts i.e. load, operate, store due to which RISC programs
are longer and require more memory to get stored but require fewer transistors due to less
complex command.