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Stability study on dynamic voltage restorer (DVR)

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 Stability Study on Dynamic Voltage Restorer (DVR)
Chi-Seng Lam', Man-Chung Wong', Ying-Duo Han'32
I
Department of Electrical and Electronics Engineering, University of Macau, Macau, SAR, P. R. China
2
Department of Electrical Engineering, Tsinghua University, Beijing, P. R. China
E-mail: ma34576@[Link]

Abstract -This paper discusses the stability study in dynamic order to obtain good system performance [2]-[4], [7]-[9].
voltage restorer @VR), a series compensation device mainly In addition, there are very few authors focused on the time
used to mitigate voltage sags. Based on the appropriate delay, damping factor, nonlinear element in the filter
modeling of the DVR system, the detailed stability analysis of inductor 121, [3], which is related to the system stability
the DVR system is performed. This research work is an
problem. However, the load impact on the system stability
attempt to obtain mathematical interactions between the
DVR and linear loads. In this paper, theoretical study of was not included. For the impact of load transients on the
different linear load effects on the system stability will be DVR, the static load and the induction motor load will
proposed and analyzed, in which the stable operation range exhibit drastic dynamic responses under the voltage phase
of the DVR is investigated. Moreover, a significant reduction shift. Greater phase shift changes will produce more
of inverter gain in the situation of over-modulation can drastic oscillations. For parallel loads, the impedance
strongly affect the system stability. The results of simulation between the source and loads could mitigate the effect of
are presented to validate the load stability analysis and over- the step voltage phase shift. When the DVR device is
modulation effect to the inverter gain, a key parameter installed very close to the loads, the response of loads
affecting the system stability
under the step voltage will cause largest impact on the
Keywords - Dynamic Voltage Restorer (DVR), stability, load, system [lo]. In which this author has considered the effect
inverter gain, over-modulation, modulation index of load to the system, but not yet set up a generalized
stability range for the DVR system.

NOMENCLATURE The objective of this paper is to study and analyze the

stability involved in the DVR and to observe the
Peak of rhe associates waveform significant effect of the load on the system stability, which
Triangle carrier may sometimes be neglected. Based on the proposed
Sinusoidal phase voltage command generalized equation, the theoretical stability study of
Modulation index = e*/ ,$ linear load effect on the system stability via ROUTH-
HURWITZ criterion will be presented. The PWM voltage
DC bus voltage source inverter gain also becomes nonlinear in the over-
Filtering inductor modulation region, which greatly influences the system
Filtering capacitor stability as well. In addition, the larger the inverter gain K,,,,
Filtering capacitor current gain the larger the system stable region will be and obtain
Load voltage feedback gain better system stability. Finally, the results of simulation
Fundamental inverter gain are included to show the validity of its stability study.
Proportional gain
Voltage transducer gain
11. DVR STRUCTURE
Time constant in PI controller
Fig. 1 shows the one line diagram of a DVR [ 5 ] , which
consists of a single phase rectifier, single phase inverter,
I. INTRODUCTION DC storage capacitor, transformer and a pair of filtering
capacitor and inductor. And the detail of the DVR circuit
A Dynamic voltage restorer (DVR) is a power-electronic- configuration can be referred to Reference [ 5 ] .
converter-based device, designed to protect critical loads
from all supply-side disturbances other than outages. It is
connected in series with a distribution feeder and is
capable of generating or absorbing real and reactive power
at its ac terminals. The basic principle of a DVR is simple:
by inserting a voltage of required magnitude and
frequency, the DVR can restore the load-side voltage to
the desired amplitude and waveform even when the source
voltage is unbalanced or distorted. Usually a DVR is
connected to protect sensitive loads during faults in the
supply system [1I.

In the past years, many authors focused on the DVR

structure, design schemes, power optimization. And most
of them concentrated on the different control methods in Fig. 1: One line diagram of a Dynamic Voltage Restorer

'66
In addition, the DVR makes use of 3 single-phase
inverters to control the voltage insertion to each phase. As
each phase operates independently without affecting the
other two phases, this benefits in the simplicity and
independent control and analysis. Moreover, zero
sequence voltage can be injected into the system. Thus, the - + - ,

control analysis of the series inverter configuration can be Fig. 4: System block diagram model of the DVR
focused on a single-phase H-bridge inverter [5], [6].
Besides, Fig. 2 demonstrates the equivalent circuit model Based on this system block diagram model, the detail of
of a single-phase inverter, while Fig. 3 shows the the system stability will be discussed in the following.
theoretical diagram of the PWM trigger signal based on
regular sampling. With the help of Fig. 2 and Fig. 3, the
equivalent model of the inverter can be established. 111. STABILITY STUDY

Define S* is an ON-OFF function, where In the past, many stability analyses assumed the load
S, S, are closed current as a constant parameter. However, in reality, load
(1) current is not always a constant value. Thus, the load
-I SIS, are closed
effect to the system stability must be considered. With the
If the peak value of the triangular wave =1, then the sine system block diagram model shown in Fig. 4, the system
stability of the DVR can be analyzed as follows.
wave is:
U , =msinw,td (0 < m < I ) (2) A. Conventional Stability Study of DVR
Reference [6] shows the open-loop transfer function Go,
where m and w, is the amplitude and angular frequency between U , and ur according to Fig. 4:
of the reference voltage, td is the average time between K,K,(Z + K,m) (4)
Go, (s) =
two triangle wave peak values.
'
mSfLCs' + K,Cas + I )
By using the average of the existing time of two-state With one zero and three poles:
values in one switching period to substitute S' , named it I
- - s*2 =--
K"r
s* in one switching period is:
S* ,then the average
-
S
1;

= msin q . i d (3) Sop) = 0 > s*pz,3= --dm

2L
*/-
From equation (6), Sop, and Sop, both have negative real
part, which is located in the left s-plane. By changing the
parameter, the locations of Sop, and Sop, will change
respectively,

If dm * ,<' LC
(2L) that is 2 > a ~ ,,the system has a pair

of complex poles.

Fig. 2: Equivalent circuit model of a single-phase inverter

(7)

t'
t .
If (%,2
2L
>i,
negative real roots.
that is
LC
2 5 &, , the system has two

T I!--?
??Ix2
When the root locus gain approaches to infinite, there are
Fig. 3:PWM trigger signal based on regular sampling
also two root locus approaches infmite as well. Moreover,
the slope of two asymptotes (9) is n/2 and 3 d 2 and the
From equation (3), the output voltage of the inverter U,,,,
intersection point between that two asymptotes and real-
equals msin(w,t,j,lsud,. Thus, the inverter can be equivalent
axis is ga,which can be calculated by equation (lo):
as a gain Km=udC,which is linear during analysis. However,
in order to have a good load regulation characteristics, fast
dynamic response and stable output load voltage, the =- ( 2 k + 1 ' r r ( k = ~ . ~ . . . n, - m - 1 ) (9)
n-m
instantaneous output voltage and the filtering capacitor
where n = number of finite poles, m= number of finite
current ijCare feedback to the system [ 5 ] , [6]. Finally, Fig.
zeros.
4 illustrates the DVR system block diagram model.
6%
 1 I

Selecting suitable system parameters can guarantee far

away fiom the jo axis, and maintain a good system
stability margin. From the open-loop transfer function (41,
the closed-loop transfer h c t i o n is:

Table 1. shows a set of designed DVR system parameters,

which can be used to analyze the system typically. ..I .... . L ..... .. . I .........
-8 4
11i3.N..

Table 1: shows a set of designed system parameters Fig. 5: Root locus diagram of the system
System Parameters Values
L 7.6mH
C 1 luF
a 24.4
B 1
KIn 25
Kv 15
KT 0.09565
r 2ms
Switching frequency f,, 1OkHz

Under the system parameters shown in Table 1, the system

.l.*?...Lr_.:__ii"L-. , .. , ,I ., , 1.."
YY--II_LYL*I...II.

has two negative real poles, and the two asymptotes IC' If Id- .IS' IC 1 d $0.

intersect at a common point on the real axis of na = - Y-F crerect

~ rads, which guarantees the root locus far away

4 . 3 4 lo4 Fig.6:Bode diagram o f the closed-loop system
from the jw axis in the s-plane.
B. Unstable Phenomenon of the DVR
According to the closed-loop transfer function (1 I), Fig. 5 However, i, is not always a constant value in reality.
demonstrates the root locus diagram of the system under Therefore, an unconventional stability study will be
the designed parameters mentioned in Table 1. From Fig. introduced in this part. When load is also considered
5 , the zero and the three poles S,,, ScplrScpz,S,, values are inside the system, the system block diagram model shown
-33.3 rad/s, -32.6 rads, -5.38~IO3 rads and -8.14~IO4 in Fig. 4 can be modified into the one shown in Fig. 7.
rads, which the poles Scy2,S,, are far away from the jo
axis. Using q,to express the intersection point between the
asymptotic and real-axis, which is located between the two
poles S,,,. Therefore, if the open-loop gain changes,
the closed-loop poles will change according to
Scp3-wa++m and Scp,poo+-a respectively, but the
position of the pole , S does not vary a lot. As a result, Fig.?: System block diagram with including the load
poles S c p ~S+, can be said as the dominated poles.
Considering the general steady state case of the system
Fig. 5 and Fig. 6 show the bode diagrams of the open-loop
and closed-loop system. From open-loop bode plot, the
block diagram including the load, Z, = R + When the yx.
system is stable due to having a rather large stability load consists of inductive element, x = ( S L ~ ) - I and Z,
margin of Gm=inf dB, Pm=88.0°. And from the closed- -
loop bode plot, the system output voltage can track the
reference voltage and have a good low-pass characteristic
~ + AdL. When the load consists of capacitive
,p

element, X = sCL and Z, = R + 1 . Then the general

at the low frequency band. h L
open-loop and closed-loop transfer function Go, and G,,
According to the block diagram model in Fig. 4, if the load between U ,and U,.is:
current il is assumed to be a constant parameter and the K ~ K , ( I+ K , ~ X +I RX)
DVR system is designed according to those parameters in
G,,(s)=
'
*({I + RX)CLs + /CK,n( 1 + RX ) + LX)s + ( I + RX ,J)
'

Table 1, the DVR system will always be stable. (12)

When the system has no load condition that is R = 0 and
X= 0, the open-loop and closed-loop transfer function is:

which are consistent with (4) and (1 1). As a result, the

system stability study with linear load R, L, C can be
based on the general transfer functions (12) and (13).

According Fig. 7, and the system parameters mentioned in

Table 1, the system stability with each type of linear load
has been analyzed. In which, the R,L load will not lead to
an unstable system. Unfortunately, pure capacitive load Fig. 8a: Pure capacitive load C, = 29.4mF
will yield a stability problem to the system. Thus the
following stability analysis will only be focused on tbe Pu*.alc *lap

pure capacitive load situation.

By ROUTH-HURWITZ criterion, the Routh table can be

obtained as follows:

s3
2 Fig. Xb: Pole-Zero map of pure capacitive load C, = 29.4mF

sI
By ROUTH-HURWITZ criterion, the stable DVR
operation range for pure capacitive load can be found,
which is between O<CL<[Link] though the analysis
so results in part A show the system very stable, it will
become unstable when capacitive load value of
The closed loop system is stable if and only if there are no C~>29.5mFis connected to the system. Therefore, it is
sign changes in the first column of the above table. Thus, significant to apply both the conventional and proposed
the system must fulfill the following four conditions: method in the whole system stability study.

Condition 1: ( C + C ~ ) L ~ > O C. Stable and Unstable Regions

According to Fig. 3 , the sine wave modulated P W M
Condition 2: aCK,t >O
inverter may be represented by the following set of
Condition 3: equations: first a describing function E1I]
aCk,r2 (I + P K , Kj- K,, ) - (C f CL)L$K, K r ,Q

aCK,r
Condition 4: PK,K, >O

According to the system parameters illustrated in Table 1, When the sinusoidal phase voltage command Y'< 2,,
Conditions 2 and 4 are satisfied. And the range of the pure peak of triangle carrier, under-modulation occurs with the
capacitive load can be found by Condition 1 and Condition modulation index M, 5 1, then the fundamental inverter
3, which is O<C~<[Link] this range, the system is gain K, is linear, which gives equation (18)
stable.
G,,,,,(u_)=~= Km
When C, = 29.4mF, the zero and the three poles S,, Srpi,
4
Scpf,,S values are -33.3 rads , -32.4 rads, -0.0251+406i However, when the sinusoidal phase voltage command V'
rad/s and -0,0251-4063 rads, in which the two dominated
poles Iocate close to the jo axis with small stability margin > if, over-modulation occurs with the modulation index
of Gm=0.523dB, Pm=0.0073', shown in Fig. Sa and Fig. Mi >1, then the fundamental inverter gain K, is nonlinear,
8b. Thus the system is marginally stable because it just which gives equation (19)
falls inside the range O< C, c29.5mF. G(Udc Mi ) = Gmmj
I ) x G t Mi j = K m (19)

69
In section 11, the inverter is equivalent as a linear gain, IV. SIMULATION RESULTS ANDDISCUSSION
which simplifies the inverter model for analysis. In order
to guarantee the theoretical capacitive load range When over-modulation occurs in the state of Mi >1, the
O<CL<29.5mFworkable in the designed DVR system, the inverter gain becomes nonlinear. As a result, the DVR
fundamental inverter gain must be linear (18). Fig. 9 system has the possibility to be unstable even inside the
clarifies the general stable and unstable regions study for theoretical stable range 0<CL<29.5mF. This unstable
capacitive load values with different inverter gain. phenomenon may cause large amount money lost due to
the abnormal operation of very sensitive loads and high
precision productive machines. In more serious situation,
it may burn the sensitive loads which are originally
,I protected by the DVR. As a result, it is essential and
important to study the stability relationship between over-
modulation and inverter gain besides the load effect.

As the capacitive load value keeps at a constant value of

20mF, the fundamental inverter gain changes to 5, 17.5
and 25 respectively. Fig. lla, Fig. l l b and Fig. l l c
illustrates the simulation results of three different cases.

Based on the nonlinear inverter gain equation (19), Fig. 10

shows that the fundamental inverter gain K, varies with
the modulation index Mi.

om 010 om om 0O
. ora

Fig. I la: Unstable output voltage at CL=20mF,K , = 5

10' 70' 10' 10' 10'

Fig. 10: Fundamental inverter gain K , vanes with the modulation

index M ,

From Fig. IO, when the modulation index appears to be Mi

5 1 (under-modulation), the inverter gain is linear and om 0 10 om on 0 40 llyl

keeps at a constant value. Then the support stable Fig 1 I b Marginally Stable output voltage at CL=20mF,K , =
capacitive load range will be 0<CL<29.5mFillustrated by 17 5
Fig. 9, which matches with the theoretical results in
section 111. But when the modulation index continues to
increase from unity (over-modulation), the inverter gain
will decrease exponentially, shown in Fig. 10. This results
in a great reduction of stable capacitive load range, which
can also be illustrated clearly in Fig. 9.

In addition, when over-modulation occurs, the inverter

gain becomes nonlinear. Then the system block diagram
model of Fig. 4 and Fig. 7 cannot be used to describe the
practical DVR system anymore. Moreover, they are no
more suitable for the system stability analysis. For the
design of the DVR, the effect of the inverter gain in both nm4. :. ....v ...._I..I :..........
.W
.J.. ....... ..i .... i ........... J........................
I
I

am 1
under-modulation and over-modulation to the system om 070 om om 0 10 0%

stability should be considered carefully. Fig. 1 IC: Stable output voltage at CL=20mF,K,,, 25
 When the inverter gain K,,, =5, the system is unstable as VI. ACKNOWLEDGMENT
the output load voltage oscillates to a simultaneously
larger magnitude, shown in Fig. 1la. However, when the The authors would like to thank for the financial support
inverter gain Km increases to 17.5, the system is of Research Committee of University of Macau and the
marginally stable because the output load voltage technical assistance and support of Tsinghua University.
oscillates without getting to a larger value, shown in Fig.
1Ib. Finally, when the inverter gain K,,, increases to 25, the
system is stable as the output load voltage reaches to a VII. REFERENCES
steady state after 0.3s, which is shown in Fig. 1IC. During
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about the load effect io the whole system. Even though the @U&.,
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