SmartMX2 P40 family

P40C012/040/072
Secure smart card controller
Rev. 3.0 — 24 April 2015 Product short data sheet
262830 COMPANY PUBLIC

1. Introduction

1.1 Product overview

SmartMX2-P40 family is a secure microcontroller family designed and manufactured by
NXP Semiconductors. It is part of the SmartMX2-IC family produced in 90 nm CMOS
technology. SmartMX2-P40 is an ISO/IEC 7816 compliant contact secure microcontroller
platform, built around the proven and powerful MRK3-SC RISC core. The overall
architecture of P40 has been streamlined to meet the performance requirements of
payment and eGovernment contact smart card applications.

NXP‘s SmartMX2 P40 security architecture is built on more than 15 years of experience in
this area. The SmartMX2-P40 product family provides embedded firmware forming a
Hardware Abstraction Layer (HAL). The use of this HAL makes it easier to efficiently
develop embedded software for the device.

SmartMX2-P40 supports DES, AES, ECC, RSA cryptography, hash computation, and
random-number generation. For asymmetric RSA and ECC cryptography, a dedicated
coprocessor supports RSA key lengths up to 4096 bits and ECC key lengths up to
521 bits. Coprocessors for symmetric ciphers support DES (single DES, 2-key 3DES, and
3-key 3DES), plus AES cryptography with bit lengths of 128-bit, 192-bit, or 256-bit. The
memory configuration, which combines up to 265 KB User ROM, 6 KB RAM, up to 72 KB
EEPROM, handles static code and dynamic data separately, and enables fast code
execution from ROM.

The P40 family also provides a ready-to-use crypto library with highly efficient software
APIs for all cryptographic functions (RSA key length up to 2048 bits, ECC up to 384 bits).

Table 1. Feature table

Product EEPROM User Total RAM allocation Coprocessor ISO/IEC 7816 Interface
type [KB] ROM RAM [B] CPU/PKCC PKC DES AES IO pads option
[KB][1]
P40C012 13 up to 265 6144 dynamic yes yes yes 1 ISO 7816
P40C040 40 up to 265 6144 dynamic yes yes yes 1
P40C072 72 up to 265 6144 dynamic yes yes yes 1

[1] Refer to Section 14.3

NXP Semiconductors P40C012/040/072
Secure smart card controller

2. General description

2.1 General remarks

This document offers an introduction into the features and the architecture of the
SmartMX2 P40 products.

The product data sheet and other detailed documentation, e.g. for Card Operating System
(COS) development are available through NXP’s portal for secured documentation.
Access to such documents is granted on a need-to-know basis. Contact NXP sales for
registration and access.

2.2 Naming conventions

Table 2. Naming conventions
P40xeee
x Interface and feature configuration identifier, as currently defined, e.g.:
x = C: Asymmetric and symmetric cryptography implemented, ISO/IEC 7816
contact interface
eee Indication of the Non-Volatile memory size in KB
eee = 012: 13 KB EEPROM implemented
eee = 040: 40 KB EEPROM implemented
eee = 072: 72 KB EEPROM implemented

2.3 Contact interfaces

Operating in accordance with ISO/IEC 7816, the SmartMX2 P40 contact interface is
supported by a built-in Universal Asynchronous Receiver/Transmitter (UART). P40 UART
enables data rates of up to 688 kbit/s allowing for the automatic generation of all typical
baud rates and supports transmission protocols T=0 and T=1.

2.4 Public Key Crypto (PKC) coprocessor

The PKCC is speeding up the computation of public-key cryptographic operations within
the P40C012/040/072.

The PKC coprocessor flexible interface provides programmers with the freedom to
implement their own cryptographic algorithms. A Common Criteria certified crypto library
from NXP providing a large range of required functions is available for all devices listed in
Table 4 in order to support customers in implementing public key-based solutions.

2.5 Coprocessor for DES and AES

The DES algorithm, widely used for symmetric encryption, is supported by a dedicated,
high performance, highly attack-resistant hardware coprocessor. Relevant standards
(ISO/IEC, ANSI, FIPS) are fully supported. A secure crypto library element for DES is
available.

The same coprocessor supports secure AES as well. The implementation is based on
FIPS197 as standardized by the National Institute for Standards and Technology (NIST),
for key lengths of 128-bit, 192-bit, and 256-bit with performance levels comparable to

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DES. AES is the next generation for symmetric data encryption and recommended
successor to DES providing significantly improved security level. A secure crypto library
element for AES is available.

2.6 Security features

Advanced 0.09 μm CMOS technology, with seven metal layers, provides enhanced
protection against reverse engineering and probing attacks, and produces a highly
protective mesh of active and dynamic multi-threaded shielding.

SmartMX2 P40 incorporates a wide range of both inherent and OS-controlled security
features as a countermeasure against all types of attacks. NXP Semiconductors apply
their extensive knowledge of chip security, very dense CMOS technology and active
shielding methodology.

As attacks evolve over time, the multi-dimensional approach of the SmartMX2 P40
security architecture allows for more proactive and continuous enhancements of the
security mechanisms compared to alternative and less versatile approaches. This makes
SmartMX2 P40 a future-proof secure micro-controller platform neutralizing all side
channel and fault attacks as well as reverse engineering efforts.

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3. Features and benefits

3.1 Standard P40C012/040/072 features

 EEPROM: 13, 40 or 72 KB
 ROM: up to 265 KB
 RAM: 6144 B split into area usable for CPU and PKC coprocessor.
 Dedicated, RISC based Smart Card CPU
 PKC coprocessor
 Boolean operations for acceleration of major Public Key Cryptography (PKC)
systems such as RSA and ECC
 32-bit operand input/output interface
 High speed DES/AES coprocessor
 ISO/IEC 7816 contact interface with UART supporting standard protocols T=0 and T=1
as well as high speed personalization up to 688 kbit/s
 High speed 8-, 16- or 32-bit CRC engine according to ITU-T polynomial definition
 Low power Random Number Generator (RNG) in hardware, AIS-31 compliant once
NXP Crypto Library functions are used
 2.7 V to 5.5 V extended operating voltage range for class B and A (depending on
product)
 -25 °C to +85 °C ambient temperature

3.2 Security features

 Security sensors
 Low and high clock frequency sensor
 Low and high temperature sensor
 Low and high supply voltage sensor
 Single Fault Injection (SFI) attack detection
 Light sensors (incl. integrated memory light sensor functionality)
 Active shielding
 10 bytes Unique ID for each die
 Clock input filter for protection against spikes
 Optional programmable card disable feature
 Memory security (encryption and physical measures) for RAM, NV memory and ROM

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4. Applications
 Banking
 Multi-application cards
 ID cards
 Health cards
 Electronic driving licences
 Digital Signature
 High-security access management
 Other secure micro controller applications

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5. Quick reference data

Table 3. Limiting values
Voltages are referenced to VSS (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage -0.5 +5.8 V
VI input voltage any signal pad -0.5 +5.8 V
Vesd electrostatic discharge voltage pads VDD, VSS, CLK, [1] ± 4.0 kV
(HBM) RST_N, IO1
electrostatic discharge voltage all pads [2] ± 1000 V
(CDM)
Ptot Total power dissipation [3] - 600 mW
Tamb Operating ambient temperature [4] -25 +85 C

[1] In accordance with ANSI/ESDA/JEDEC JS-001-2011, ESDA/JEDEC Joint Standard for Electrostatic
Discharge Sensitivity Testing - Human Body Model (HBM) - Component Level.
[2] In accordance with JEDEC JESD22-C101 for Charged-Device Model (CDM).
[3] Depending on appropriate thermal resistance of the package.
[4] All product properties and values specified within this data sheet are only valid within the operating ambient
temperature range.

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6. Ordering information
Table 4. Ordering information
Type number Package
Name Description Version
P40C012U15 FFC 12 inch wafer (sawn, 150 μm thickness, on film frame NAU000
P40C040U15 carrier; electronic fail die marking according to SECSII
format)
P40C072U15
P40C012U75 FFC 12 inch wafer (sawn, 75 μm thickness, on film frame NAU000
P40C040U75 carrier; electronic fail die marking according to SECSII
format)
P40C072U75
P40C012X84 PCM1.5 contact chip card module (super 35 mm tape format, SOT658
P40C040X84 8-contact); multi-source

P40C072X84
P40C012X85 Pd-PCM1.5 palladium plated contact chip card module (super SOT658
P40C040X85 35 mm tape format, 8-contact); multi-source

P40C072X85
P40C012X60 PCM3.1 contact chip card module (super 35 mm tape format, SOT658
P40C040X60 8-contact)

P40C072X60
P40C012X61 Pd-PCM3.1 palladium plated contact chip card module (super SOT658
P40C040X61 35 mm tape format, 8-contact)

P40C072X61

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Product short data sheet
P40C040_C072_SMX2_FAM_SDS

NXP Semiconductors
7. Functional diagram

P40C012/040/072

ROM EEPROM RAM

PROGRAMMABLE UART
IO1
I/O 1 ISO 7816

up to 265 KB(1) 13 KB/ 40 KB/ 72 KB 6144 B

PROGRAM MEMORY DATA AND PROGRAM DATA MEMORY
MEMORY

POR OSCILLATOR
All information provided in this document is subject to legal disclaimers.

MEMORY MANAGEMENT UNIT (MMU)

Rev. 3.0 — 24 April 2015
262830

SECURE SmartMX2 P40 CPU

CLOCK CLOCK
CLK
FILTER GENERATION

P40C012/040/072
COPROCESSORS
SECURITY SENSORS
RST_N
RESET GENERATION PKC (PUBLIC
CRC
WATCHDOG AES KEY CRYPTO)

Secure smart card controller

8-bit/16-bit TRNG DES
TIMER 128-bit/192-bit COPROCESSOR
or 32-bit
or 256-bit e.g. RSA, ECC
© NXP Semiconductors N.V. 2015. All rights reserved.

VOLTAGE REGULATOR

VDD VSS aaa-008728

Remark: The diagram provides a generic overview of the architecture of the SmartMX2 P40 product family. Functional blocks, pins and connections shown in this diagram
are optional and represent a super-set of those elements actually implemented in a real product.
(1) see Section 14.3 “ROM size and communication library”
8 of 15

Fig 1. Functional diagram P40C012/040/072

NXP Semiconductors P40C012/040/072
Secure smart card controller

8. Revision history
Table 5. Revision history
Document ID Release date Data sheet status Change notice Supersedes
P40C040_C072_SMX 20150424 Product short data sheet - P40C040_C072_SMX2_
2_FAM_SDS v3.0 FAM_SDS v2.1
Modifications: • updated to “product” status
• global update: standardised graphics (formal check only, no content change)
P40C040_C072_SMX 20141010 Preliminary short data sheet - P40C040_C072_SMX2_
2_FAM_SDS v2.1 FAM_SDS v2.0
P40C040_C072_SMX 20140923 Preliminary short data sheet - P40C040_C072_SMX2_
2_FAM_SDS v2.0 FAM_SDS v1.4
P40C040_C072_SMX 20131217 Objective short data sheet - P40C040_C072_SMX2_
2_FAM_SDS v1.4 FAM_SDS v1.3
P40C040_C072_SMX 20131105 Objective short data sheet - P40C040_C072_SMX2_
2_FAM_SDS v1.3 FAM_SDS v1.2
P40C040_C072_SMX 20131011 Objective short data sheet -
2_FAM_SDS v1.2

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9. Legal information

9.1 Data sheet status

Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL [Link]

9.2 Definitions Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Draft — The document is a draft version only. The content is still under
malfunction of an NXP Semiconductors product can reasonably be expected
internal review and subject to formal approval, which may result in
to result in personal injury, death or severe property or environmental
modifications or additions. NXP Semiconductors does not give any
damage. NXP Semiconductors and its suppliers accept no liability for
representations or warranties as to the accuracy or completeness of
inclusion and/or use of NXP Semiconductors products in such equipment or
information included herein and shall have no liability for the consequences of
applications and therefore such inclusion and/or use is at the customer’s own
use of such information.
risk.
Short data sheet — A short data sheet is an extract from a full data sheet
Applications — Applications that are described herein for any of these
with the same product type number(s) and title. A short data sheet is intended
products are for illustrative purposes only. NXP Semiconductors makes no
for quick reference only and should not be relied upon to contain detailed and
representation or warranty that such applications will be suitable for the
full information. For detailed and full information see the relevant full data
specified use without further testing or modification.
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the Customers are responsible for the design and operation of their applications
full data sheet shall prevail. and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
Product specification — The information and data provided in a Product design. It is customer’s sole responsibility to determine whether the NXP
data sheet shall define the specification of the product as agreed between Semiconductors product is suitable and fit for the customer’s applications and
NXP Semiconductors and its customer, unless NXP Semiconductors and products planned, as well as for the planned application and use of
customer have explicitly agreed otherwise in writing. In no event however, customer’s third party customer(s). Customers should provide appropriate
shall an agreement be valid in which the NXP Semiconductors product is design and operating safeguards to minimize the risks associated with their
deemed to offer functions and qualities beyond those described in the applications and products.
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
9.3 Disclaimers customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Limited warranty and liability — Information in this document is believed to
Semiconductors products in order to avoid a default of the applications and
be accurate and reliable. However, NXP Semiconductors does not give any
the products or of the application or use by customer’s third party
representations or warranties, expressed or implied, as to the accuracy or
customer(s). NXP does not accept any liability in this respect.
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no Limiting values — Stress above one or more limiting values (as defined in
responsibility for the content in this document if provided by an information the Absolute Maximum Ratings System of IEC 60134) will cause permanent
source outside of NXP Semiconductors. damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
In no event shall NXP Semiconductors be liable for any indirect, incidental,
the Recommended operating conditions section (if present) or the
punitive, special or consequential damages (including - without limitation - lost
Characteristics sections of this document is not warranted. Constant or
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repeated exposure to limiting values will permanently and irreversibly affect
replacement of any products or rework charges) whether or not such
the quality and reliability of the device.
damages are based on tort (including negligence), warranty, breach of
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Notwithstanding any damages that customer might incur for any reason products are sold subject to the general terms and conditions of commercial
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards sale, as published at [Link] unless otherwise
customer for the products described herein shall be limited in accordance agreed in a valid written individual agreement. In case an individual
with the Terms and conditions of commercial sale of NXP Semiconductors. agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
Right to make changes — NXP Semiconductors reserves the right to make applying the customer’s general terms and conditions with regard to the
changes to information published in this document, including without purchase of NXP Semiconductors products by customer.
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior No offer to sell or license — Nothing in this document may be interpreted or
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Export controlled classification (1) — The content of this document is

subject to export controls. Export or supply to listed parties requires a prior
9.4 Licenses
authorization from the competent authorities. The Export Control
Classification Number (ECCN) is 5E002. ICs with DPA Countermeasures functionality
Quick reference data — The Quick reference data is an extract of the NXP ICs containing functionality
product data given in the Limiting values and Characteristics sections of this implementing countermeasures to
document, and as such is not complete, exhaustive or legally binding. Differential Power Analysis and Simple
Power Analysis are produced and sold
Non-automotive qualified products — Unless this data sheet expressly
under applicable license from
states that this specific NXP Semiconductors product is automotive qualified,
Cryptography Research, Inc.
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for 9.5 Trademarks
reference only. The English version shall prevail in case of any discrepancy
Notice: All referenced brands, product names, service names and trademarks
between the translated and English versions.
are the property of their respective owners.
FabKey — is a trademark of NXP Semiconductors N.V.
SmartMX — is a trademark of NXP Semiconductors N.V.

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10. Contact information

For more information, please visit: [Link]
For sales office addresses, please send an email to: salesaddresses@[Link]

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11. Tables
Table 1. Feature table. . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table 2. Naming conventions . . . . . . . . . . . . . . . . . . . . . .2
Table 3. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 4. Ordering information . . . . . . . . . . . . . . . . . . . . .7
Table 5. Revision history . . . . . . . . . . . . . . . . . . . . . . . . .9

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12. Figures
Fig 1. Functional diagram P40C012/040/072 . . . . . . . . .8

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13. Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Product overview . . . . . . . . . . . . . . . . . . . . . . . 1
2 General description . . . . . . . . . . . . . . . . . . . . . . 2
2.1 General remarks . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2 Naming conventions . . . . . . . . . . . . . . . . . . . . . 2
2.3 Contact interfaces. . . . . . . . . . . . . . . . . . . . . . . 2
2.4 Public Key Crypto (PKC) coprocessor . . . . . . . 2
2.5 Coprocessor for DES and AES . . . . . . . . . . . . 2
2.6 Security features. . . . . . . . . . . . . . . . . . . . . . . . 3
3 Features and benefits . . . . . . . . . . . . . . . . . . . . 4
3.1 Standard P40C012/040/072 features . . . . . . . . 4
3.2 Security features. . . . . . . . . . . . . . . . . . . . . . . . 4
4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5 Quick reference data . . . . . . . . . . . . . . . . . . . . . 6
6 Ordering information . . . . . . . . . . . . . . . . . . . . . 7
7 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 8
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 9
9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10
9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10
9.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
9.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
9.4 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9.5 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
10 Contact information. . . . . . . . . . . . . . . . . . . . . 12
11 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
12 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

© NXP Semiconductors N.V. 2015. All rights reserved.

For more information, please visit: [Link]
For sales office addresses, please send an email to: salesaddresses@[Link]
Date of release: 24 April 2015
Document identifier: 262830