ULN2803C

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ULN2803C 达林顿晶体管阵列

1 特性 3 说明
• 500mA 额定集电极电流 ULN2803C 器件是一款 50V、500mA 达林顿晶体管阵
（单输出） 列。该器件由八个 NPN 达林顿对组成，这些达林顿对
• 高电压输出：50V 具有高压输出，带有用于开关电感负载的共阴极钳位二
• 钳位二极管输出 极管。每个达林顿对的集电极电流额定值为 500mA。
• 可兼容各类逻辑的输入 将达林顿对并联可以提供更高的电流。
2 应用 应用包括继电器驱动器、电锤驱动器、灯驱动器、显示
驱动器（LED 和气体放电）、线路驱动器和逻辑缓冲
• 工厂自动化和控制
器 。 ULN2803C 器 件 的 每 个 达 林 顿 对 都 具 有 一 个
• 楼宇自动化
• 电器 2.7kΩ 的串联基极电阻，可直接与 TTL 或 5V CMOS
• IP 网络摄像头 器件配合使用。
• HVAC 阀门和执行器控制 封装信息(1)
• 继电器、螺线管和灯驱动 器件型号 封装 封装尺寸（标称值）
• 步进电机驱动 ULN2803CDW DW（SOIC、20） 12.80mm × 7.50mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
[Link]，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLRS076
ULN2803C
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Table of Contents
1 特性................................................................................... 1 8.2 Functional Block Diagram......................................... 10
2 应用................................................................................... 1 8.3 Feature Description...................................................10
3 说明................................................................................... 1 8.4 Device Functional Modes..........................................10
4 Revision History.............................................................. 2 9 Application and Implementation.................................. 11
5 Pin Configuration and Functions...................................3 9.1 Application Information..............................................11
6 Specifications.................................................................. 4 9.2 Typical Application.................................................... 11
6.1 绝对最大额定值...........................................................4 9.3 Power Supply Recommendations.............................13
6.2 ESD Ratings............................................................... 4 9.4 Layout....................................................................... 13
6.3 Recommended Operating Conditions.........................4 10 Device and Documentation Support..........................15
6.4 Thermal Information....................................................4 10.1 接收文档更新通知................................................... 15
6.5 Electrical Characteristics.............................................5 10.2 支持资源..................................................................15
6.6 Switching Characteristics............................................5 10.3 Trademarks............................................................. 15
6.7 Typical Characteristics................................................ 6 10.4 Electrostatic Discharge Caution..............................15
7 Parameter Measurement Information............................ 7 10.5 术语表..................................................................... 15
8 Detailed Description......................................................10 11 Mechanical, Packaging, and Orderable
8.1 Overview................................................................... 10 Information.................................................................... 15

4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE REVISION NOTES
August 2022 * Initial release.

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5 Pin Configuration and Functions

图 5-1. DW Package 20-Pin SOIC Top View

表 5-1. Pin Functions

PIN
TYPE DESCRIPTION
NAME NO.
1B 1
2B 2
3B 3
4B 4
I Channel 1 through 8 Darlington base input
5B 5
6B 6
7B 7
8B 8
1C 20
2C 19
3C 18
4C 17
O Channel 1 through 8 Darlington collector output
5C 16
6C 15
7C 14
8C 13
GND 9 — Common emitter shared by all channels (typically tied to ground)
COM 12 I/O Common cathode node for flyback diodes (required for inductive loads)
NC 10, 11 — No connect pin

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6 Specifications
6.1 绝对最大额定值
在 25°C 的自然通风温度下（除非另有说明）(1)
最小值 最大值 单位
VCE 集电极 - 发射极的电压 50 V
VI 输入电压(2) 30 V
集电极峰值电流 500 mA
I(clamp) 输出钳位电流 500 mA
基板端子总电流 -2.5 A
TJ 结温 -65 150 °C
Tstg 贮存温度 –65 150 °C

(1) 超出绝对最大额定值运行可能会对器件造成永久损坏。绝对最大额定值并不表示器件在这些条件下或在建议运行条件以外的任何其他条
件下能够正常运行。如果超出建议运行条件但在绝对最大额定值范围内使用，器件可能不会完全正常运行，这可能影响器件的可靠性、
功能和性能并缩短器件寿命。
(2) 除非特别说明，否则所有电压值都以发射极/基板端子 GND 为基准。

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge V
Charged device model (CDM), per ANSI/ESDA/ JEDEC JS-002(2) ±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCE Collector-emitter voltage 0 50 V
TA Ambient temperature –40 85 °C

6.4 Thermal Information

ULN2803C
THERMAL METRIC(1) DW (SOIC) UNIT
20 PINS
RθJA Junction-to-ambient thermal resistance 68.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 34.3 °C/W
RθJB Junction-to-board thermal resistance 37.5 °C/W
ψJT Junction-to-top characterization parameter 10.7 °C/W
ψJB Junction-to-board characterization parameter 37.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.5 Electrical Characteristics

at TA = 25°C free-air temperature (unless otherwise noted)
ULN2803C
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX
VCE = 50 V,
ICEX Collector cutoff current II = 0 50 μA
see 图 7-1
VCE = 50 V, IC = 500 μA,
II(off) Off-state input current 50 65 μA
TA = 70°C see 图 7-2
II(on) Input current VI = 3.85 V, See 图 7-3 0.93 1.35 mA
IC = 200 mA 2.4
VCE = 2 V,
VI(on) On-state input voltage IC = 250 mA 2.7 V
see 图 7-4
IC = 300 mA 3
II = 250 μA,
IC = 100 mA 0.9 1.1
see 图 7-5
II = 350 μA,
VCE(sat) Collector-emitter saturation voltage IC = 200 mA 1 1.3 V
see 图 7-5
II = 500 μA,
IC = 350 mA 1.3 1.6
see 图 7-5
IR Clamp diode reverse current VR = 50 V, see 图 7-6 50 μA
VF Clamp diode forward voltage IF = 350 mA see 图 7-7 1.7 2 V
Ci Input capacitance VI = 0, f = 1 MHz 15 25 pF

6.6 Switching Characteristics

TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low- to high-level output VS = 50 V, CL = 15 pF, RL = 163 Ω, 130
ns
tPHL Propagation delay time, high- to low-level output See 图 7-8 20
VOH High-level output voltage after switching VS = 50 V, IO = 300 mA, see 图 7-9 VS – 20 mV

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6.7 Typical Characteristics

μ μ

μ
μ

图 6-1. Collector-Emitter Saturation Voltage vs 图 6-2. Collector-Emitter Saturation Voltage vs

Collector Current (One Darlington) Total Collector Current (Two Darlingtons in
Parallel)

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7 Parameter Measurement Information

Open VCE Open VCE

IC
ICEX II(off)
Open

图 7-1. ICEX Test Circuit

图 7-2. II(off) Test Circuit
Open Open

II IC
VI Open VI

VCE

图 7-3. II(on) Test Circuit

图 7-4. VI(on) Test Circuit
Open VR
IC
hFE = IR
II
II IC

Open
VCE

图 7-6. IR Test Circuit

图 7-5. hFE, VCE(sat) Test Circuit

IF
VF

Open

图 7-7. VF Test Circuit

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Input Open VS = 50 V

RL = 163 Ω
Pulse
Generator Output
(see Note A)

CL = 15 pF
(see Note B)

Test Circuit

<5 ns <10 ns
VIH
Input 90% 90% (see Note C)
50% 50%
10% 10% 0
0.5 µs

tPHL tPLH
VOH
50% 50%
Output

Voltage Waveforms
A. The pulse generator has the following characteristics: PRR = 12.5 kHz, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
C. VIH = 3 V.

图 7-8. Propagation Delay Times

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VS

Input
2 mH

163 Ω
Pulse
Generator Output
(see Note A)

CL = 15 pF
(see Note B)

Test Circuit

<5 ns <10 ns
VIH
Input 90% 90% (see Note C)
1.5 V 1.5 V
10% 10% 0
40 µs

VOH
Output

Voltage Waveforms
A. The pulse generator has the following characteristics: PRR = 12.5 kHz, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
C. VIH = 3 V.

图 7-9. Latch-Up Test

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8 Detailed Description
8.1 Overview
This standard device has proven ubiquity and versatility across a wide range of applications. This feature is due
to its integration of eight Darlington transistors that are capable of sinking up to 500 mA and wide GPIO range
capability.
The ULN2803C is comprised of eight high voltage, high current NPN Darlington transistor pairs. All units feature
a common emitter and open collector outputs. To maximize their effectiveness, these units contain suppression
diodes for inductive loads. The ULN2803C has a series base resistor to each Darlington pair, thus allowing
operation directly with TTL or CMOS operating at supply voltages of 5 V or 3.3 V. The ULN2803C offers
solutions to a great many interface needs, including solenoids, relays, lamps, small motors, and LEDs.
Applications requiring sink currents beyond the capability of a single output can be accommodated by paralleling
the outputs.
8.2 Functional Block Diagram
COM

2.7 kΩ Output C
Input B

7.2 kΩ 3 kΩ
E

8.3 Feature Description

Each channel of ULN2803C consists of Darlington connected NPN transistors. This connection creates the
effect of a single transistor with a very-high current gain. The very high β allows for high output current drive
with a very-low input current, essentially equating to operation with low GPIO voltages.
The GPIO voltage is converted to base current through the 2.7-kΩ resistor connected between the input and
base of the predriver Darlington NPN.
The diodes connected between the output and COM pin are used to suppress the kickback voltage from an
inductive load that is excited when the NPN drivers are turned off (stop sinking) and the stored energy in the
coils causes a reverse current to flow into the coil supply through the kickback diode.
In normal operation, the diodes on base and collector pins to emitter are reverse biased. If these diodes are
forward biased, internal parasitic NPN transistors draw (a nearly equal) current from other (nearby) device pins.
8.4 Device Functional Modes
8.4.1 Inductive Load Drive
When the COM pin is tied to the coil supply voltage, ULN2803C can drive inductive loads and suppress the
kickback voltage through the internal free wheeling diodes.
8.4.2 Resistive Load Drive
When driving resistive loads, COM can be left unconnected or connected to the load voltage supply. If multiple
supplies are used, connect to the highest voltage supply.

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9 Application and Implementation

备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

ULN2803C is typically used to drive a high-voltage or current peripherals from an MCU or logic device that
cannot tolerate these conditions. The following design is a common application of ULN2803C, driving inductive
loads. This includes motors, solenoids, and relays. Each load type can be modeled by what is seen in 图 9-1.
9.2 Typical Application

图 9-1. ULN2803C as Inductive Load Driver

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9.2.1 Design Requirements

For this design example, use the parameters listed in 表 9-1 as the input parameters.
表 9-1. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
GPIO voltage 3.3 or 5 V
Coil supply voltage 12 to 50 V
Number of channels 8
Output current (RCOIL) 20 to 300 mA per channel
Duty cycle 100%

9.2.2 Detailed Design Procedure

When using ULN2803C in a coil driving application, determine the following:
• Input voltage range
• Temperature range
• Output and drive current
• Power dissipation
[Link] Drive Current
The coil current is determined by the coil voltage (VSUP), coil resistance, and output low voltage (VOL or
VCE(SAT)).

ICOIL = (VSUP – VCE(SAT)) / RCOIL (1)

[Link] Output Low Voltage

The output low voltage (VOL) is the same thing as VCE(SAT) and can be determined by 图 6-1, 图 6-2, or Electrical
Characteristics.
[Link] Power Dissipation and Temperature
The number of coils driven is dependent on the coil current and on-chip power dissipation. To determine the
number of coils possible, use 方程式 2 to calculate ULN2803C on-chip power dissipation PD.

N
PD = å VOLi ´ ILi
i=1 (2)

where
• N is the number of channels active together.
• VOLi is the OUTi pin voltage for the load current ILi. This is the same as VCE(SAT).
To ensure the reliability of ULN2803C and the system, the on-chip power dissipation must be lower that or equal
to the maximum allowable power dissipation (PD) dictated by 方程式 3.

TJ MAX TA
PD MAX
TJA (3)

where
• TJ(MAX) is the target maximum junction temperature.
• TA is the operating ambient temperature.
• θJA is the package junction to ambient thermal resistance.

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TI recommends to limit the ULN2803C IC die junction temperature to < 125°C. The IC junction temperature is
directly proportional to the on-chip power dissipation.
9.2.3 Application Curves
The following curves are generated with ULN2803C driving an OMRON G5NB relay – Vin = 5.0 V; Vsup= 12 V
and RCOIL= 2.8 kΩ.

13 14
12
11 12
10
9 10
Output voltage - V

Output voltage - V
8
8
7
6
6
5
4 4
3
2 2
1
0 0
-0.004 0 0.004 0.008 0.012 0.016 -0.004 0 0.004 0.008 0.012 0.016
Time (s) D001
Time (s) D001

图 9-2. Output Response with Activation of Coil 图 9-3. Output Response with De-activation of Coil
(Turn-On) (Turn Off)

9.3 Power Supply Recommendations

This devicedoes not need a power supply; however, the COM pin is typically tied to the system power supply.
With this case, make sure that the output voltage does not heavily exceed the COM pin voltage. This action can
heavily forward bias the flyback diodes and cause a large current to flow into COM, potentially damaging the on-
chip metal or overheating the part.
9.4 Layout
9.4.1 Layout Guidelines
Thin traces can be used on the input due to the low current logic that is typically used to drive ULN2803C. Take
care to separate the input channels as much as possible, as to eliminate crosstalk. TI recommends thick traces
for the output to drive high currents as desired. Wire thickness can be determined by the trace material current
density and desired drive current.
Because all of the channels currents return to a common emitter, size that trace width to be very wide. Some
applications require up to 2.5 A.

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9.4.2 Layout Example

图 9-4. ULN2803C Layout Example

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10 Device and Documentation Support

10.1 接收文档更新通知
要接收文档更新通知，请导航至 [Link] 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

10.5 术语表
TI 术语表 本术语表列出并解释了术语、首字母缩略词和定义。

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

[Link] 17-Feb-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

ULN2803CDWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ULN2803C Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OUTLINE
DW0020A SCALE 1.200
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
18X 1.27
20
1

13.0 2X
12.6 11.43
NOTE 3

10
11
0.51
20X
7.6 0.31 2.65 MAX
B 0.25 C A B
7.4
NOTE 4

0.33
TYP
0.10

0.25
SEE DETAIL A GAGE PLANE

1.27 0.3
0 -8 0.40 0.1

DETAIL A
TYPICAL

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

[Link]
 EXAMPLE BOARD LAYOUT
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2) SYMM

1
20

20X (0.6)

18X (1.27)

SYMM

(R0.05)
TYP

10 11

(9.3)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220724/A 05/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2)
SYMM
1
20

20X (0.6)

18X (1.27)

SYMM

10 11

(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

[Link]
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