POST SILICON VALIDATION FOR I2C (SMBUS) PERIPHERAL

[Link] Shilaskar, Ketki Sonawane, [Link] Bhatlawande, Anup Behare

Vishwakarma Institute of Technology, Seagate Technology

PROBLEM METHOD / PIPELINE / ALGORITHM / PROCESS

Before a product is released into the market, • Making a test plan is the first step.
it needs to adhere to its expected • Aim in building firmware for test cases- Segregate code into functions to
behavior/functionality, protocol requirement- exploit reusability and make the code modular. This also ensures that
this effort in VLSI design flow is known as Post other stakeholders beyond developers can comprehend the code
Silicon Validation. Relevant with the growth in • Debugging the firmware in use to make it free of logical errors or writing
logic and design complexity in the code patches that help us isolate and root cause issues in both firmware
semiconductor industry. and hardware. Interrupt Service Routines and their exit condition are
Aim was to validate an I2C (SMBUS) peripheral critical points prone to error in test execution and must be logically tested
It focuses on confirming electrical components to pass errorless in all possible cases of execution.
of the design or finding manufacturing errors
along with functional system validation.

RELATED WORK / MOTIVATION

Post Silicon Validation consumes nearly half of a SoC's
entire design cost at 65nm technology. Cost rises as .
the size decreases, making it critical. RESULTS
Functional errors may be seen across chips. For
manufacturing defects, every of the chips must be A close to absolute (~ 100%) test coverage has been aimed and accomplished
individually examined. and the device’s behavior has been well within its expectations, deeming it fit
for our application. Some of the commonly occurring interesting challenges
Innovation called IFRA, which stands for Instruction
included:
Footprint Recording and Analysis where instruction
flow information is recorded and their impact through • Building test cases
various microarchitectural blocks of the processor is • Generating scenarios prone to failure or corner cases
used to identify, evaluate a defect. • Having an interface with the SOC to generate them.
Around 80 cases falling under I2C protocol compliance and hardware registers’
Design approaches like the Field-Repairable Control validation broadly can be classified as related to:
Logic (FRCL) can help fix issues.

Challenges in Post Silicon Validation include

controllability and observability limitations, error
sequentiality, debugging in the presence of noise and
Status registers Status registers
security. and interrupts and interrupts
pertaining to pertaining to
basic read- SMBUS
YOUR APPROACH / SOLUTION writes. commands
For calculating coverage metrics- register coverage and
transactional coverage.
ARP status flags and
interrupts (as
elaborated in the
Timeouts and previous sections)
Loopbacking have been validated
for the device with
right logic design and
programming flow.

REFERENCES
[1] Mitra, Subhasish, Sanjit A. Seshia, and Nicola Nicolici. "Post-silicon validation opportunities, challenges and
recent advances." In Design Automation Conference, pp. 12-17. IEEE, 2010.
[2] Karimibiuki, Mehdi, Kyle Balston, Alan J. Hu, and Andre Ivanov. "Post-silicon code coverage evaluation with
reduced area overhead for functional verification of SoC." In 2011 IEEE International High Level Design Validation and
For generating multiple test scenarios, scripts were developed and run on the
Test Workshop, pp. 92-97. IEEE, 2011.
[3] Abramovici, Miron, Paul Bradley, Kumar Dwarakanath, Peter Levin, Gerard Memmi, and Dave Miller. "A Corelis debugger with the device under test. Slave emulators and some by
reconfigurable design-for-debug infrastructure for SoCs." In Proceedings of the 43rd annual Design Automation
Conference, pp. 7-12. 2006.
[4] Keshava, Jagannath, Nagib Hakim, and Chinna Prudvi. "Post-silicon validation challenges: How EDA and
default slave scripts were used to test various status flags and interrupts.
academia can help." In Design Automation Conference, pp. 3-7. IEEE, 2010.
[5] Farahmandi, Farimah, Ronny Morad, Avi Ziv, Ziv Nevo, and Prabhat Mishra. "Cost-effective analysis of post-
silicon functional coverage events." In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, pp. An ARP issue encountered made it crucial to have every relevant flag or
392-397. IEEE, 2017.