APPLICATION NOTE

[Link]

NCP4318 Tips and Tricks

AND90154/D
LLC converter is a popular isolated dc−dc power Drain Voltage of SR MOSFETs
conversion topology for high power applications. Figure 2 shows an example of the secondary−side currents
The primary−side winding of the transformer in LLC and voltage waveform of SR MOSFETs. When the current
converter sees an ac current of the resonant tank. In lower in the Lr and Lm of the primary side of the LLC converter
output voltage scenarios, center−tapped windings are used diverts from each other, the difference between them
for the secondary side of the transformer. Two diodes are becomes the current transferred to the secondary side.
used to rectify the output current of the secondary windings. Whatever MOSFET or the body diode conducts
To improve conversion efficiency of the LLC converter, the secondary−side current, Figure 2 notes the current as
people use a synchronous rectification (SR) technique on ISD, as the current is flowing from source to drain terminal
the output rectifying diodes. Synchronous rectification of the SR MOSFET. When the current flows through M1,
means using power transistors to replace the diodes. Within VDS of M1 pulls low. If M2 conducts the secondary−side
the diode conduction time duration, turn on the power current, VDS of M1 shows VOUT plus reflected voltage from
transistor to replace the diode’s conduction role. It takes the the transformer winding, which makes the voltage
advantage of the on−resistance voltage drop of the power amplitude roughly two times of VOUT.
transistor being lower than forward voltage drop In a below−resonant operation of the LLC converter, there
of the diodes, thanks to the low on−resistance RDS−ON is a duration that no current is transferred from the primary
of modern power transistors, such as power MOSFETs. to the secondary side. The capacitor across the drain
NCP4318 is a synchronous rectification controller and source terminals of the two SR MOSFETs resonates
dedicated for LLC converters. Figure 1 shows a typical with the equivalent Lr reflected to the secondary side,
application circuit of NCP4318. It senses the voltage across making a sub−resonance as in Figure 2.
drain and source pins of the SR MOSFETs through two sets Zooming in the VDS and ISD waveform when the ISD
of VD and VS pins. An ROFFSET is placed in series of each current conducts, we get a waveform as shown in Figure 3.
VD and drain pin connection. NCP4318 has two VG pins to The body diode of the SR MOSFET conducts first and then
drive the respective SR MOSFET when its body diode can NCP4318 generates gate signal, VG, making the SR
be forward biased. VDD of NCP4318 can be supplied by MOSFET turned on. The amplitude of VDS change from
voltage not higher than 37 V, so the output voltage the forward voltage of the body diode to the voltage drop
of the LLC converter can be directly used as NCP4318’s across the MOSFET’s on−resistance. Thus, the conduction
power supply. Thus, NCP4318 can control the SR loss of the secondary−side current on the rectifying device,
MOSFETs with very low external part counts. which means diodes, can be reduced. The gate signal will be
NCP4318 datasheet [1] had introduced basic operation turned off before the ISD current drop to zero. The time
principle of this controller. This application note provides interval between gate turning off and current dropping
further explanation for its practical operation in different to zero is the dead time of the SR gate signal.
scenarios.

Figure 1. Typical Application Circuit of NCP4318

© Semiconductor Components Industries, LLC, 2022 1 Publication Order Number:

January, 2023 − Rev. 1 AND90154/D
 AND90154/D

VDS.M 1 stray inductance can still be found in the short PCB trace and
Sub−resonance
the MOSFET package. The stray inductance generates a
~2*VOUT
voltage difference VLS when amplitude of the
flowing−through current changes. The sensed VDS becomes
ISD.M1 a summation of VLS and –ISD ⋅ RDS−ON. When ISD drops,
VLS becomes positive, which raises VDS voltage and makes
the SR controller turn off the SR MOSFET prematurely, as
ISD.M2 shown in Figure 4 (b).
To overcome the premature turn−off phenomenon,
NCP4318 has a range of adjustable VTH−OFF levels and it
Ilr, ILm can adjust the VTH−OFF by optimizing its turning−off instant
Ilr and adjusts the VTH−OFF to regulate the dead time. For
ILm
avoiding overreaction of the VTH−OFF adjustment, the
optimized dead time is defined as a hysteresis band.
NCP4318 adjusts VTH−OFF higher for the dead time being
Figure 2. Typical SR Current and Voltage longer than tDEAD−HBAND and lower for the dead time being
Waveforms of a Below−resonant LLC Converter shorter than tDEAD−LBAND . More, the VTH−OFF is adjusted
with high resolution by the combination of VTH−OFF and
VDS.M1 IOFFSET. These are depicted in Figure 6 and Figure 7.
The IOFFSET and ROFFSET changes the VDS detected in the
VD and VS pins, making the turn−off criterion become
Voltage drop of on−resistance
V DS ) I OFFSET @ R OFFSET * V TH*OFF + 0.
Body diode’s forward voltage (eq. 1)

VG1
So, we can define a virtual VTH−OFF as a combination of
VTH−OFF and IOFFSET’s effects as
ISD.M1
Virtual V TH*OFF + V TH*OFF * R OFFSET @ I OFFSET.
(eq. 2)
t
With both VTH−OFF and IOFFSET as variables, VTH−OFF is
Figure 3. Zoomed−in Waveform of SR Current defined as larger step and IOFFSET is defines as smaller step
and Voltage of the adjustment of the virtual VTH−OFF. Both of them are
controlled by 5−bit digital numbers, so there are totally 1024
Dead Time Regulation and VTH−OFF Range
variations of the combination. Stepping down of the virtual
Figure 4 (a) shows an ideal operating scenario of the SR
VTH−OFF can happen in every switching cycle for a fast
MOSFET in LLC converters. When the body diode of the
response. However, stepping up of the virtual VTH−OFF
SR MOSFET conducts, voltage across its drain and source
needs 128 consecutive switching cycles having tDEAD >
terminals, VDS, goes negative. Its amplitude is the forward
tDEAD−HBAND. This is for avoiding too fast dead time
voltage of the body diode. NCP4318 senses the VDS to turn
reduction that may interfere the feedback loop of LLC
on the SR MOSFET when the measured VDS is lower than
control.
a turn−on threshold voltage noted as VTH−ON in the figure.
IOFFSET varies between 0 and 310 mA, and NCP4318 has
Since turned on the SR MOSFET, VDS shows the voltage
two different step size for VTH−OFF. To make the
drop on the RDS−ON. As the source−to−drain current ISD
IOFFSET⋅ROFFSET fill the step size of VTH−OFF, the
drops, VDS rise to a value close to 0 mV, and NCP4318 turns
off the SR MOSFET based on a turn−off threshold voltage recommended ROFFSET value is 30 W for
VTH−OFF. Then, ISD conducts via body diode for the VTH−OFF−STEP = 8 mV and 15 W for VTH−OFF−STEP = 4 mV.
remaining duration of non−zero ISD. More, except the VTH−OFF−STEP options, NCP4318 also has
In practical scenarios, there are parasitic inductance two different options for VTH−OFF−MIN . VTH−OFF−MIN and
everywhere in the current conducting path. Even if two VTH−OFF−STEP defines the variable range of VTH−OFF.
separate pins are used to sense the differential voltage VDS, Larger VTH−OFF−STEP leads to higher VTH−OFF−MAX .

[Link]
2
 AND90154/D

IOFFSET Turn−off
ROFFSET VD

VTH−OFF
VDS VS
COM2

a) Without Stray Inductance Figure 7. IOFFSET and the Virtual VTH−OFF

V TH*OFF*MAX + V TH*OFF*MIN ) 31 @ V TH*OFF*STEP

(eq. 3)
Wider range of VTH−OFF may be required when the stay
inductance of the SR MOSFET is higher, such as with
TO−220 package, or the LLC is operating in below−resonant
region mostly. When the LLC converter operates in
below−resonant region, as in Figure 8 (a) and (b), variation
in current slope tends to be larger. Thus, the effect of stray
inductance on VDS becomes much variable. If the variable
range of VTH−OFF is not large enough, the dead time will be
larger in heavy load condition. It is due to saturation of the
a) With Stray Inductance
adjustable VTH−OFF range; the required VTH−OFF for the
Figure 4. Effect of Stray Inductance on VDS wanted dead time is higher than VTH−OFF−MAX .

Inspecting VD Waveform on Oscilloscope

The operation of NCP4318 is based on detecting the
voltage across drain and source terminals of SR MOSFETs
to decide whether the VG signal should be high or low. For
an LLC converter with 19.5 V of output voltage, typical VD
waveform is like Figure 9 (a) and has an amplitude of around
40 V, but the portion of interest for VD waveform during the
SR operation is in the range of −1~1 V.

Figure 5. Stray Inductance of the MOSFET Package

Figure 6. Hysteresis Band of Dead Time Regulation

by Adjusting the Virtual VTH−OFF

[Link]
3
 AND90154/D

Overall, the waveform captured by differential probes

shows a much correct wave shape, but the oscilloscope may
introduce some voltage offset at different voltage scale
according to the oscilloscope’s characteristics. Inspecting
the behavior of SR controller by capturing VD signal has no
problem but capturing threshold voltage like VTH−OFF may
a) Below Resonant, b) Below Resonant, not be easy in an operating LLC converter.
Heavy Load Light Load
Minimum On−Time and Multi−Step VTH−OFF
When SR gate is turning on, VDS may show ringing due
to parasitic components. NCP4318 has a minimum on−time
(tON−MIN ) to avoid premature gate turning off by the
parasitic ringing.
In a load−transient condition under above−resonant
operation, the SR conduction time may reduce a lot in
c) Above Resonant, d) Above Resonant, consecutive cycles. NCP4318 has a multi−step VTH−OFF to
Heavy Load Light Load
deal with sudden reduction on the SR conduction time. The
Figure 8. SR Current Waveform in Different multi−step VTH−OFF means to have lowered VTH−OFF in a
Operating Region of LLC Converter time duration defined as K2ND−TOFF.
(Ch1: VG1 2 V/div, Ch2: VG2 2 V/div, Ch3: VD1
200 mV/div, Ch4: ISD1 2 A/div)

a) Typical VD Waveform b) VD in 2 V/div

Figure 10. tON−MIN Prevents Premature

Turning−Off by Ringing Noise

c) VD in 1 V/div d) VD in 0.5 V/div

Figure 9. VD Waveforms Captured by an Oscilloscope

(Ch1: VG1 10 V/div, Ch2: VD1 by Standard Probe,
Ch3: VD1 by Differential Probe)

When you try to check VD waveform in the range of

interest for NCP4318 by oscilloscope, some non−ideal Figure 11. Multistep VTH−OFF Turns Off SR GATE
waveform may be captured due to oscilloscope’s Earlier when SR Conducting Duration Reduces
characteristics. In the Figure 9, channel #2 and #3 are
capturing the same VD signal with different probes. Both tON−MIN and K2ND−TOFF response to operating
Channel #2 is with standard 10x probe and channel #3 uses information of its previous switching cycle, making them
a differential probe set at 1/20 of signal ratio. Comparing adaptive to operating conditions. The tON−MIN refers to a
Figure 9 (b) and (c) for the y−axis zoom−in of the VD signal SRCOND signal, and K2ND−TOFF refers to gate on−time.
around 0 V, the shape of VD is slightly different between two More, tON−MIN and K2ND−TOFF change according to
kinds of probes. Also, when the voltage scale changes, DC operating−mode flags DLY_EN and LLD respectively.
offset of the signal may also change. In Figure 9 (d), the Definition and variation of SRCOND, tON−MIN, and
waveform captured by the standard 10x probe is even K2ND−TOFF under different operating modes of NCP4318
distorted in its wave shape. are depicted in Figure 12.

[Link]
4
 AND90154/D

Figure 13. Leading−edge Inversion Current

When the leading−edge inversion current happens, the

a) DLY_EN = 0, LLD = 0 current inversion detection function SRCINV will be
triggered once. Then, turning−on criterion of VG1 and VG2
become requiring VD1 and VD2 to be lower than VTH−ON
continuously for a tON−DLY2 duration. To avoid conducting
inversion current, the tON−DLY2 needs to be longer than the
discharging time of the capacitive current and period of the
following sub−resonance.
NCP4318 offers various tON−DLY2 options from 240 ns to
1580 ns. For an LLC converter operating in above−resonant
region, tON−DLY2 doesn’t need to be too long. It may still
work in below−resonant region during its input bulk voltage
hold−up time during power−off, which is usually a
heavy−load condition. However, when an LLC converter
b) DLY_EN = 1, LLD = 0 can operate in below−resonant region with light load
condition, longer tON−DLY2 may be required for avoiding the
leading−edge inversion current.

c) DLY_EN = 0, LLD = 1 or 2

Figure 12. tON−MIN and K2ND−TOFF in Different Modes Figure 14. tON−DLY Changing Instant

Leading−Edge Inversion Current and tON−DLY2

For an LLC converter operating in below−resonant region
and light−load condition, current may conduct two times in
one switching cycle for a rectifier branch. This phenomenon
had been explained in [2] as capacitive current. The main
reason is that the amplitude of the Cr voltage is not enough,
so the Lr current doesn’t built up at the beginning of the
primary−side on time. However, the COSS
charging/discharging during the switching transition make
the SR MOSFET’s body diode conducts for a short period.
If SR MOSFET turns on in the short period, it results in
leading−edge inversion current in the SR MOSFET
conducting duration, which makes additional conduction Figure 15. tON−DLY2 Avoids Inversion Current
loss.

[Link]
5
 AND90154/D

SRCINV makes turning−on delay time as the longer

tON−DLY2 , instead of a short tON−DLY. To recover back to the VDD = VOUT VDD−GATE−ON
short tON−DLY, NCP4318 inspects VD waveform before SR t
gate turning on. If VD crosses below VTH−ON for only one
time, a hINV−EXT counter adds by one. This counter resets
VD1, 2
when the VD < VTH−ON event happens more than one time
in one switching cycle. When the hINV−EXT counter has t
reached 16000, the criterion of turning on the SR gain 256 cycles
recovers back to tON−DLY, which is simply a propagation VG1, 2
7V
delay. It can also be witnessed in Figure 16 that the t
recovering from tON−DLY2 of one channel is independent a) VDD Connects to VOUT
from the other channel.
VDD−GATE−ON
VDD

VOUT
t

VD1, 2

t
256 cycles
VG1, 2 10 V
7V
t
Figure 16. Recovering from the Long tON−DLY2
b) VDD Connects to an Auxiliary Power Source

Figure 17. Soft Start

Soft Start and VDD Connection
Although the steady−state operation of an LLC converter
[31]
is pulse−frequency modulation (PFM) with designed IOFFSET
frequency range, different LLC controllers may have [0]
different process of initiating its switching operating after [8] [9]
[5] [6] [7]
power on. After VDD exceeds VDD−GATE−ON, NCP4318 VTH− [2] [3] [4]
counts switching cycle of the LLC converter and skips the OFF

SR gate output for the first 256 cycles to avoid any LLD [2] [1] [0]
unpredicted behavior from the LLC controller. VDD of
NCP4318 can be connected to VOUT or an auxiliary power VG1, 2 10 V
6V
source. With different connection, the SR gate starts at
different moment when the LLC converter start its switching 24576 cycles
operation. Figure 18. IOFFSET, VTH−OFF, LLD, and VGATE when
the Virtual VTH−OFF Keeps Increasing

[Link]
6
 AND90154/D

When NCP4318 starts to deliver SR gate signals during Primary−side

ML MU ML ML MU ML
soft start, amplitude of VG1 and VG2 starts with 7 V. If the
Gate signals t
ILr dormant
adaptive gate voltage control is not enabled, VG1 and VG2 Resonant−
changes its amplitude to 10 V after another 256 switching tank current t
ILm
cycles. However, when the adaptive gate voltage control is
enabled, amplitude of VG1 and VG2 will be decided by the
LLD status. Take NCP4318ALC as an example. Its ISD1 ISD2
Rectifier
VTH−OFF−MIN , VTH−OFF−STEP, and VTH−OFF−RST are −6, 4, currents

and 2 mV, which means, at powering on, its VTH−OFF reset t

to the 2nd step (( 2 mV − ( −6 mV )) / 4 mV = 2nd step ), in a) Example #1
which the 32 steps of VTH−OFF are noted as 0~31st steps.
VGATE amplitude changes to 10 V when the VTH−OFF is
Primary−side
higher than the 7th step. Each VTH−OFF step includes 32 steps Gate signals
ML MU ML ML MU ML
t
of IOFFSET change, and it takes 128 switching cycles for the ILr dormant
virtual VTH−OFF to increase by one step of IOFFSET change. Resonant−
t
tank current
Assuming the virtual VTH−OFF keeps increasing during the ILm
process, it will take roughly (7 − 2 + 1) ⋅ 32 ⋅ 128 = 24576
switching cycles to make VTH−OFF rise to the level that
Rectifier ISD2 ISD2
makes VGATE change to 10 V. Overall, when the adaptive currents
gate voltage control is enabled, the number of 7−V gate
pulses during soft start is much larger than 256. t
b) Example #2
Similar to the soft start, with different VDD connection,
SR gate signal stops at different moment when VOUT drops Figure 19. Examples of Light−load Mode Current
during power off. In case VDD is supplied from VOUT, VG1 Waveforms
and VG2 stops when VOUT drops below VDD−GATE−OFF,
even if the primary side LLC controller still delivers gate
pulses to the LLC converter.

Working with LLC Controllers with a Light−load Mode

Instead of operating the LLC converter with
pulse−frequency modulation (PFM) with 50% of duty cycle,
some LLC controller provides special primary−side gate
drive pattern to improve light−load efficiency. Let’s call it a
light−load mode here. The idea is to make the LLC converter
delivers similar amplitude of current to the secondary side
with similar primary−side pulse on−time, while modulating a) Primary−side Pulse vs. VD of SR
a dormant duration to adjust average delivered power.
In this mode of operation, the rectifier currents don’t grow
in every primary−side gate pulse. Whether the rectifier
currents grow or not depends on the design of the
primary−side pulse packet. For example, in Figure 19, you
see ML−MU−ML primary−side pulse packets. Figure 19 (b)
shows shorter on−time in the last ML of the packet. It results
in no energy delivering during the MU pulse duration due to
the resulting Cr voltage in that duration.
Whatever the light−load−mode packet is, while the
rectifier currents grow, we want the respective SR gate to
turn on, like what we can see in Figure 20. To better cope b) Respective SR Gate Pulse
with the light−load mode operation, you can select Figure 20. Waveform of NCP4318 Working
NCP4318 with its parameters adjusted as described below. with Light−Load Mode

[Link]
7
 AND90154/D

Shorter tON−DLY2
NCP4318 utilizes tON−DLY2 to deal with the leading−edge VD
inversion current happening in light−load conditions. When t
the LLC converter operates in the light−load mode, the After GREEN2, SRCINV,
leading−edge inversion current may not happen. In addition, or reset to initial conditon.
the modulated dormant period, which had been indicated in VG
Figure 19, can be longer than tGRN2−ENT, making tON−DLY2
be activated. Thus, to work with LLC controllers with such t
kind of light−load mode, the tON−DLY2 parameter should be Maximum
on−time 1.2 ms +550 ns +550 ns
shorter, such as 240 ns in NCP4318AHD.
a) tGATE−LIM Function
However, sometimes the leading−edge inversion current
may still happen in light−load mode. The primary shutdown
VD
may be triggered in this condition, as shown in Figure 21. In
this situation, slightly longer tON−DLY2 to cover the t
capacitive current spike can help the SR operate much Deficient of SR gate
stably. on−time due to the
VG tGATE−LIM function

t
Maximum +550 ns at most Dead−time
on−time regulation
b) tGATE−LIM under a Short−long−short
Conduction Pattern
Figure 22. tGATE−LIM Function

Reduce tOFF−MIN
NCP4318 has a tOFF−MIN function which avoids SR gate
to be turned on by the noise generated around its turn−off
transition. SR gate is prohibited to be turned on again after
turning off within a tOFF−MIN time window. In the light−load
Figure 21. A Light−load Mode with Leading−edge
Inversion Current Makes Primary Shutdown mode operation, if the dormant duration, as in Figure 19, is
Protection Triggered very short, the SR gate may need to be turned on again after
it has just been turned off before the short dormant duration.
In this condition, we want the tOFF−MIN parameter of
Disable tGATE−LIM NCP4318 to be shorter.
The SR conduction duration of the light−load mode may
vary a lot in consecutive switching cycles. NCP4318 has an
optional tGATE−LIM function that makes the SR gate on−time
VD
increase gradually, as shown in Figure 22 (a). When the SR t
operation is reset by power−on, SRCINV, or other
protections, the on−time of SR gate pulses starts from 1.2 ms.
The increment rate of the SR gate pulses from their previous tOFF−
VG MIN
cycles is limited to 550 ns. Apparently, that function will
make the SR gate on−time always small when the SR t
conduction duration shows a repetitive short−long−short Figure 23. tOFF−MIN Function
pattern, as shown in Figure 22 (b). In a light−load mode, the
primary−side gate pulses of the LLC converter tend to be not NCP4318 has shorter tOFF−MIN option for both its
consistent, so as the SR conduction duration. Thus, the H−version and L−version. In addition, since tON−DLY2 itself
tGATE−LIM function should be disabled to make the SR gate can be seen as a minimum off−time, NCP4318 also offers an
on−time follows the actual conduction duration detected option to disable tOFF−MIN when tON−DLY2 has been
from VDS signal. activated.

[Link]
8
 AND90154/D

Estimating Gate−drive Power Consumption

The operation of SR is to turn on the MOSFET when the
body diode is in conduction and turn off the MOSFET to let
the body diode takes over at the end of the conducting
duration. Load of the gate driver is CISS and CRSS of the
MOSFET at VDS ≈ 0V. The VDD pin’s sinking current, IDD,
can be estimated as below.
C TOTAL 5 S all_MOSFETsǒC ISSǒ V DS + 0 Ǔ ) C RSSǒ V DS + 0 ǓǓ
(eq. 4)

I DD + I DD ) C TOTAL @ V GATE @ f SW
VG_loaded VG_open
(eq. 5)
For example, the MOSFET FDMS004N08C shows Figure 24. Capacitance vs. VDS Drawing
CISS ≈3200 pF and CRSS ≈ 270 pF. When we put two for FDMS004N08C
MOSFET in parallel for each VG channel and make the LLC
converter operate at 103 kHz at full load, the total average The total power consumption of NCP4318 is VDD*IDD,
current consumption of the gate drivers is but not all power needs to be eventually dissipated as heat on
(3200 pF + 270 pF) × 2 × 2 × 10.5 V × 103 kHz = 15 mA. NCP4318. The gate−drive portion of the power
When VG pins are open, the measured IDD is as 3 mA. So, consumption have some variation based on external
the total IDD is 18 mA. circuitry. For example, when there is a series resistor RG in
the turning−on current path, it slows down the turn−on slew
rate and makes the power dissipated on RDRV−SOURCE
becomes

R DRV*SOURCE
E DRV*SOURCE + ǒV DD @ C TOTAL @ V GATE*MAX * 0.5 @ C TOTAL @ V GATE*MAX Ǔ@
2
(eq. 6)
R DRV*SOURCE ) R G

which implied that part of power dissipation will be directed VDD

from RDRV−SOURCE to the external RG. Also, the total
energy that needs to be dissipated during gate turning off is RDRV−SOURCE
0.5 × CTOTAL × VGATE−MAX2. The turn−off energy can be
VG RG
directed to an external PNP bipolar transistor when it is used VGATE−MAX
in the turn−off circuit. However, with the simplest ISOURCE
connection in Figure 1, which connects VG pins to
MOSFET’s gate terminal without any additional elements,
the gate drive power dissipation will be all on the NCP4318
chip.
a) Gate Current Sourcing
P DRV + V DD @ C TOTAL @ V GATE*MAX @ f SW
(eq. 7) VDD

VG

Isink

b) Gate Current Sinking

Figure 25. Gate Current Sourcing and Sinking

Situation with Additional Elements

[Link]
9
 AND90154/D

PCB Layout Recommendation between VS pin and source pin of MOSFET. If there is
To explain the recommended PCB layout, let us look at the additional connection between the GND pin and the output
example of an SR daughter card with NCP4318A as its SR ground, the impedance is denoted as Z3. Assume Z1<<Z2
controller in Figure 26. and Z1<<Z3, for Z1 being in the main current trace. The
VD1 and VD2 pins for drain sensing are connected to voltage difference VS0 between IC’s VS pin and MOSFET’s
drain pads at terminals that the flowing current, indicated as source pin can be derived as I sec @ Z 1ń2 for Figure 27 (a) and
arrows, begins. It is not at any middle way of any possible I sec @ Z 1 @ (Z 2 ) Z 3)ń(Z 2 ) 2Z 3) for Figure 27 (b). The
current path. This connection avoids the noise generated by voltage difference VS0 in Figure 27 (a) is smaller between
the changing current and the stray inductance on the PCB the two.
trace.
VS1 and VS2 pins are connected to SR MOSFET’s source
Isec
terminals and GND pin separately, forming a Y connection.
GND pin also connect to a VDD capacitor.
Gate drive current goes from VG1 and VG2 to the
respective source terminal of the MOSFET and returns to Z2 Z2
GND through the VS1 and VS2 connections. Keeping the VS0
loop area of VG and VS connections small avoids the gate Z1 Z1
drive current loop to interfere other parts of the circuit.
For a higher wattage application, gate charge for
MOSFETs in each switching cycle can be higher. Using a) IC round doesn’t connect to output ground
external PNP transistors Q1 and Q2 to help the turning−off
process can be considered. The PNP transistors reduces
turning−off current−loop area and alleviate the power Isec
consumption on the SR controller during the turning−off
process.
Z2 Z2
VS0
Z1 Z1
Z3

b) IC ground connects to output ground

Figure 27. Ground Connection and Current Flow

Enhancing Heat−Dissipation Capability of SOIC−8 EP

a) Printed Circuit Board
Package
When NCP4318 needs to drive more paralleled SR
MOSFETs in higher−output−current designs, power
consumption on the gate driver of NCP4318 gets higher.
Higher power consumption leads to higher junction
temperature on the chip. NCP4318 has an SOIC−8 EP
package variant in its lineup. This type of package provides
exposed pad for direct thermal attachment, which makes
lower the thermal impedance to the chip. To make good use
of the package’s characteristic, here we provide additional
b) Schematic reminder on the PCB layout design.
The exposed pad can be connected to NCP4318’s GND
Figure 26. NCP4318A SR Daughter Card
pin. When a PCB design still has some room to extend the
copper area for GND, one way to enhance the thermal
The GND pin of NCP4318 is connected to LLC
dissipation is to connect the GND copper area to the exposed
converter’s output ground terminal through the VS
pad of the package. This way, the copper area is utilized as
connections. It doesn’t need to connect to output ground
heat−sinking copper. Make sure that the exposed pad
with other additional connection. Figure 27 shows the
connects exactly to the copper area. More, note that the GND
connection methods of VS pins, GND pin, and the output
copper area is signal ground for NCP4318, not power
ground of the LLC converter. It is assumed that the layout is
ground for the output of the LLC converter.
perfectly symmetrical. Z1 is the impedance between source
pin of MOSFET and the output ground. Z2 is the impedance

[Link]
10
 AND90154/D

If the PCB design is of multi−layer, you may consider VD

Isec
drawing the ground copper area in the other layer of the same VTH−HIGH
position as the IC and connecting the exposed pad to the VD
ground copper area through thermal vias. The thermal vias VDS IG
can be spaced by 1 mm and have diameter of 0.3 mm.
Figure 28 provides a design example.
VS0
VGATE

Figure 29. Effect of Gate Turn−off Current on VDS

Misfiring on the SR Gate while the LLC Controller Shuts

Down
Another example that adding a capacitor between VD and
GND may help happens at shutting down of the LLC
controller. When the primary side LLC controller shuts
a) Top side down its operation, the resonant tank stops delivering energy
to the secondary side. The remaining energy in Lm and COSS
of the primary−side power switches makes a resonance. The
voltage across Lm reflects to the secondary side, making a
slower ringing on VDS of the SR MOSFETs. At the same
time, the remaining energy in COSS of SR MOSFETs and
leakage inductance on the secondary side makes an
additional resonance at a much higher frequency. Waveform
of the two resonances is shown in Figure 30.

b) Bottom side

Figure 28. A PCB Layout with Thermal Vias for

Package with Exposed Pad

Situations That May Require Filtering Capacitors

on the VD Pins
The application schematic of Figure 1 mentioned that a
capacitor may be added between VD and GND pins. The
added capacitor on VD pin forms a low−pass filter with
ROFFSET on the VD signal. Since the low−pass filter will Figure 30. Added−up Resonances on VDS at LLC
leads to delay on the VD signal, time constant of the Controller Shutting Down
low−pass filter had better not to exceed 30 ns for a proper SR
operation. The capacitor is not required in general cases for When the two resonances are added up, VDS on the SR
NCP4318 to operate normally. However, there are some MOSFET may satisfy VTH−ON and NCP4318 generates gate
cases that adding capacitors on VD pins may help. turn−on signal, which results in an inversion current
Gate Turn−off Noise conducted in the SR MOSFET. The SR inversion current
When the gate capacitance of the MOSFET is huge, detection function or the primary shutdown protection can
amplitude of the MOSFET turn−off current tends to be turn off the SR gate immediately; however, it is even better
higher. The turn−off current of the gate driver can induce a if the VG signal isn’t turned on by the VDS ringing. In such
voltage spike on the parasitic inductor in the current path, as a case, adding a R−C snubber to the SR MOSFET or adding
described in Figure 29. If the spike is not higher than a capacitor for the VD signal can absorb or filter out the VDS
VTH−HGH, it doesn’t cause problem. However, if the spike ringing, avoiding the mis−triggered SR gate pulse. Note that
makes VD exceeds VTH−HGH (0.85 V in typical), it may the ROFFSET and VD−pin capacitor equivalently form an
mis−trigger abnormal−VD protection, or at least interfere R−C snubber to the SR MOSFET.
the dead−time judgement. In such a situation, adding Mis−triggering of SR Gate During LLC Hold−up Time
VD−pin capacitors may help to filter the spike. Or there are Yet another example that adding VD−pin capacitors may
also orderable part numbers of NCP4318 that has a higher help happens during hold−up time. The LLC converter tends
VTH−HGH of 1.5 V, which can be an alternative solution to to operate in below−resonant region during the hold−up
this situation. time, so sub−resonance can be seen in each switching cycle.

[Link]
11
 AND90154/D

In addition, since the load during hold−up time is usually board or noise that is beyond resolution of oscilloscope.
heavy, turning−on delay of NCP4318 tends to be the shorter In Figure 32 (a), when the VG2 turned off, VD2 didn’t show
tON−DLY, which means the SR gate turns on immediately a waveform that satisfied VTH−OFF or SRCINV. Although
when VD < VTH−ON. Furthermore, the VCr amplitude tends the oscilloscope didn’t capture the problem, it was found
to be high during the hold−up time. that the problem can be solved by adding a capacitor on the
In some design examples, the amplitude of VCr may be VD2 pin. If that happens in your design too, adding capacitor
increased larger than VIN. Thus, when the current in M1 cuts on VD pins can be worth trying.
off and VD shows sub−resonance, the amplitude of the
sub−resonance becomes larger than 2 × VO, as depicted in
Figure 31. It makes VD2 dips to a negative value, which may VD1
1V/div
satisfy the VTH−ON criterion and mis−triggers turning−on of VD2
M2. Same phenomenon happens on M1 on the other half 1V/div

cycle.
In this case, a snubber on SR MOSFETs damps the
sub−resonance and makes the amplitude of the
VG1
10V/div
sub−resonance reduce faster. Thus, adding snubber, or using VG2 turns
VD−pin capacitor to form an equivalent snubber with VG2
10V/div
off, but no
clue can be
ROFFSET, helps avoiding the mis−triggering of SR gate found in VD2.
signals. time 5μ s/div
a) Without VD−pin capacitor

VD1
1V/div
VD2
1V/div

VG1
10V/div
VG2 operates normally.
VG2
10V/div
a) An LLC Converter
Slope = time 5μ s/div
(VIN − VCr)/(Lm + Lr) b) With VD−pin capacitor

ILr Figure 32. SR Gate is Turned off

by Not−capturable Noise

VIN
VCr Conclusion
VIN/2
NCP4318 is an SR controller for LLC converters with
nVo
(VIN − VCr)Lm/(Lm + Lr) center−tapped secondary−side configuration. With highly
VTx integrated functionalities, NCP4318 controls the SR power
switches with very few additional circuit elements.
2Vo NCP4318 delivers the driving pulses for SR power switches
Vo + VTx/n that maximize the efficiency of LLC converters. With
Vo
VD2 sophisticated protections, NCP4318 responds to sudden
changes in the operation of LLC converters with appropriate
actions in the gate drive signals.
NCP4318 has several orderable part numbers (OPNs) that
b) Sub−resonance that Causes Mis−trigger of SR Gate provides different function sets and parameter values. For
Figure 31. Increased Sub−resonance Amplitude different LLC converter designs, the required function sets
During Hold−up Time and parameter values may vary. This application note is
meant to share the insights for selecting the appropriate OPN
by explaining the functionalities in much detail. Some
SR Gate turns off by not−capturable noise
circuit design tips are provided to ease the difficulties that
It had been observed that SR gate may sometimes be
one might sometimes confront when designing LLC
turned off while no clue can be found on its respective VD
converters with NPC4318 for the SR control.
signal. Possible reasons may include radiated noise on the

[Link]
12
 AND90154/D

References
[1] NCP4318 Data Sheet
[Link]
.pdf
[2] LLC Resonant Converter Synchronous Rectification Design using FAN6248
[Link]

onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at [Link]/site/pdf/Patent−[Link]. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT: TECHNICAL SUPPORT
Email Requests to: orderlit@[Link] North American Technical Support: Europe, Middle East and Africa Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 00421 33 790 2910
onsemi Website: [Link] Phone: 011 421 33 790 2910 For additional information, please contact your local Sales Representative

◊ [Link]
13