austriamicrosystems AG

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AS3693B austriamicrosystems

Product Specification, Confidential

AS3693B–16 Channel high precision LED driver for

LCD Backlight

id
al
1 General Description

lv
The AS3693B is a 16 channels high precision LED
controller with build in PWM generators for driving
external FETs in LCD-backlight panels.
External clock and synchronizing inputs allow the

il
synchronization of the LCD backlight with the TV
picture. Local dimming and scan dimming is

st
te G
supported by 16 independent PWM generators with
programmable delay, period and duty cycle. Three
free configurable dynamic power feedback circuits
on A
make the device usable for white LED as well as
nt
RGB backlights. Build in safety features include
thermal shutdown as well as open and short LED
Free programmable 12 bit resolution ( period,
detection. All circuit parameters are programmable
lc s

high time and delay )

via I2C or SPI interface.
Overvoltage detection ( short LED )
am

Undervoltage detection ( open LED )

Temperature shutdown

Fault interrupt output
2 Key Features
H-Sync, V-Sync inputs to synchronize with TV-
set

16 Channel LED driver
Internal or external PWM – clock

I2C interface

Output current only limited by external
transistor
SPI interface

Output voltage 0.4V to 50V
5 bit device - address (sets device address

Absolute current accuracy +/- 0.5% and interface mode)

Automatic supply regulation feedback

Output slew rate programmable
Each output can be assigned to red, green or
ca

Current programmable with external resistor

Linear current control with 8 - bit DAC blue feedback.

Linear current control with external analog
Package epTQFP64 and QFN64
voltage
ni

Digital current control with 16 independent

PWM generators
ch

3 Applications
• LED backlighting for LCD – TV sets and
monitors
Te

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AS3693B austriamicrosystems

4 Block Diagram

Vsupply

V2_5
REF
FBG
FBR
FBB
Vreg
Reference,
PWM DAC PWM

id
Fault detectors
PWM PWM

SMPS

al
feedback
PWM PWM

lv
PWM PWM
AS3693B
PWM PWM

il
st
te G PWM PWM
on A
86 byte
PWM registers PWM
nt
lc s

PWM SPI / I2C PWM

Interface
am
Hsync
Vsync

Addr2
Addr1
Fault
SDO
SDA
SCL

V2_5
CS

Typical application
Vdcdc

Power Supply
ca

16 output
channels
ni

Rvreg
ch

2.2uF
10k

10k

10k

Vreg Curr1 Rfb1 Curr2 Rfb2 Curr15 Rfb15 Curr16 Rfb16

Gate1 Gate2 Gate15 Gate16
SDI
SCLK
Rfb

xCS
Te

Vsync
Micro Hsync
controller 100k 100k V2_5 AS3693B FBR
FBG
10k

10k

FBB
SDO
Fault Cfb Cfb Cfb
Ref(EXT) V2_5 AGND GND ADDR2 ADDR1
10uF 10uF 10uF
( Exposed Pad )

2.2uF 2.2uF

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AS3693B austriamicrosystems

Table of Contents
1 General Description ....................................................................................................................................... 1
2 Key Features.................................................................................................................................................. 1
3 Applications.................................................................................................................................................... 1
4 Block Diagram................................................................................................................................................ 2
5 Characteristics ............................................................................................................................................... 4
5.1 Absolute Maximum Ratings .................................................................................................................... 4
5.2 Operating Conditions .............................................................................................................................. 5
5.3 Electrical Characteristics......................................................................................................................... 6
6 Typical Operation Characteristics .................................................................................................................. 8
6.1 Output current vs Output Voltage ........................................................................................................... 8

id
6.2 Vsupply vs VREG and V2.5 at startup .................................................................................................... 8
6.3 9us Slew Rate ......................................................................................................................................... 9
6.4 Supply Regulation ................................................................................................................................... 9

al
7 Block Description ......................................................................................................................................... 10
7.1 Feedback Circuit ................................................................................................................................... 10
7.1.1 Feedback Selection ....................................................................................................................... 11
7.1.2 Voltage fault registers .................................................................................................................... 12

lv
7.2 Curreg 1-16........................................................................................................................................... 12
7.3 PWM – modes ...................................................................................................................................... 14
7.3.1 SYNC mode (PWM_MODE = 00) .................................................................................................. 14
7.3.2 ASYNC – mode (PWM_MODE = 01) ............................................................................................ 16

il
7.4 PWM – high time, period and delay registers ....................................................................................... 17
7.5 Shunt Regulator .................................................................................................................................... 18

st
7.5.1
7.6
te G
Undervoltage lockout ..................................................................................................................... 18
Over temperature control ...................................................................................................................... 18
7.7 Device address setup ........................................................................................................................... 19
on A
7.7.1 I2C Device Address setup ............................................................................................................. 19
7.7.2
7.8
nt
SPI Device Address setup ............................................................................................................. 19
Digital interface ..................................................................................................................................... 20
7.8.1 I2C interface .................................................................................................................................. 20
lc s

7.8.2 SPI interface .................................................................................................................................. 22

8 Register map................................................................................................................................................ 24
am

9 Pinout and Packaging .................................................................................................................................. 27

9.1 Pinout.................................................................................................................................................... 27
9.2 Package drawing epTQFP64 ............................................................................................................... 29
9.3 Package drawing QFN64 ...................................................................................................................... 30
10 Ordering Information .................................................................................................................................... 31
Copyright............................................................................................................................................................. 32
Disclaimer ........................................................................................................................................................... 32
Contact Information ............................................................................................................................................. 32
ca
ni
ch
Te

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AS3693B austriamicrosystems

5 Characteristics

5.1 Absolute Maximum Ratings

Stresses beyond those listed in Table 1 may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated in Section 5
Electrical Characteristics is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 1 – Absolute Maximum Ratings

id
Symbol Parameter Min Max Unit Note
1
VDDMAX Supply for LED’s -0.3 >50 V See notes

al
VINVREG VREG supply voltage -0.3 7.0 V Applicable for pin VREG
Maximum Current flowing into
IINVREG Maximum Vreg current 100 mA
Vreg

lv
4
VIN2.5V 2.5 V Pins -0.3 V2_5+0.3V V Applicable for 2.5V pins
VREG+ 2
VIN5V 5V Pins -0.3 V Applicable for 5V pins
0.3V

il
Applicable for CURR1, CURR2,
VIN50V 50V Pins -0.3 55 V

st
te G CURR3 up to CURR16
IIN Input Pin Current -25 +25 mA At 25ºC, Norm: Jedec 17
on A
TSTRG Storage Temperature Range
nt -55 150 °C
Humidity 5 85 % Non condensing
Electrostatic Discharge on Pins
lc s

VESD -4000 4000 V Norm: MIL 883 E Method 3015

Curr1 – Curr16
am

VESD Electrostatic Discharge on all Pins -2000 2000 V Norm: MIL 883 E Method 3015
At Ta = 25ºC, no airflow for
PT Total Power Dissipation 3.8W W ePTQFP64 on two layer FR4-Cu
3
PCB
mW/ 3
PDERATE PT Derating Factor 40 See notes
°C
Body Temperature during according to IPC/JEDEC J-STD-
TBODY 260 °C
Soldering 020C

Notes:
ca

1, As the AS3693B is not directly connected to this supply. Only the parameters VINVREG, VIN5V and
VIN50V have to be guaranteed by the application
2, All pins except CURR1 to CURR16 and 2.5V
3, Copper area > 9 cm², thermal vias
ni

4, 2.5V Pins are Fault, SDO, ADDR1 and ADDR2

ch
Te

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AS3693B austriamicrosystems

5.2 Operating Conditions

Test circuit

Vcurr

Vreg
Vreg Curr1 Rfb1 Curr2 Rfb2 Curr15 Rfb15 Curr16 Rfb16

id
Gate1 Gate2 Gate15 Gate16
SDI
SCLK
xCS
Vsync

al
Hsync
V2_5 AS3693B FBR
FBG
10k

10k

FBB

lv
SDO
Fault
Ref(EXT) V2_5 AGND GND ADDR2 ADDR1

( Exposed Pad )

2.2uF 2.2uF

il
Table 2 – Operating Conditions

st
Symbol
te G
Parameter Min Typ Max Unit Note
Supply is not directly connected to
Not
on A
VDD Main Supply V the AS3693B – see section ‘Shunt
Limited
Regulator’
nt Applies only for supply VREG is
VDDTOL Main Supply Voltage Tolerance -20 +20 %
connected via Rvdd
lc s

Supply (shunt regulated by If internally (shunt-)regulated by

VREGINT 5.0 5.2 5.4 V
am

AS3693B) ZD1
VREGEXT 3 4.5 4.9 V If externally supplied
If Vreg < UVUL current sources
VUVL Untervoltage lockout voltage 2.4 2.7 3 V are turned off
( Addr 0x01,Addr 0x02 = 0x00 )
Excluding current through shunt
regulator (ZD1) – see section
Supply Current (Chip current
IVREG 20 mA ‘Shunt Regulator’. Note: Take care
consumption)
of the Power dissipation of the
external Resistor.
ca

Maximum Current Into VREG –

IVREG_M
Maximum Supply current 30 mA PIN (Supply current + shunt
AX
regulator current).
ni

Condition: externally supplied

IVREG 350 uA
EXT_OFF Curr_reg1-16 off (register 01h =
00h, register 02h = 00h)
ch

Igate Gate driving capability 0.5 1 2 mA Gate1 – Gate16 output current

Te

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AS3693B austriamicrosystems

5.3 Electrical Characteristics

Table 3 – Analog Electrical Characteristics

Symbol Parameter Min Typ Max Unit Note

VCURR Voltage at CURR1 to CURR16 50.0 V
Using 250mV reference
-0.5 +0.5 % @25C TJUNCTION, excluding
variation of external resistors
Using 250mV reference

id
(1)
-20°C to +100°C TJUNCTION,
ICURR, -1.5 +1.5 % -20°C to +85°C TAMB, excluding
Current Source Tolerance

al
TOL variation of external resistors;
V(CURRx) <= 4.0V
Using DAC reference

lv
VDAC =250mV ( Data = 0x80 )
-1.6 +1.6 %
@25C TJUNCTION, excluding
variation of external resistors

il
DAC_INL DAC INL -4 +4 LSB DAC integral nonlinearity
Automatic Supply Regulation trip See section ‘Feedback Circuit

st
VC
point
te G
Automatic Supply Regulation
0.5 1 V
(DCDC_Regulation_Trip_Point)’.
Voltage to current ratio; output
VC,GAIN 2.0 mA/V
on A
gain nt current range typ. 0 to 200uA
(2)
TOVTEMP Over temperature Limit 130 140 150 °C Maximum junction temperature
Thyst Over temperature hysteresis 10 °C
lc s

CLK Internal Clock for PWM 400 500 600 KHz Clock for internal PWM generation
am

Notes:
1, Accuracy at +100°C guaranteed by design and verified by laboratory characterization

2, If the temperature exceeds the over temperature limit, the PWM will be turned off. If the temperature
decreases, the PWM is activated again. The register settings are not reset.

Table 4 – Digital Input pins characteristics (SDI,VSYNC,HSYNC,SCL,CS)

Symbol Parameter Min Typ Max Unit Note

ca

VIH High Level Input voltage 1.3 VREG V

VIL Low Level Input voltage -0.3 0.4 V
ni

f_SCL Maximum SCL Frequency 10 MHz

Output driver is slew rate limited
f_HSYNC Maximum HSYNC Frequency 10 MHz
( Register: Curreg_Control 0x0D )
ch

SYNC-mode:
Vsync setup time before rising PWM values are updated with first
ts_VH 15 ns
edge of Hsync rising edge of Hsync while Vsync = 1
Te

( see [Link] )
Vsync hold time after rising edge
th_VH 15 ns
of Hsync
ts_SCISCL Setup time SDI,SCL 15 ns SPI interface mode
th_SCLSCI Hold time SCL,SDI 15 ns SPI interface mode
ts_CSSCL Setup time CS,SCL 15 ns SPI interface mode

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AS3693B austriamicrosystems

Symbol Parameter Min Typ Max Unit Note

th_SCLCS Hold time SCL, CS 15 ns SPI interface mode
Bus free time between
tBUF 1.3 us I2C interface mode
Stop and Start conditions
Setup time for repeated
Tsetupstart 100 ns I2C interface mode
Start condition
Hold time for repeated
Tholdstart 160 ns I2C interface mode
Start condition
Setup time for

id
Tsetupstop 160 ns I2C interface mode
Stop condition

al
Table 5 – Digital output pins characteristics (SDO)

Symbol Parameter Min Typ Max Unit Note

lv
VOH High Level Output voltage 2.4 2.5 V
VOL Low Level Output voltage -0.3 0.4 V

il
st
te G
on A
nt
lc s
ca am
ni
ch
Te

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AS3693B austriamicrosystems

6 Typical Operation Characteristics

6.1 Output current vs Output Voltage

0,16

0,14

id
0,12

0,1

al
150mA
0,08 75mA
25mA

lv
0,06

0,04

il
0,02

st
0
te G
0 5 10 15 20 25
on A
nt
lc s

6.2 Vsupply vs VREG and V2.5 at startup

ca am
ni
ch

Channel 1 = VREG
Channel 2 = V2_5
Te

Channel3 = Vsupply

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AS3693B austriamicrosystems

6.3 9us Slew Rate

id
al
il lv
st
te G
on A
trr
Channel 1 = Voltage on Current Source
nt Channel 2 + Voltage on RES Pin
lc s

6.4 Supply Regulation

ca am
ni
ch
Te

Channel 1 = DCDC VOUT (30V)

Channel 2 = Voltage on RES Pin
Channel 3 = Voltage on Curr Pin

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AS3693B austriamicrosystems

7 Block Description

7.1 Feedback Circuit

The AS3693B supports a flexible feedback selection for external DCDC – supplies. Beside the default setup for
RGGB lighting, each channel can be assigned to an external DCDC feedback loop. This feedback circuit is
important to reduce power dissipation of the device.

Table 6 – Feedback Control

Addr: 04h Feedback control

id
Enables and Disables the Different Feedback modes
Bit Bit Name Default Access Description
1 = Feedback Circuit is active

al
0 Feedback on 1 R/W
0 = The entire Feedback Loop is disabled
1 Feedback on PWM 0 R/W 0 = The Feedback Regulator is always active
1 = The Feedback Regulator is only active, if PWM = 1

lv
Enables open Led Detection Comparators
2 Open_Led_Det_on 0 R/W 0 = Open Led Detection Disabled
1 = Open Led Detection Enabled, Level: Ucurrx = 50mV
Enables Short detection

il
3 Short_det_on 0 R/W 0 = Short detection off
1 = Sort detection on.

st
5:4
Short Led Detect
Voltage(VSL)
te G R/W
Short led Detection Trip Voltage ( debounced 3mS )
00 = 2V
01 = 3V
on A
Trip Point voltage of the DCDC-Feedback Regulation
nt Circuit. (NOTE: This value has to be adjusted if Analog
DCDC_Regulation_tri Ref select Bit is changed.)
7:6 00 R/W
lc s

00 = 0.5V (Note use for Currents up to 70 mA)

p Point (VC)
01 = 0.6V (Note use for Currents up to 80 mA)
10 = 0.8V (Note use for Currents up to 110 mA)
am

11 = 1.0V (Note use for Currents up to 150 mA)

ca
ni
ch
Te

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AS3693B austriamicrosystems

7.1.1 Feedback Selection

In the AS3693B, each led – string feedback can be assigned to the specific led-supply, to minimize the power
consumption in the system. It can be chosen in between FBR, FBG and FBB.
DCDC Converter
for VDD
From main (Internal or externa)l
supply
R1
R3
Voltage Feedback Vfb
input for DCDC
R2 C1

id
Feedback resistor divider
(part of DCDC converter circuit)

al
AS3693B

ANALOG REGULATION
CIRCUIT

lv
16 REGULATORS

3...16
2
1 FB R

il
FB G
FB B
NOFB

st
te G VC

SHORTLED
on A
VSL
nt
OPENLED
VOL REF
lc s

R5
am

Table 7 – Feedback Selection

Addr: 05h,06h,07h,08h Feedback Select 1-4
This register controls the Feedback of the Automatic feedback loop
Bit Bit Name Default Access Description
ca

Selects the feedback of the voltage regulators

FB1_Select
00= regulator on FBR
FB5_Select
1:0 00 R/W 01= regulator on FBG
FB9_Select
10= regulator on FBB
FB13_Select
ni

11= regulator not connected to FB

Selects the feedback of the voltage regulators
FB2_Select
00= regulator on FBR
FB6_Select
ch

3:2 01 R/W 01= regulator on FBG

FB10_Select
10= regulator on FBB
FB14_Select
11= regulator not connected to FB
Selects the feedback of the voltage regulators
FB3_Select
00= regulator on FBR
Te

FB7_Select
5:4 01 R/W 01= regulator on FBG
FB11_Select
10= regulator on FBB
FB15_Select
11= regulator not connected to FB
Selects the feedback of the voltage regulators
FB4_Select
00= regulator on FBR
FB8_Select
7:6 10 R/W 01= regulator on FBG
FB12_Select
10= regulator on FBB
FB16_Select
11= regulator not connected to FB

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AS3693B austriamicrosystems

7.1.2 Voltage fault registers

In this registers an open or short led fault can be detected. If an open or short led error occurs, pin fault is pulled
to 0 (3 ms debounced ).
Remark: At 100% PWM duty cycle, short led fault detection is not available. Please set PWM to 99% duty cycle.
Open led fault detection is available at 100% PWM duty cycle.

Table 8 – Fault Registers

Addr: 09h-0ch Voltage Fault 1,2,3,4

This register shows a fault on any led string
Bit Bit Name Default Access Description

id
Fault_Reg 1 Shows a error on any led string
1:0 Fault_Reg 5 00 R 00 = no fault
Fault_Reg 9 01 = open led

al
Fault_Reg 13 10 = short led
Fault_Reg 2 Shows a error on any led string

lv
Fault_Reg 6 00 = no fault
3:2 00 R
Fault_Reg 10 01 = open led
Fault_Reg 14 10 = short led
Fault_Reg 3 Shows a error on any led string

il
Fault_Reg 7 00 = no fault
5:4 00 R
Fault_Reg 11 01 = open led

st
Fault_Reg 15
Fault_Reg 4
te G 10 = short led
Shows a error on any Led string
Fault_Reg 8 00 = no Fault
on A
7:6 00 R
Fault_Reg 12 01 = open Led
Fault_Reg 16
nt 10 = short Led
lc s

7.2 Curreg 1-16

am

Each current source can be turned on and off separately.

Table 9 –Reg. Control 1

Addr: 01h Reg. Control1

This register enables or disables the curreg 1 - 8
Bit Bit Name Default Access Description
00000000

Enables or disables the current regulators

ca

7:0 Curreg 1-8_ON R/W 0 = regulator off

1 = regulator on
ni
ch

Table 10– [Link] 2

Addr: 02h Reg. Control2

This Register enables or disables the curreg 9-16
Te

Bit Bit Name Default Access Description

00000000

Enables or disables the current regulators

7:0 Curreg 9 -16_ON R/W 0 = regulator off
1 = regulator on

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AS3693B austriamicrosystems

Table 11 –CURREG_CONTROL
Addr: 0dh Curreg Control
Controls Rise, Fall times and References of the Curreg.
Bit Bit Name Default Access Description
Voltage reference for the current regulators can be
chosen with these options.
00 = 250mV reference
1:0 Analog Ref Select 00 R/W
01 = external reference

id
10 = DAC reference
11 = do not use
SLEW – RATE – Control. Adjusts the rise and fall time of

al
the current switching
SLEW_RATE_CONT 00 = typ. 9us
3:2
ROL
00 R/W
01 = typ. 6us
10 = typ. 3us

lv
11 = typ. 1us
Note: Test bits for internal use only
5:4 PWM_LOW_LEVEL 00 R/W
Gives +30% current.

il
7 boost mode 0 R/W
only available in internal reference mode.

st
te G
on A
nt
lc s

AS3693B
am

Reference Sources

Analog Ref Select 3-16

0,5% VREF 250mV 2
1
PWM
8Bit DAC
0...500mV

External Reference
Curreg
ca
ni

Table 12 – Ref_DAC_Voltage
Addr: 0eh Ref_DAC_Voltage
The Regulation Voltage can be chosen in this register
ch

Bit Bit Name Default Access Description

Reference voltage for current regulators. (Note: If Analog
Ref Select = 10, the regulation voltage can be adjusted
Te

here.
00000000 = 0mV
7…0 Ref_DAC_Voltage 00 R/W 00000001
…
01111111 = 250 mV
..
11111111= 500mV

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AS3693B austriamicrosystems

7.3 PWM – modes

Table 14– PWM CONTROL

Addr: 0fh PWM_MODE

Controls the different PWM modes and Internal or external PWM
Bit Bit Name Default Access Description
00 Sync mode

id
01 Async - mode
1:0 01 R/W
10 not used
PWM_MODE
11 not used

al
NOTE: Sync mode can only be used with
PWM INT = 0.
2 1 R/W 0 PWM generator uses external H and Vsync clock

lv
PWM INT/EXT
1 PWM generator uses internal 500kHz clock.
3 0 R/W 0 VSYNC active high (PWM triggers on rising edge)
VSYNC_INVERT
1 VSYNC active low (PWM triggers on falling edge)
0 PWM normal (PWM starts with “1” after delay)

il
4 PWMINVERT 0 R/W
1 PWM inverted(PWM starts with “0” after delay)

st
Note: If Vsync or Hsync is not used, connect it to GND.
te G
on A
7.3.1 SYNC mode (PWM_MODE = 00)
nt
In this mode the PWM is synchronized with VSYNC and HSYNC.
lc s

Reg: N
am

Reset
Vsync Delay
Or
R
Reg: P
Hsync Counter
Compare

Compare PWM

Reg: M
PWMINVERT( Register 0x0F )
ca

Setup options:
ni

Delay (N) = registers 0h32 to 0h51

High Time (M) = registers 0h12 to 0h31
PWM Period (P) = register 0h10
ch
Te

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AS3693B austriamicrosystems

P WM duration = t vsync

V sync

Hs ync

P WM Delay =N * t hsync
Reset

P*t > t
hsync vsync P WM
reset with Vsync P WM s ignal: High time = M * t hsync

P WM P eriode = t vsyunc

id
P*t < t

al
hsync vsync
P WM
Repetitive PWM P WM s ignal: High time = M * t hsync

reset with P * t Restart

hsync P WM P eriode = P * t hsync

lv
Example: Two PWM output channels with fixed delays and variable high times (HT)
PWMINVERT = 0

il
st
te G
on A
nt
lc s

PWMINVERT = 1
am

[Link] SYNC – mode PWM – generator update cycle.

ca

-Store new values from serial interface

-Update delay immediately
ni

-no new data -new data

ch

VSYNC Update HighTime, Period

Delayed
Te

VSYNC
(internal)

PWM

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AS3693B austriamicrosystems

Shift new data Restart PWM

in PWM – State
maschine
VSYNC

HSYNC

id
al
7.3.2 ASYNC – mode (PWM_MODE = 01)

lv
This PWM is synchronized with Hsync or internal 500KHz clock. The registers are updated with each serial data.

Reset

il
Vsync

st
te G R
Reg: P
Hsync Counter
Compare
on A
nt Compare PWM

Reg: M
lc s

PWMINVERT( Register 0x0F )

am

High time (M) = registers 0h12 to 0h 31

PWM period (P) = register 0h10

Hs ync

AsyncMode
Repetitive PWM
no Reset
Syncronized on Hsync or
ca

P WM
internal P WM s ignal: High time = M * t hsync

Clock P WM P eriode = P * t hsync

ni
ch
Te

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AS3693B austriamicrosystems

7.4 PWM – high time, period and delay registers

Table 15 – Curreg1-16_DELAY_LSB

Addr: 32h – 50h CURREGX_DELAY_LSB

Defines delay of the different PWM’s
Bit Bit Name Default Access Description

00000000

id
7:0 CurregX_DELAY_LSB R/W Defines the delay time of the PWM

al
Table 16 – Curreg1-16_DELAY_MSB

lv
Addr: 32h-51h CURREGX_DELAY_LSB
Defines delay of the different PWM’s

il
Bit Bit Name Default Access Description

3:0 CurregX_DELAY_MSB 0000 R/W Defines the delay time of the PWM

st
te G
Table 17– PWM_PERIOD_LSB
on A
Addr: 10h PWM – Period – LSB
nt Defines PWM – Periode
lc s

Bit Bit Name Default Access Description

am 11111111

7:0 PWM_PERIOD_LSB R/W Defines the period of the PWM

Table 18– PWM_PERIOD_MSB

Addr: 11h PWM – Period – MSB
Defines PWM – Periode
ca

Bit Bit Name Default Access Description

3:0 PWM_PERIOD_MSB 0000 R/W Defines the period of the PWM

ni

Table 19– Curreg1-16_HT_LSB

ch

Addr: 12h-30h CURREGX_HT_LSB

Defines High Time of PWM
Bit Bit Name Default Access Description
Te

7:0 Curreg1_HT_LSB 0 R/W Defines PWM high time

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AS3693B austriamicrosystems

Table 20– Curreg1-16_HT_MSB

Addr: 13h-31h CURREGX_HT_MSB

Defines High Time of PWM
Bit Bit Name Default Access Description

3:0 Curreg1_HT_MSB 0000 R/W Defines PWM high time

7.5 Shunt Regulator

id
The supply of the AS3693B is generated from the high voltage supply. To obtain a 5V regulated supply, a series
resistor Rvdd is used together with an internal zener diode (ZD1). An external capacitor Cvdd is used to filter the
supply on the pin VREG.

al
The external resistor Rvdd has to be choosen according to the following formula:

lv
VDDMIN − 5,4V VDDMIN is the minimum voltage of the
Rvdd = supply, where Rvdd is connected
20mA

il
This ensures enough supply current (IVREGMAX) for the AS3693B under minimum supply voltage VDDMIN.

st
If a stable 5V supply within the operating conditions limits of VREGEXT is already existing in the system it is
te G
possible to supply the AS3693B directly. In this case remove the resistor Rvdd and connected this supply
directly to VREG.
on A
7.5.1 Undervoltage lockout
nt
The undervoltage lockout is an additional safety feature to prevent LED-current under abnormal Vreg conditions.
lc s

If the supply voltage Vreg is below 2.7V (e.g. device is supplied only by the voltage of the serial interface ) the
registers Reg.Control1 and RegControl2 (0x01 and 0x02) are reset. This turns off all current sinks.
am

Vreg 3V to 5.4V

Reset
Register 0x01
2.7V
Reset
Register 0x02
ca
ni

7.6 Over temperature control

ch

Table 14– Overtemp Control

Addr:55h Over temperature Control
Controls the temperature functions
Te

Bit Bit Name Default Access Description

Enables the over temperature protection
0 overtemp_on 1 R/W 0 = Protection off
1 = Protection on
Displays temperature status
1 ov_temp 0 R/W 0 = Normal operation
1 = Over temperature shutdown

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AS3693B austriamicrosystems

7.7 Device address setup

The I2C and SPI – Device address can be set via PIN ADDR1 and ADDR2. The AS3693B offers 31 I2C or 32
SPI addresses, which can be set via external resistor. ADDR2 bit 2 decides if I2C or SPI interface is used.

AS3693
Flexible 6- Bit Address Programming
with 2 external resistors.

Digital
Digital Registers
PWM - Generator

id
6 Bit I2C ADDRESS

al
ADC

lv
ADDR1 ADDR2

R1 R2

il
st
Table 13– Device Address

Device Adress Setup:

te G I2C ADDRESS
on A
nt I2C ADDRESS Options
Bit Bit Name Default Access Description
Lower 3 bits of device address
lc s

000 open Note: don’t use address 00h

001 320kΩ
am

010 160kΩ
2:0 Device ADDR1 000 R 011 80kΩ
100 40kΩ
101 20kΩ
110 10kΩ
111 0Ω
Upper 3 bits of device address
000 open Note: activates I2C - mode
001 320kΩ Note: activates I2C - mode
010 160kΩ Note: activates I2C - mode
ca

5:3 Device ADDR2 000 R 011 80kΩ Note: activates I2C - mode
100 40kΩ Note: activates SPI - mode
101 20kΩ Note: activates SPI - mode
110 10kΩ Note: activates SPI - mode
ni

111 0Ω Note: activates SPI – mode

ch

7.7.1 I2C Device Address setup

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

Te

0 0 (ADDR2<2>) ADDR2<1> ADDR2<0> ADDR1<2> ADDR1<1> ADDR1<0> R/W

7.7.2 SPI Device Address setup

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0 0 1 (ADDR2<2>) ADDR2<1> ADDR2<0> ADDR1<2> ADDR1<1> ADDR1<0>

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AS3693B austriamicrosystems

7.8 Digital interface

The AS3693B can be controlled with two types of interfaces.

7.8.1 I2C interface

[Link] Feature List

• Fast-mode capability (max. SCL-frequency is 400 kHz)
• Write formats: Single-Byte-Write, Page-Write

id
• Read formats: Current-Address-Read, Random-Read, Sequential-Read
• SDA input delay and SCL spike filtering by integrated RC-components

al
[Link] Transfer Formats
2
Figure 1 – I C Byte-Write:

lv
S START condition after STOP
S DW A WA A reg_data A P Sr repeated START
DW device address for write
DR device address for read

il
WA word address
write register,
A acknowledge
WA++
N no acknowledge

st
te G P
white field
grey field
WA++
stop condition
slave as receiver
slave as transmitter
increment word address internally
on A
nt
2
Figure 2 – I C Page-Write:
lc s

S DW A WA A reg_data 1 A reg_data 2 A … reg_data n A P

am

write register write register write register

WA++ WA++ WA++

Byte-Write and Page-Write are used to write data to the slave.

The transmission begins with the START condition, which is generated by the master when the bus is in IDLE
state (the bus is free). The device-write address is followed by the word address. After the word address any
number of data bytes can be send to the slave. The word address is incremented internally, in order to write
subsequent data bytes on subsequent address locations.

For reading data from the slave device, the master has to change the transfer direction. This can be done either
ca

with a repeated START condition followed by the device-read address, or simply with a new transmission START
followed by the device-read address, when the bus is in IDLE state. The device-read address is always followed
st
by the 1 register byte transmitted from the slave. In Read-Mode any number of subsequent register bytes can
be read from the slave. The word address is incremented internally.
ni

The diagrams below show various read formats available:

ch

2
Figure 3 – I C Random-Read:

S DW A WA A Sr DR A data N P
Te

read register WA++

WA++

Random-Read and Sequential-Read are combined formats. The repeated START condition is used to change
the direction after the data transfer from the master.
The word address transfer is initiated with a START condition issued by the master while the bus is idle. The
START condition is followed by the device-write address and the word address.

[Link] Revision 1.21 / 2011-09-30 20 - 32

AS3693B austriamicrosystems

st
In order to change the data direction a repeated START condition is issued on the 1 SCL pulse after the
acknowledge bit of the word address transfer. After the reception of the device-read address, the slave becomes
the transmitter. In this state the slave transmits register data located by the previous received word address
vector. The master responds to the data byte with a not-acknowledge, and issues a STOP condition on the bus.
2
Figure 4 – I C Sequential-Read:

S DW A WA A Sr DR A data 1 A data 2

id
… A data n N P

al
read register WA++
WA++

Sequential-Read is the extended form of Random-Read, as more than one register-data bytes are transferred

lv
subsequently. In difference to the Random-Read, for a sequential read the transferred register-data bytes are
responded by an acknowledge from the master. The number of data bytes transferred in one sequence is
unlimited (consider the behavior of the word-address counter). To terminate the transmission the master has to
send a not-acknowledge following the last data byte and generate the STOP condition subsequently.

il
2
Figure 5 – I C Current-Address-Read:

st
S DR A
te G data 1 A data 2 … A data n N P
on A
read register read register read register WA++
nt
WA++ WA++ WA++
lc s

To keep the access time as small as possible, this format allows a read access without the word address transfer
am

in advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device-
Read address. Analogous to Random-Read, a single byte transfer is terminated with a not-acknowledge after the
st
1 register byte. Analogous to Sequential-Read an unlimited number of data bytes can be transferred, where the
data bytes has to be responded with an acknowledge from the master. For termination of the transmission the
master sends a not-acknowledge following the last data byte and a subsequent STOP condition.
ca
ni
ch
Te

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AS3693B austriamicrosystems

7.8.2 SPI interface

SPI – Interface Pins

OUTPUT
Digital
SDI
Control -Registers FAULT
SCL PWM - Generator
SDO
CS
VSYNC

id
HSYNC

al
ADDR1 ADDR2

lv
SPI Mode – Digital Interface Pins:
CS(N) Chip Select input
SDO Serial Data output
SDI Serial Data input

il
SCL Serial Clock input
VSYNC Video Sync signal input

st
HSYNC
ADDR1
te G
Video Sync signal input
Device Address pins (can be
ADDR2 set via resistor).
on A
nt
lc s

[Link] Read Sequence

am

CS1

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK

8 Bit Device Address 7 Bit Register Address R/W

SDI
7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 1
(SDA)

Data Out
High Impedance
SDO 7 6 5 4 3 2 1 0
ca

[Link] Page Read Sequence

ni
ch
Te

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AS3693B austriamicrosystems

[Link] Write Sequence

CS1 TWC
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

SCL
8 Bit Device Address 7 Bit Address R/W Data Byte
SDI 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 0 7 6 5 4 3 2 1 0
(SDA)

High Impedance
SDO

id
al
[Link] Page Write Sequence

lv
CS1

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

il
SCK

8 Bit Device Address 7 Bit Register Address R/W Data Byte 1

st
SDI
(SDA)
7 6 5
te G 4 3 2 1 0 6 5 4 3 2 1 0 0 7 6 5 4 3 2 1 0
on A
CS1

24 25 26
nt 27 28 29 30 31 32 33 34 35 36 37 38 39
lc s

SCK
Data Byte 2 Data Byte 3 Data Byte n (32 max)
am

SD
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
(SDA)
ca
ni
ch
Te

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 AS3693B austriamicrosystems

8 Register map

Name Def
Addr B7 b6 b5 B4 b3 b2 b1 b0
ault
Curreg Curreg7 Curreg6 Curreg5 Curreg4 Curreg Curreg Curreg1
Reg. Control1 01h 00h
8_ON _ON _ON _ON _ON 3_ON 2_ON _ON
Curreg Curreg1 Curreg1 Curreg1 Curreg1 Curreg Curreg Curreg9
Reg Control 2 02h 00h
16_ON 5_ON 4_ON 3_ON 2_ON 11_ON 10_ON _ON

id
OPEN_
SHORT Feedba FEEDB
DCDC_REGULATI Short_Led Detect LED
Feedback Control 04h 01h _DET_ ck_on_ ACK_O

al
ON_TRIP_POINT Voltage _DET
ON PWM N
_ON
Fedback Select 1 05h 94h FB4_ Select FB3_ Select FB2_ Select FB1_Select

lv
Fedback Select 2 06h 94h FB8_ Select FB7_ Select FB6_ Select FB5_ Select
Fedback Select 3 07h 94h FB12_ Select FB11_ Select FB10_ Select FB9_ Select
Fedback Select 4 08h 94h FB16_ Select FB15_ Select FB14_ Select FB13_ Select

il
Voltage_Fault 1 09h 00h Fault_Reg4 Fault_Reg3 Fault_Reg2 Fault_Reg1

st
Voltage_Fault 2
Voltage_Fault 3
0Ah
0Bh
te G
00h
00h
Fault_Reg8
Fault_Reg12
Fault_Reg7
Fault_Reg11
Fault_Reg6
Fault_Reg10
Fault_Reg5
Fault_Reg9
on A
Voltage_Fault 4 0Ch 00h
nt Fault_Reg16 Fault_Reg15 Fault_Reg14 Fault_Reg13
switch_
CURREG_CONTR boost PWM_LOW_LEVE
0Dh 00h output_ RC_SEL Select Ref
OL mode L
driver
lc s

Ref_DAC_Voltage 0Eh 00h Vref_DAC

am

PWM VSYNC PWM-

PWM –CONTROL 0Fh 04h INVER _INVER INT/EX PWM - MODE
T T T
PWM-
10h FFh PWM –PERIOD - LSB
PERIOD_LSB
PWM-PERIOD-
11h 00h PWM – period - MSB
MSB
Curreg1_HT_LSB 12h 00h Curreg1_HT_LSB
Curreg1_HT_MSB 13h 00h Curreg1_HT_MSB
ca

Curreg2_HT_LSB 14h 00h Curreg2_HT_LSB

Curreg2_HT_MSB 15h 00h Curreg2_HT_MSB
ni

Curreg3_HT_LSB 16h 00h Curreg3_HT_LSB

Curreg3_HT_MSB 17h 00h Curreg3_HT_ MSB
Curreg4_HT_LSB 18h 00h Curreg4_HT_LSB
ch

Curreg4_HT_MSB 19h 00h Curreg4_HT_ MSB

Curreg5_HT_LSB 1Ah 00h Curreg5_HT_LSB
Curreg5_HT_MSB 1Bh 00h Curreg5_HT_ MSB
Te

Curreg6_HT_LSB 1Ch 00h Curreg6_HT_LSB

Curreg6_HT_MSB 1Dh 00h Curreg6_HT_ MSB
Curreg7_HT_LSB 1Eh 00h Curreg7_HT_LSB
Curreg7_HT_MSB 1Fh 00h Curreg7_HT_ MSB
Curreg8_HT_LSB 20h 00h Curreg8_HT_LSB

[Link] Revision 1.21 / 2011-09-30 24 - 32

 AS3693B austriamicrosystems

Name Def
Addr B7 b6 b5 B4 b3 b2 b1 b0
ault
Curreg8_HT_MSB 21h 00h Curreg8_HT_ MSB
Curreg9_HT_LSB 22h 00h Curreg9_HT_LSB
Curreg9_HT_MSB 23h 00h Curreg9_HT_ MSB
Curreg10_HT_LSB 24h 00h Curreg10_HT_LSB
Curreg10_HT_MSB 25h 00h Curreg10_HT_ MSB
Curreg11_HT_LSB 26h 00h Curreg11_HT_LSB
Curreg11_HT_MSB 27h 00h Curreg11_HT_ MSB

id
Curreg12_HT_LSB 28h 00h Curreg12_HT_LSB
Curreg12_HT_MSB 29h 00h Curreg12_HT_MSB

al
Curreg13_HT_LSB 2Ah 00h Curreg13_HT_LSB
Curreg13_HT_MSB 2Bh 00h Curreg13_HT_MSB

lv
Curreg14_HT_LSB 2Ch 00h Curreg14_HT_LSB
Curreg14_HT_MSB 2Dh 00h Curreg14_HT_MSB
Curreg15_HT_LSB 2Eh 00h Curreg15_HT_LSB

il
Curreg15_HT_MSB 2Fh 00h Curreg15_HT_MSB
Curreg16_HT_LSB 30h 00h Curreg16_HT_LSB

st
Curreg16_HT_MSB 31h
te G
00h Curreg16_HT_MSB
Curreg1_DELAY_L
on A
32h 00h Curreg1_DELAY_LSB
SB
Curreg1_ DELAY
33h
nt
00h Curreg1_DELAY_MSB
_MSB
lc s

Curreg2_ DELAY
34h 00h Curreg2_DELAY_LSB
_LSB
am

Curreg2_ DELAY
35h 00h Curreg2_DELAY_MSB
_MSB
Curreg3_ DELAY
36h 00h Curreg3_DELAY_LSB
_LSB
Curreg3_ DELAY
37h 00h Curreg3_DELAY_ MSB
_MSB
Curreg4_ DELAY
38h 00h Curreg4_DELAY_LSB
_LSB
Curreg4_ DELAY
ca

39h 00h Curreg4_DELAY_ MSB

_MSB
Curreg5_DELAY_L
3Ah 00h Curreg5_DELAY_LSB
SB
ni

Curreg5_DELAY_M
3Bh 00h Curreg5_DELAY_ MSB
SB
Curreg6_DELAY_L
ch

3Ch 00h Curreg6_DELAY_LSB

SB
Curreg6_DELAY_M
3Dh 00h Curreg6_DELAY_ MSB
SB
Te

Curreg7_DELAY_L
3Eh 00h Curreg7_DELAY_LSB
SB
Curreg7_DELAY_M
3Fh 00h Curreg7_DELAY_ MSB
SB
Curreg8_DELAY_L
40h 00h Curreg8_DELAY_LSB
SB

[Link] Revision 1.21 / 2011-09-30 25 - 32

 AS3693B austriamicrosystems

Name Def
Addr B7 b6 b5 B4 b3 b2 b1 b0
ault
Curreg8_DELAY_M
41h 00h Curreg8_DELAY_ MSB
SB
Curreg9_DELAY_L
42h 00h Curreg9_DELAY_LSB
SB
Curreg9_DELAY_M
43h 00h Curreg9_DELAY_ MSB
SB
Curreg10_DELAY_
44h 00h Curreg10_DELAY_LSB
LSB

id
Curreg10_DELAY_
45h 00h Curreg10_DELAY_ MSB
MSB
Curreg11_DELAY_

al
46h 00h Curreg11_DELAY_LSB
LSB
Curreg11_DELAY_
47h 00h Curreg11_DELAY_ MSB
MSB

lv
Curreg12_DELAY_
48h 00h Curreg12_DELAY_LSB
LSB
Curreg12_DELAY_

il
49h 00h Curreg12_DELAY_MSB
MSB

st
Curreg13_DELAY_ te G
4Ah 00h Curreg13_DELAY_LSB
LSB
Curreg13_DELAY_
4Bh 00h Curreg13_DELAY_MSB
on A
MSB
Curreg14_DELAY_
4Ch 00h
nt Curreg14_DELAY_LSB
LSB
lc s

Curreg14_DELAY_
4Dh 00h Curreg14_DELAY_MSB
MSB
am

Curreg15_DELAY_
4Eh 00h Curreg15_DELAY_LSB
LSB
Curreg15_DELAY_
4Fh 00h Curreg15_DELAY_MSB
MSB
Curreg16_DELAY_
50h 00h Curreg16_DELAY_LSB
LSB
Curreg16_DELAY_
51h 00h Curreg16_DELAY_LSB
MSB
ov_temp
ca

Overtemp control 55h 01h ov_temp

_on
ASIC ID1 5Ch CAh 1 1 0 0 1 0 1 0
ASIC ID2 5Dh 5Xh 0 1 0 1 REVISION
ni

Revision code:
0x8… initial version November 2008
ch
Te

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AS3693B austriamicrosystems

9 Pinout and Packaging

9.1 Pinout
Table 5 – Pinlist

Pin Name Type Description

1 GATE16 AIO Connect to Gate of External Transistor

id
2 RFB1 AIO Connect to Source of External Transistor and to Resistor RSET
3 GATE1 AIO Connect to Gate of External Transistor

al
4 CURR_sense1 AIO Connect to Drain of external Transistor (input for Open and Short led detection)
Automatic supply regulation for GREEN led strings; if not
5 FBG AIO

lv
used, leave open
Automatic supply regulation for BLUE led strings; if not
6 FBB AIO
used, leave open
7 REF(EXT) AI Reference pin for PWM = 1 voltage, if not used leave open

il
8 GND(SENSE) AIO GND supply connection (sense)

st
9 VREG AIO
te G
Shunt regulator supply; connect to Rvdd and
Cvdd
10 V2_5 AIO Digital supply, connect 1uF blocking capacitor
on A
11 ADDR2 AIO Connect to external resistor for serial interface address selection,
12 ADDR1 AIO
nt
Connect to external resistor for serial interface address selection.
lc s

13 CURR_sense2 AIO Connect to Drain of external Transistor (input for Open and Short led detection)
14 GATE2 AIO Connect to Gate of External Transistor
am

15 RFB2 AIO Connect to Source of External Transistor and to Resistor RSET

16 GATE3 AIO Connect to Gate of External Transistor
17 RFB3 AIO Connect to Source of External Transistor and to Resistor RSET
18 CURR_sense3 AIO Connect to Drain of external Transistor (input for Open and Short led detection)
19 GATE4 AIO Connect to Gate of External Transistor
20 RFB4 AIO Connect to Source of External Transistor and to Resistor RSET
21 CURR_sense4 AIO Connect to Drain of external Transistor (input for Open and Short led detection)
ca

22 GATE5 AIO Connect to Gate of External Transistor

23 RFB5 AIO Connect to Source of External Transistor and to Resistor RSET
24 CURR_sense5 AIO Connect to Drain of external Transistor (input for Open and Short led detection)
ni

25 CURR_sense6 AIO Connect to Drain of external Transistor (input for Open and Short led detection)
26 RFB6 AIO Connect to Source of External Transistor and to Resistor RSET
ch

27 GATE6 AIO Connect to Gate of External Transistor

28 CURR_sense7 AIO Connect to Drain of external Transistor (input for Open and Short led detection)
29 RFB7 AIO Connect to Source of External Transistor and to Resistor RSET
Te

30 GATE7 AIO Connect to Gate of External Transistor

31 CURR_sense8 AIO Connect to Drain of external Transistor (input for Open and Short led detection)
32 RFB8 AIO Connect to Source of External Transistor and to Resistor RSET
33 GATE8 AIO Connect to Gate of External Transistor
34 RFB9 AIO Connect to Source of External Transistor and to Resistor RSET
35 GATE9 AIO Connect to Gate of External Transistor

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AS3693B austriamicrosystems

Table 5 – Pinlist

Pin Name Type Description

36 CURR_sense9 AIO Connect to Drain of external Transistor (input for Open and Short led detection)
Automatic supply regulation for RED led strings; if not
37 FBR AIO
used, leave open
38 VSYNC DI Video sync signal , NOTE: Connect to GND in ASYNC MODE
39 HSYNC DI Video sync signal or external clock input in ASYNC mode

40 CS DI SPI : CS – function, I2C: connect to GND

id
41 SCL DI SPI/ I2C: Serial interface clock input.
42 SDA DI SPI/ I2C: Serial interface data I/O.

al
43 SDO DO SPI: digital data output, I2C: leave open
44 FAULT DO FAULT PIN, open drain output. Connect pull up resistor to V2_5

lv
45 CURR_sense10 AIO Connect to Drain of external Transistor (input for Open and Short led detection)
46 GATE10 AIO Connect to Gate of External Transistor
47 RFB10 AIO Connect to Source of External Transistor and to Resistor RSET

il
48 GATE11 AIO Connect to Gate of External Transistor

st
49
50
RFB11
CURR_sense11
AIO
AIO
te G
Connect to Source of External Transistor and to Resistor RSET
Connect to Drain of external Transistor (input for Open and Short led detection)
on A
51 GATE12 AIO Connect to Gate of External Transistor
nt
52 RFB12 AIO Connect to Source of External Transistor and to Resistor RSET
53 CURR_sense12 AIO Connect to Drain of external Transistor (input for Open and Short led detection)
lc s

54 GATE13 AIO Connect to Gate of External Transistor

am

55 RFB13 AIO Connect to Source of External Transistor and to Resistor RSET

56 CURR_sense13 AIO Connect to Drain of external Transistor (input for Open and Short led detection)
57 CURR_sense14 AIO Connect to Drain of external Transistor (input for Open and Short led detection)
58 RFB14 AIO Connect to Source of External Transistor and to Resistor RSET
59 GATE14 AIO Connect to Gate of External Transistor
60 CURR_sense15 AIO Connect to Drain of external Transistor (input for Open and Short led detection)
61 RFB15 AIO Connect to Source of External Transistor and to Resistor RSET
62 GATE15 AIO Connect to Gate of External Transistor
ca

63 CURR_sense16 AIO Connect to Drain of external Transistor (input for Open and Short led detection)
64 RFB16 AIO Connect to Source of External Transistor and to Resistor RSET
65 VSS Supply connection; add as many vias to
ni

GND S
(EP) ground plane as possible.

AIO…Analog pin
ch

DI…Digital input. Protected with clamp to 2.5V

DO…Digital output. Protected with clamp to 2.5V
S… VSS supply
Te

Note: Connect any unused output channel as follows:

- GATEx = open, RFbx = CURR_senseX = GND

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AS3693B austriamicrosystems

9.2 Package drawing epTQFP64

id
al
il lv
st
te G
on A
nt
lc s
ca am
ni
ch
Te

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AS3693B austriamicrosystems

9.3 Package drawing QFN64

id
al
il lv
st
te G
on A
nt
lc s
ca am
ni
ch
Te

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AS3693B austriamicrosystems

10 Ordering Information

Table 6 – Ordering Information

Part Number Marking Package Type Delivery Form Description

Tape and Reel Package size = 10x10mm, Exposed pad
AS3693B-ZTQT AS3693B epTQFP64 in Dry Pack size = 4.5x4.5mm, Pitch = 0.5mm, Pb-free;
Tape and Reel Package size = 9x9mm, Pitch = 0.5mm,
AS3693B-ZQFT AS3693B QFN64 in Dry Pack Pb-free;

id
Tape and Reel Package size = 9x9mm, Pitch = 0.5mm,
AS3693B-ZMFT AS3693B MLF64 in Dry Pack Pb-free;

al
il lv
st
te G
on A
nt
lc s
ca am
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ch
Te

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AS3693B austriamicrosystems

Copyright
Copyright © 1997-2006, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-
Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted,
merged, translated, stored, or used without the prior written consent of the copyright owner.

All products and companies mentioned are trademarks of their respective companies.

id
Disclaimer

al
Devices sold by austriamicrosystems AG are covered by the warranty and patent identification provisions
appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by
description regarding the information set forth herein or regarding the freedom of the described devices from
patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time

lv
and without notice. Therefore, prior to designing this product into a system, it is necessary to check with
austriamicrosystems AG for current information. This product is intended for use in normal commercial
applications. Applications requiring extended temperature range, unusual environmental requirements, or high
reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not

il
recommended without additional processing by austriamicrosystems AG for each application.

st
te G
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However,
austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not
limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect,
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special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing,
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performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise
or flow out of austriamicrosystems AG rendering of technical or other services.
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Contact Information
Headquarters:

austriamicrosystems AG
Business Unit Communications
A 8141 Schloss Premstätten, Austria
T. +43 (0) 3136 500 0
F. +43 (0) 3136 5692
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info@[Link]

For Sales Offices, Distributors and Representatives, please visit:

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