Computer Organization

and Architecture
(EET 2211)
 Chapter 3
A Top-Level View of Computer Function and
Interconnection

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Learning Objectives:
After studying this chapter, you should be able to:
• Understand the basic elements of an instruction cycle and the role of
interrupts.
• Describe the concept of interconnection within a computer system.
• Assess the relative advantages of point-to-point interconnection
compared to bus interconnection.
• Present an overview of QPI.
• Present an overview of PCIe.

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Introduction:
• At a top level, a computer consists of CPU (central processing unit),
memory, and I/O components.

• At a top level, we can characterize a computer system by describing :

(1) the external behavior of each component, that is, the data and
control signals that it exchanges with other components, and

(2) the interconnection structure and the controls required to manage

the use of the interconnection structure.

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Contd.
• Top-level view of structure and function is important because it explains the
nature of a computer and also provides understanding about the
increasingly complex issues of performance evaluation.

• This chapter focuses on the basic structures used for computer component
interconnection.

• The chapter begins with a brief examination of the basic components and
their interface requirements.

• Then a functional overview is provided.

• Then the use of buses to interconnect system components has been

explained.
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3.1. Computer Components
All contemporary computer designs are based on the concepts of von
Neumann architecture. It is based on three key concepts:

• Data and instructions are stored in a single read–write memory.

• The contents of this memory are addressable by location, without

regard to the type of data contained there.

• Execution occurs in a sequential fashion (unless explicitly modified)

from one instruction to the next.

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Programming in hardware
Ø The fig.1 shows a customized hardware.
Ø The system accepts data and produces
results.
Ø If there is a particular computation to be
p e r fo r m e d , a c o n f i g u ra t i o n o f l o g i c
components designed specifically for that
computation could be constructed. Fig.1. Programming in H/W.

Ø However, a rewiring of the hardware is required if a different computation is

needed every time.

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Programming in software
• Instead of rewiring the hardware for each new
program, the programmer merely needs to
supply a new set of control signals.

• The fig.2 shows a general purpose hardware,

that will perform various functions on data
depending on control signals applied to the
hardware.

• The system accepts data and control signals

Fig.2. Programming in S/W.
and produces results.

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How to supply the control signals?
• The entire program is actually a sequence of steps. At each step,
some arithmetic or logical operation is performed on some data.
• For each step, a new set of control signals is needed. Provide a unique
code for each possible set of control signals and add to the general-
purpose hardware a segment that can accept a code and generate
control signals as shown in fig.2.
• Instead of rewiring the hardware for each new program, provide a
new sequence of codes.
• Each code is an instruction, and part of the hardware interprets each
instruction and generates control signals. To distinguish this new
method of programming, a sequence of codes or instructions is called
software.
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3.2 Computer Function
• The basic function performed by a computer is execution of a
program, which consists of a set of instructions stored in memory.
• The processor does the actual work by executing instructions
specified in the program.

• Instruction processing consists of two steps:

1. The processor reads (fetches) instructions from memory one at a
time and
2. Executes each instruction.
• Program execution consists of repeating the process of instruction
fetch and instruction execution. The instruction execution may involve
several operations and depends
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on the nature of the instruction
Computer Organization and Architecture 10
Computer Components: Top-Level View

Fig.3. Computer Components :

Top-Level View

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Main Memory:
• Figure 3 illustrates these top-level components and suggests the
interactions among them.
ØMemory, or main memory:
• An input device may fetch instructions and data sequentially. But the
execution of a program may not be sequential always; it may jump around.
• Similarly, operations on data may require access to more than just one
element at a time in a predetermined sequence. Thus, there must be a
place to temporarily store both instructions and data. That module is called
memory, or main memory.
• The term ‘main memory’ has been used to distinguish it from external
storage or peripheral devices.
• Von Neumann stated that the same memory could be used to store both
instructions and data.
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Central Processing Unit (CPU):
• The CPU exchanges data with memory by using two internal (to the
CPU) registers:
1. Memory Address Register (MAR): It specifies the address in
memory for the next read or write.
2. Memory Buffer Register (MBR): It contains the data to be written
into memory or receives the data read from memory.
• The CPU also contains:
• (I/O AR): It is an I/O address register which specifies a particular I/O
device.
• (I/OBR): It is an I/O buffer register which is used for the exchange of
data between an I/O module and the CPU.
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Memory and I/O Module:
• Memory Module:
• It consists of a set of locations, defined by sequentially numbered
addresses.
• Each location contains a binary number that can be interpreted as
either an instruction or data.
• I/O module:
• It transfers data from external devices to CPU and memory, and vice
versa.
• It contains internal buffers for temporarily holding these data until
they can be sent on.

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Instruction Fetch and Execute:
• The processing required for a single instruction is called an
instruction cycle.
• There are two steps referred to as the fetch cycle and the execute
cycle as shown in the fig.4.

Fig.4. Basic Instruction Cycle

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Contd.
• At the beginning of each instruction cycle, the processor fetches an
instruction from memory.

• In a typical processor, a register called the program counter (PC)

holds the address of the instruction to be fetched next.

• Unless instructed, the processor always increments the PC after each

instruction fetch so that it will fetch the next instruction in sequence
(i.e., the instruction located at the next higher memory address).

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Contd.
• The fetched instruction is loaded into a register in the processor
known as the instruction register (IR).

• The instruction contains bits that specify the action the processor is
to take.

• The processor interprets the instruction and performs the required

action.

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Contd.
• The processor performs the following four actions:
• Processor-memory: Data may be transferred from processor to
memory or from memory to processor.

• Processor-I/O: Data may be transferred to or from a peripheral device

by transferring between the processor and an I/O module.

• Data processing: The processor may perform some arithmetic or logic

operation on data.

• Control: An instruction may specify that the sequence of execution be

altered.
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Characteristics of a Hypothetical Machine

6/2/2021 Fig.5. Characteristics ofOrganization

Computer a Hypothetical Machine
and Architecture 19
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Contd.
• An instruction’s execution may involve a combination of these
actions:
• Let us consider an example using a hypothetical machine that
includes the characteristics listed in fig.5.
• The processor contains a single data register, called an accumulator
(AC).
• Both instructions and data are 16 bits long. Thus, it is convenient to
organize memory using 16-bit words.
• The instruction format provides 4 bits for the opcode, so that there
can be as many as different opcodes, and
• Up to words of memory can be directly addressed.

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Basic Instruction Cycle:

Fig.6. Instruction Cycle State Diagram

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Contd.
• Fig.6. shows the state diagram of basic instruction cycle. The states
can be described as follows:
• Instruction address calculation (iac): Determine the address of the
next instruction to be executed. Usually, this involves adding a fixed
number to the address of the previous instruction.
• For example, if each instruction is 16 bits long and memory is
organized into 16-bit words, then add 1 to the previous address. If,
instead, memory is organized as individually addressable 8-bit bytes,
then add 2 to the previous address.
• Instruction fetch (if): Read instruction from its memory location into
the processor.
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Contd.
• Instruction operation decoding (iod): Analyze instruction to
determine type of operation to be performed and operand(s) to be
used.
• Operand address calculation (oac): If the operation involves
reference to an operand in memory or available via I/O, then
determine the address of the operand.
• Operand fetch (of): Fetch the operand from memory or read it in
from I/O.
• Data operation (do): Perform the operation indicated in the
instruction.
• Operand store (os): Write the result into memory or out to I/O.
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Contd.
• States in the upper part of fig.6. involve an exchange between the
processor and either memory or an I/O module.

• States in the lower part of the diagram involve only internal processor
operations.

• The oac state appears twice, because an instruction may involve a

read, a write, or both.

• However, the action performed during that state is fundamentally the

same in both cases, and soComputer
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only a single state identifier is needed. 25
Organization and Architecture
 Thank You !

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