Chapter 3

Introduction to 8086 microprocessors

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❑ In 1978, intel manufactured the 8086 microprocessor it’s 16-bit 40-pin
dual inline packaged chip.

❑ Contents:
✓ Features
✓ Signal and pins
✓ Architecture
✓ Register organization
✓ Memory segmentation.

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 Features of 8086
❑ The 8086 is a 16-bit microprocessor
❑ i.e. its arithmetic logic unit, registers and most of its instructions are designed
to work with 16-bit binary words.
❑ The 8086 has 16-bit data bus
❑ It can read data from or write data to memory and ports 16-bit data at a time.
❑ The 8086 has 20-bit address bus
❑ It can directly access 2^20 or 10,48,576 (1MB) memory locations.
❑ Each of the 10,48,576 memory locations are a byte wide 8 bit.

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❑ The 8086 can generate 16-bit I/O address
❑ Hence it accesses 216 = 65536 I/O ports.
❑ The 8086 provides fourteen 16-bit registers
❑ The 8086 has multiplexed address and data bus which reduces the number of pins
❑ The 8086 microprocessor performs bit, byte, word and block operation
❑ It performs the arithmetic and logical operations on bit, byte, word and
decimal numbers including multiplication and dividing.

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❑ The 8086 is designed to operate in two modes, namely minimum and
maximum mode
❑ The 8086 supports multiprogramming
❑ The 8086 fetches up to six instructions bytes from memory and queue stores
them in order to speed up instruction execution
❑ The 8086 provides powerful instruction set with the following addressing
modes:
❑ Register, immediate, direct, indirect through index or base, indirect
through the sum of a base and an index register, relative and implied.

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 Architecture of 8086
❑ The internal architecture of 8086 is divided into two separate functional units

1. The Bus Interface Unit, BIU

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 I. Bus interface unit, BIU
❑ The BIU of 8086’s interface the processor to the outside world
❑ It provides a full 16-bit bi-directional data bus and 20-bit unidirectional
address bus
❑ The BIU is responsible for performing all external bus operations, listed as:
❑ It sends address of memory or I/O
❑ It fetches instruction from memory
❑ It reads data from port/memory
❑ It writes data into port/memory
❑ It supports instruction queuing
❑ It provides the address relocation facility
❑ To implement these functions the BIU contains the instruction queue, segment
registers, instruction pointer, address summer and bus control logic units.

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Instruction queue
❑ To speed up program execution, the BIU fetches six instruction bytes a
head of time from memory
❑ Those prefetched instruction bytes are held for the execution unit in a
group of registers called queue
❑ With the help of queue, it’s possible to fetch the next instruction while
current instruction is in execution
❑ The BIU continues this process as long as the queue is not full
❑ Due to this execution unit gets ready instruction in the queue and
instruction fetch time is eliminated
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❑ The queue operates on the principle of first in first out FIFO
❑ Feature of fetching the next instruction while the current instruction is executing
is called pipelining

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 II. Execution unit EU
❑ The EU of 8086 tells the BIU from where to fetch instructions or data, decodes
instructions and executes instructions and it includes:
❑ Control circuitry
❑ Instruction decoder
❑ Arithmetic logic unit ALU
❑ Register organization
❑ Flag register
❑ General purpose register
❑ Pointer and index register

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❑ The control circuitry in EU guides the internal operations
❑ A decoder in EU translates the instructions fetched from memory in to a
series of actions which the EU performs
❑ ALU is 16-bit and,
❑ It can add, subtract, AND, OR, increment, decrement, complement
and shift binary numbers

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 Register organization
❑ The 8086 has a powerful set of 16-bit registers, those registers known as
programmer’s model of 8086, they all are accessible by the programmer

Pointer and Index register

Flag register

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 I. General purpose registers
❑ The 8086 has four 16-bit general purpose registers labeled AX, BX, CX and DX
❑ Each 16-bit general purpose register can be split into two 8-bit registers
❑ The letters L and H specify the lower and higher bytes of a particular register
❑ E.g. BL is the lower byte (8-bits) of register BX and
❑ BH is the higher byte (8-bits) of register BX
❑ The general-purpose registers are used for holding data and intermediate results
temporarily
❑ The register AX is used as 16-bit accumulator whereas register AL (lower byte of
AX) is used as 8-bit accumulator
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 II. Segment registers
❑ The physical address of the 8086 is 20-bits wide to access 1Mbyte memory
locations
❑ The 8086 treats the 1Mbytes of memory as divided into segments, with a max
size of segment as 64Kbytes. Thus, any location within the segment can be access
by using only 16-bits address
❑ The 8086 allows only four active segments at a time
❑ For the selection of the four active segments the 16-bit segments registers are
provided by the bus interface unit (BIU) of the 8086

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❑ Those four registers are:
❑ Code segment (CS) register
❑ Data segment (DS) register
❑ Extra segment (ES) register
❑ Stack segment (SS) register

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❑ Those registers are used to hold the upper 16-bit of the starting addresses of the
four memory segments
❑ The starting address is known as base address or segment base
❑ The BIU always inserts zeros for the lower 4-bits (nibble) in the content of
segment register to generate 20-bit base address
❑ E.g. If the code segment register contains 248AH, then the code segment will
start at address 348A0H

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 Functions of segment registers
❑ The CS register holds the upper 16-bit of the starting address of the segment from
which the BIU is currently fetching the instruction code byte
❑ The SS register is used for the upper 16-bit of the starting address for the
program stack
❑ The ES register and DS register are used to hold the upper 16-bit of the starting
address of the two memory segments which are used for data.

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 III. Pointer and index registers
❑ All segment registers are 16-bit wide, but its necessary to generate 20-bit address
(physical address) on the address bus
❑ To get 20-bit physical address one more pointer or index register are associated
with each segment register
❑ The pointer register IP, BP and SP are associated with code, data and stack
segments, respectively
❑ The index register DI and SI are used as a general-purpose register as well as for
offset storage incase of indexed, based indexed and relative based indexed
addressing modes
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 Instruction pointer (IP)
❑ the instruction pointer register is used as a program counter.
❑ IP used for the calculation of memory addresses of instructions which will be
executed.
❑ This register stores the offset for the instruction.
❑ The content of IP is automatically incremented while the execution of an
instruction is going on.
❑ The address of the next instruction is computed after adding IP contents to the
code segment register contents after 4-bit left-shift.

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 Stack pointer (SP)
❑ The stack pointer register contains the 16-bit offset
from the start of the segment to the top of stack
❑ E.g. The content of SS = 4000H and SP = 9F20H
❑ The shifted content of SS = 40000H
❑ After adding the offset from SP = 9F20H
❑ Finally, the 20-bit physical address of memory
is: 49F20H

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 Base pointer, Source and destination index (BP, SI and DI)
❑ These three 16-bit registers can be used as general-purpose registers However,
their main use is to hold the 16-bit offset of the data word in one of the segments

❑ Base pointer: We can use the BP register instead of SP for accessing the stack
using the based addressing mode
❑ Source index: SI can be used to hold the offset of a data word in the data
segment
❑ Destination index: the ES register pointes to the extra segment in which data is
stored.
❑ String instructions always use ES and DI to determine physical address 21
 IV. Flag register
❑ The flag register contains nine active flags which indicates some condition
produced by the execution of an instruction or controls certain operations of the
EU

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❑ Carry flag (CF)
❑ The carry flag is set to 1 if after arithmetic operation a carry is generated or a
❑ borrow is generated in subtraction.
❑ When there is no carry out, the carry flag is reset or 0.
❑ This flag can also be used in some shift and rotate instructions.
❑ Parity flag (PF)
❑ It is set to 1 if result of byte operation or lower byte of word operation contain
an even number of ones
❑ It is reset to 0 if result of byte operation or lower byte of word operation
contain an odd number of ones
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❑ Auxiliary flag (AF)
❑ It set to 1 if there is an overflow out of bit 3 i.e. carry from lower nibble to
higher nibble (D3 bit to D4)
❑ This flag is used for BCD operations and it is not available for programmer
❑ Zero flag (ZF)
❑ It set it the result of operation in ALU is zero and flag reset if the result is
nonzero
❑ It also set if a certain register content becomes zero following an increment or
decrement operation of that register

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❑ Sign flag (SF)
❑ After execution of arithmetic or logical operation, if the MSB of the result is 1,
the sign flag is set, which indicates the result is negative
❑ Overflow flag (OF)
❑ This flag is set to 1 if the signed result cannot be expressed within the number
of bits in the destination register.
❑ This flag is used to detect magnitude overflow in signed arithmetic operations.
❑ During addition operation, the flag is set when there is a carry into the MSB and
the flag is reset if there is no carry out of the MSB.
❑ For subtraction operation, the flag is set when the MSB desires a borrow,
❑ and the flag is reset if there is no borrow from MSB. 25
Cont.’

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❑ The three remaining flags are used to control certain operations of the processor
❑ Trap flag (TF)
❑ One way to debug a program is to run the program one instruction at a time
and see the contents of used registers and memory variables after execution of
every instruction
❑ Trap flag is used for single stepping through a program
❑ If set a trap is executed after execution of each instruction
❑ Thus, programmer can easily trace and correct errors in the program

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❑ Interrupt flag (IF)
❑ It’s used to allow/prohibit the interruption of a program
❑ If set a certain type of interrupt can be recognized by the 8086
❑ Direction flag (DF)
❑ It’s used with string instructions
❑ If DF = 0, the string is processed from its beginning with the first
element having the lowest address
❑ Otherwise, the string is processed from the high address towards the low
address
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 Memory segmentation
❑ Two types of memory segmentations are commonly used, linear and segmented
addressing.
❑ In linear addressing the entire memory space is available to the processor in one linear
array
❑ In segmented addressing on the other hand the available memory space is divided in to
chunks called segments known as segmented memory
❑ In 8086 the available memory space is 1Mbyte. This memory is divided into number of
logical segments
❑ Each segment is 64K bytes in size and addressed by one segment register

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❑ The 16-bit contents of the segment register
give the starting/base address of a
particular segment
❑ To access a specific memory location
within a segment we need an offset address
❑ The offset address is a 16-bit wide and it is
provided by one of the associated pointer
or index register

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 Rules for memory segmentation
1. The four segments can overlap for small programs, in a minimum system all

segments can start at address 00000H

2. The segment can begin/start at any memory address which is divisible by 16

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 Advantages of memory segmentation
1. It allows the memory addressing capacity to 1Mbyte even though the address
associated with individual instruction is only 16-bit
2. It allows instruction code, data, stack and portion of program to be more than 64KB
long by using more than one code, data, stack and extra segments
3. It facilitates use of separate memory areas for program, data and stack
4. It permits a program or its data to be put in different areas of memory, each time the
program, is executed

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 Generation of 20-bit address
❑ To access a specific memory location from any segment we need 20-bit physical
address
❑ The 8086 generates this address using the content of segment register and the
offset register associated with it
❑ E.g. The content of CS = 348AH
❑ The shifted content of CS = 348A0H
❑ After adding the offset from IP = 4214H
❑ Finally, the 20-bit physical address of memory is: 38AB4H

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❑ It is important to note that each segment requires particular segment register and
offset register to generate the 20-bit physical address

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Default and alternate register assignments

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❑ Eg. Assume:
❑ CS = 1000H, DS = 2000H, SS = 3000H, ES = 4000H, BP = 0010H, BX = 0020H,
SP = 0030H, SI = 0040H and DI = 0050H
1. MOV AL, [BP]

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2. MOV CX, [BX]

3. MOV AL, [BP+SI]

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4. MOV CS : [BX], AL

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