a High Speed 12-Bit

Monolithic D/A Converters

AD565A/AD566A
FEATURES FUNCTIONAL BLOCK DIAGRAMS
Single Chip Construction REF OUT VCC BIPOLAR OFF
Very High Speed Settling to 1/2 LSB
AD565A: 250 ns max 20V SPAN

AD566A: 350 ns max 10V AD565A 5k⍀

9.95k⍀
Full-Scale Switching Time: 30 ns REF
19.95k⍀ 0.5mA 10V SPAN

Guaranteed for Operation with ⴞ12 V (565A) Supplies, IN

IREF
5k⍀
DAC DAC OUT
with –12 V Supply (AD566A) IOUT =
REF 20k⍀ IO 8k⍀
Linearity Guaranteed Overtemperature GND 4 ⴛ IREF ⴛ CODE
1/2 LSB max (K, T Grades)
CODE INPUT
Monotonicity Guaranteed Overtemperature
Low Power: AD566A = 180 mW max; –VEE POWER MSB LSB
AD565A = 225 mW max GND BIPOLAR OFF
Use with On-Board High Stability Reference (AD565A)
or with External Reference (AD566A) 20V SPAN
AD566A
Low Cost 5k⍀
9.95k⍀
MlL-STD-883-Compliant Versions Available REF
19.95k⍀ 0.5mA 10V SPAN
IN 5k⍀
IREF
DAC DAC OUT
PRODUCT DESCRIPTION IOUT =
REF 20k⍀ IO 8k⍀
The AD565A and AD566A are fast 12-bit digital-to-analog GND 4 ⴛ IREF ⴛ CODE
converters that incorporate the latest advances in analog circuit
CODE INPUT
design to achieve high speeds at low cost.
The AD565A and AD566A use 12 precision, high speed bipolar –VEE POWER MSB LSB
GND
current-steering switches, a control amplifier, and a laser-trimmed
thin-film resistor network to produce a very fast, high accuracy AD565A and AD566A are available in four performance
analog output current. The AD565A also includes a buried grades. The J and K grades are specified for use over the 0°C to
Zener reference that features low noise, long-term stability, and +70°C temperature range while the S and T grades are speci-
temperature drift characteristics comparable to the best discrete fied for the –55°C to +125°C range. The D grades are all pack-
reference diodes. aged in a 24-lead, hermetically sealed, ceramic, dual-in-line
The combination of performance and flexibility in the AD565A and package. The JR grade is packaged in a 28-lead plastic SOIC.
AD566A has resulted from major innovations in circuit design, PRODUCT HIGHLIGHTS
an important new high speed bipolar process, and continuing 1. The wide output compliance range of the AD565A and
advances in laser-wafer-trimming techniques (LWT). The AD566A are ideally suited for fast, low noise, accurate voltage
AD565A and AD566A have a 10%–90% full-scale transition output configurations without an output amplifier.
time less than 35 ns and settle to within ±1/2 LSB in 250 ns max
(350 ns for AD566A). Both are laser-trimmed at the wafer level 2. The devices incorporate a newly developed, fully differential,
to ± 1/8 LSB typical linearity and are specified to ± 1/4 LSB max nonsaturating precision current switching cell structure that
error (K and T grades) at +25°C. High speed and accuracy make combines the dc accuracy and stability first developed in the
the AD565A and AD566A the ideal choice for high speed display AD562/AD563 with very fast switching times and an optimally
drivers as well as for fast analog-to-digital converters. damped settling characteristic.

The laser trimming process that provides the excellent linearity 3. The devices also contain SiCr thin-film application resistors
is also used to trim both the absolute value and the temperature that can be used with an external op amp to provide a preci-
coefficient of the reference of the AD565A, resulting in a typical sion voltage output or as input resistors for a successive-
full-scale gain TC of 10 ppm/°C. When tighter TC performance approximation A/D converter. The resistors are matched to
is required or when a system reference is available, the AD566A the internal ladder network to guarantee a low gain temperature
may be used with an external reference. coefficient and are laser-trimmed for minimum full-scale and
bipolar offset errors.
4. The AD565A and AD566A are available in versions compliant
with MIL-STD-883. Refer to the Analog Devices Military
Products Databook or current /883B data sheet for detailed
REV. E specifications.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 [Link]
under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2002
AD565A–SPECIFICATIONS (T = 25ⴗC, V A CC = 15 V, VEE = 15 V, unless otherwise noted.)
AD565AJ AD565AK
Parameter Min Typ Max Min Typ Max Unit
DATA INPUTS1 (Pins 13 to 24)
TTL or 5 V CMOS
Input Voltage
Bit ON Logic “1” 2.0 5.5 2.0 5.5 V
Bit OFF Logic “0” 0.8 0.8 V
Logic Current (Each Bit)
Bit ON Logic “1” 120 300 120 300 µA
Bit OFF Logic “0” 35 100 35 100 µA
RESOLUTION 12 12 Bits
OUTPUT
Current
Unipolar (All Bits On) –1.6 –2.0 –2.4 –1.6 –2.0 –2.4 mA
Bipolar (All Bits On or Off) ⴞ0.8 ± 1.0 ⴞ1.2 ⴞ0.8 ± 1.0 ⴞ1.2 mA
Resistance (Exclusive of Span Resistors) 6 8 10 6 8 10 kΩ
Offset
Unipolar 0.01 0.05 0.01 0.05 % of F.S. Range
Bipolar (Figure 3, R2 = 50 Ω Fixed) 0.05 0.15 0.05 0.1 % of F.S. Range
Capacitance 25 25 pF
Compliance Voltage
TMIN to TMAX –1.5 +10 –1.5 +10 V
ACCURACY (Error Relative to
Full Scale) 25°C ± 1/4 ⴞ1/2 ± 1/8 ⴞ0.35 LSB
(0.006) (0.012) (0.003) (0.0084) % of F.S. Range
TMIN to TMAX ± 1/2 ⴞ3/4 ± 1/4 ⴞ1/2 LSB
(0.012) (0.018) (0.006) (0.012) % of F.S. Range
DIFFERENTIAL NONLINEARITY
25°C ± 1/2 ⴞ3/4 ± 1/4 ⴞ1/2 LSB
TMIN to TMAX MONOTONICITY GUARANTEED MONOTONICITY GUARANTEED
TEMPERATURE COEFFICIENTS
With Internal Reference
Unipolar Zero 1 2 1 2 ppm/°C
Bipolar Zero 5 10 5 10 ppm/°C
Gain (Full Scale) 15 50 10 20 ppm/°C
Differential Nonlinearity 2 2 ppm/°C
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON 250 400 250 400 ns
FULL-SCALE TRANSITION
10% to 90% Delay plus Rise Time 15 30 15 30 ns
90% to 10% Delay plus Fall Time 30 50 30 50 ns
TEMPERATURE RANGE
Operating 0 +70 0 +70 °C
Storage –65 +150 –65 +150 °C
POWER REQUIREMENTS
VCC, +11.4 to +16.5 V dc 3 5 3 5 mA
VEE, –11.4 to –16.5 V dc –12 –18 –12 –18 mA
POWER SUPPLY GAIN SENSITIVITY2
VCC = +11.4 to +16.5 V dc 3 10 3 10 ppm of F.S./%
VEE = –11.4 to –16.5 V dc 15 25 15 25 ppm of F.S./%
PROGRAMMABLE OUTPUT RANGES
(See Figures 2, 3, 4) 0 to +5 0 to +5 V
–2.5 to +2.5 –2.5 to +2.5 V
0 to +10 0 to +10 V
–5 to +5 –5 to +5 V
–10 to +10 –10 to +10 V
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50 Ω
Resistor for R2 (Figure 2) ± 0.1 ⴞ0.25 ± 0.1 ⴞ0.25 % of F.S. Range
Bipolar Zero Error with Fixed
50 Ω Resistor for R1 (Figure 3) ± 0.05 ⴞ0.15 ± 0.05 ± 0.1 % of F.S. Range
Gain Adjustment Range (Figure 2) ± 0.25 ± 0.25 % of F.S. Range
Bipolar Zero Adjustment Range ± 0.15 ± 0.15 % of F.S. Range
REFERENCE INPUT
Input Impedance 15 20 25 15 20 25 kΩ
REFERENCE OUTPUT
Voltage 9.90 10.00 10.10 9.90 10.00 10.10 V
Current (Available for External Loads)3 1.5 2.5 1.5 2.5 mA
POWER DISSIPATION 225 345 225 345 mW
NOTES
1
The digital inputs are guaranteed but not tested over the operating temperature range.
2
The power supply gain sensitivity is tested in reference to a V CC, VEE of ± 15 V dc.
3
For operation at elevated temperatures, the reference cannot supply current for external loads. It, therefore, should be buffered if additional loads are to be supplied.
Specifications subject to change without notice.

–2– REV. E
 AD565A/AD566A
AD565AS AD565AT
Parameter Min Typ Max Min Typ Max Unit
DATA INPUTS1 (Pins 13 to 24)
TTL or 5 V CMOS
Input Voltage
Bit ON Logic “1” 2.0 5.5 2.0 5.5 V
Bit OFF Logic “0” 0.8 0.8 V
Logic Current (Each Bit)
Bit ON Logic “1” 120 300 120 300 µA
Bit OFF Logic “0” 35 100 35 100 µA
RESOLUTION 12 12 Bits
OUTPUT
Current
Unipolar (All Bits On) –1.6 –2.0 –2.4 –1.6 –2.0 –2.4 mA
Bipolar (All Bits On or Off) ⴞ0.8 ± 1.0 ⴞ1.2 ⴞ0.8 ± 1.0 ⴞ1.2 mA
Resistance (Exclusive of Span Resistors) 6 8 10 6 8 10 kΩ
Offset
Unipolar 0.01 0.05 0.01 0.05 % of F.S. Range
Bipolar (Figure 3, R2 = 50 Ω Fixed) 0.05 0.15 0.05 0.1 % of F.S. Range
Capacitance 25 25 pF
Compliance Voltage
TMIN to TMAX –1.5 +10 –1.5 +10 V
ACCURACY (Error Relative to
Full Scale) 25°C ± 1/4 ⴞ1/2 ± 1/8 ⴞ0.35 LSB
(0.006) (0.012) (0.003) (0.0084) % of F.S. Range
TMIN to TMAX ± 1/2 ⴞ3/4 ± 1/4 ⴞ1/2 LSB
(0.012) (0.018) (0.006) (0.012) % of F.S. Range
DIFFERENTIAL NONLINEARITY
25°C ± 1/2 ⴞ3/4 ± 1/4 ⴞ1/2 LSB
TMIN to TMAX MONOTONICITY GUARANTEED MONOTONICITY GUARANTEED
TEMPERATURE COEFFICIENTS
With Internal Reference
Unipolar Zero 1 2 1 2 ppm/°C
Bipolar Zero 5 10 5 10 ppm/°C
Gain (Full Scale) 15 30 10 15 ppm/°C
Differential Nonlinearity 2 2 ppm/°C
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON 250 400 250 400 ns
FULL-SCALE TRANSITION
10% to 90% Delay plus Rise Time 15 30 15 30 ns
90% to 10% Delay plus Fall Time 30 50 30 50 ns
TEMPERATURE RANGE
Operating –55 +125 –55 +125 °C
Storage –65 +150 –65 +150 °C
POWER REQUIREMENTS
VCC, +11.4 to +16.5 V dc 3 5 3 5 mA
VEE, –11.4 to –16.5 V dc –12 –18 –12 –18 mA
POWER SUPPLY GAIN SENSITIVITY2
VCC = +11.4 to +16.5 V dc 3 10 3 10 ppm of F.S./%
VEE = –11.4 to –16.5 V dc 15 25 15 25 ppm of F.S./%
PROGRAMMABLE OUTPUT RANGES
(See Figures 2, 3, 4) 0 to +5 0 to +5 V
–2.5 to +2.5 –2.5 to +2.5 V
0 to +10 0 to +10 V
–5 to +5 –5 to +5 V
–10 to +10 –10 to +10 V
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50 Ω
Resistor for R2 (Figure 2) ± 0.1 ⴞ0.25 ± 0.1 ⴞ0.25 % of F.S. Range
Bipolar Zero Error with Fixed
50 Ω Resistor for R1 (Figure 3) ± 0.05 ⴞ0.15 ± 0.05 ⴞ0.1 % of F.S. Range
Gain Adjustment Range (Figure 2) ± 0.25 ± 0.25 % of F.S. Range
Bipolar Zero Adjustment Range ± 0.15 ± 0.15 % of F.S. Range
REFERENCE INPUT
Input Impedance 15 20 25 15 20 25 kΩ
REFERENCE OUTPUT
Voltage 9.90 10.00 10.10 9.90 10.00 10.10 V
Current (Available for External Loads)3 1.5 2.5 1.5 2.5 mA
POWER DISSIPATION 225 345 225 345 mW
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
Specification subject to change without notice.

REV. E –3–
AD566A–SPECIFICATIONS(T = 25ⴗC, V A EE = –15 V, unless otherwise noted)

AD566AJ AD566AK
Parameter Min Typ Max Min Typ Max Unit
DATA INPUTS1 (Pins 13 to 24)
TTL or 5 V CMOS
Input Voltage
Bit ON Logic “1” 2.0 5.5 2.0 5.5 V
Bit OFF Logic “0” 0 0.8 0 0.8 V
Logic Current (Each Bit)
Bit ON Logic “1” 120 300 120 300 µA
Bit OFF Logic “0” 35 100 35 100 µA
RESOLUTION 12 12 Bits
OUTPUT
Current
Unipolar (All Bits On) –1.6 –2.0 –2.4 –1.6 –2.0 –2.4 mA
Bipolar (All Bits On or Off) ⴞ0.8 ± 1.0 ⴞ1.2 ⴞ0.8 ± 1.0 ⴞ1.2 mA
Resistance (Exclusive of Span Resistors) 6 8 10 6 8 10 kΩ
Offset
Unipolar (Adjustable to Zero per Figure 3) 0.01 0.05 0.01 0.05 % of F.S. Range
Bipolar (Figure 4, R1 and R2 = 50 Ω Fixed) 0.05 0.15 0.05 0.1 % of F.S. Range
Capacitance 25 25 pF
Compliance Voltage
TMIN to TMAX –1.5 +10 –1.5 +10 V
ACCURACY (Error Relative to
Full Scale) 25°C ± 1/4 ⴞ1/2 ± 1/8 ⴞ0.35 LSB
(0.006) (0.012) (0.003) (0.0084) % of F.S. Range
TMIN to TMAX ± 1/2 ⴞ3/4 ± 1/4 ⴞ1/2 LSB
(0.012) (0.018) (0.006) (0.012) % of F.S. Range
DIFFERENTIAL NONLINEARITY
25°C ± 1/2 ⴞ3/4 ± 1/4 ⴞ1/2 LSB
TMIN to TMAX MONOTONICITY GUARANTEED MONOTONICITY GUARANTEED
TEMPERATURE COEFFICIENTS
Unipolar Zero 1 2 1 2 ppm/°C
Bipolar Zero 5 10 5 10 ppm/°C
Gain (Full Scale) 7 10 3 5 ppm/°C
Differential Nonlinearity 2 2 ppm/°C
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON 250 350 250 350 ns
FULL-SCALE TRANSITION
10% to 90% Delay plus Rise Time 15 30 15 30 ns
90% to 10% Delay plus Fall Time 30 50 30 50 ns
POWER REQUIREMENTS
VEE, –11.4 to –16.5 V dc –12 –18 –12 –18 mA
POWER SUPPLY GAIN SENSITIVITY 2
VEE = –11.4 to –16.5 V dc 15 25 15 25 ppm of F.S./%
PROGRAMMABLE OUTPUT RANGES
(see Figures 3, 4, 5) 0 to +5 0 to +5 V
–2.5 to +2.5 –2.5 to +2.5 V
0 to +10 0 to +10 V
–5 to +5 –5 to +5 V
–10 to +10 –10 to +10 V
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50 Ω
Resistor for R2 (Figure 3) ± 0.1 ⴞ0.25 ± 0.1 ⴞ0.25 % of F.S. Range
Bipolar Zero Error with Fixed
50 Ω Resistor for R1 (Figure 4) ± 0.05 ⴞ0.15 ± 0.05 ⴞ0.1 % of F.S. Range
Gain Adjustment Range (Figure 3) ± 0.25 ± 0.25 % of F.S. Range
Bipolar Zero Adjustment Range ± 0.15 ± 0.15 % of F.S. Range
REFERENCE INPUT
Input Impedance 15 20 25 15 20 25 kΩ
POWER DISSIPATION 180 300 180 300 mW
MULTIPLYING MODE PERFORMANCE (All Models)
Quadrants Two (2): Bipolar Operation at Digital Input Only
Reference Voltage 1 V to 10 V, Unipolar
Accuracy 10 Bits (± 0.05% of Reduced F.S.) for 1 V dc Reference Voltage
Reference Feedthrough (Unipolar Mode,
All Bits OFF, and 1 V to 10 V [p-p], Sine Wave
Frequency for 1/2 LSB [p-p] Feedthrough) 40 kHz typ
Output Slew Rate 10%–90% 5 mA/µs
90%–10% 1 mA/µs
Output Settling Time (All Bits ON and a 0 V–10 V
Step Change in Reference Voltage) 1.5 µs to 0.01% F.S.
CONTROL AMPLIFIER
Full Power Bandwidth 300 kHz
Small-Signal Closed-Loop Bandwidth 1.8 MHz
NOTES
1
The digital input levels are guaranteed but not tested over the temperature range.
2
The power supply gain sensitivity is tested in reference to a V EE of –1.5 V dc.
Specifications subject to change without notice.

–4– REV. E
 AD565A/AD566A
AD566AS AD566AT
Parameter Min Typ Max Min Typ Max Unit
1
DATA INPUTS (Pins 13 to 24)
TTL or 5 V CMOS
Input Voltage
Bit ON Logic “1” 2.0 5.5 2.0 5.5 V
Bit OFF Logic “0” 0 0.8 0 0.8 V
Logic Current (Each Bit)
Bit ON Logic “1” 120 300 +120 300 µA
Bit OFF Logic “0” 35 100 +35 100 µA
RESOLUTION 12 12 Bits
OUTPUT
Current
Unipolar (All Bits On) –1.6 –2.0 –2.4 –1.6 –2.0 –2.4 mA
Bipolar (All Bits On or Off) ⴞ0.8 ± 1.0 ⴞ1.2 ⴞ0.8 ± 1.0 ⴞ1.2 mA
Resistance (Exclusive of Span Resistors) 6 8 10 6 8 10 kΩ
Offset
Unipolar (Adjustable to Zero per Figure 3) 0.01 0.05 0.01 0.05 % of F.S. Range
Bipolar (Figure 4, R1 and R2 = 50 Ω Fixed) 0.05 0.15 0.05 0.1 % of F.S. Range
Capacitance 25 25 pF
Compliance Voltage
TMIN to TMAX –1.5 +10 –1.5 +10 V
ACCURACY (Error Relative to
Full Scale) 25°C ± 1/4 ⴞ1/2 ± 1/8 ⴞ0.35 LSB
(0.006) (0.012) (0.003) (0.0084) % of F.S. Range
TMIN to TMAX ± 1/2 ⴞ3/4 ± 1/4 ⴞ1/2 LSB
(0.012) (0.018) (0.006) (0.012) % of F.S. Range
DIFFERENTIAL NONLINEARITY
25°C ± 1/2 ⴞ3/4 ± 1/4 ⴞ1/2 LSB
TMIN to TMAX MONOTONICITY GUARANTEED MONOTONICITY GUARANTEED
TEMPERATURE COEFFICIENTS
Unipolar Zero 1 2 1 2 ppm/°C
Bipolar Zero 5 10 5 10 ppm/°C
Gain (Full Scale) 7 10 3 5 ppm/°C
Differential Nonlinearity 2 2 ppm/°C
SETTLING TIME TO 1/2 LSB
All Bits ON-to-OFF or OFF-to-ON 250 350 250 350 ns
FULL-SCALE TRANSITION
10% to 90% Delay plus Rise Time 15 30 15 30 ns
90% to 10% Delay plus Fall Time 30 50 30 50 ns
POWER REQUIREMENTS
VEE, –11.4 to –16.5 V dc –12 –18 –12 –18 mA
POWER SUPPLY GAIN SENSITIVITY 2
VEE = –11.4 to –16.5 V dc 15 25 15 25 ppm of F.S./%
PROGRAMMABLE OUTPUT RANGES
(see Figures 3, 4, 5) 0 to +5 0 to +5 V
–2.5 to +2.5 –2.5 to +2.5 V
0 to +10 0 to +10 V
–5 to +5 –5 to +5 V
–10 to +10 –10 to +10 V
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50 Ω
Resistor for R2 (Figure 3) ± 0.1 ⴞ0.25 ± 0.1 ⴞ0.25 % of F.S. Range
Bipolar Zero Error with Fixed
50 Ω Resistor for R1 (Figure 4) ± 0.05 ⴞ0.15 ± 0.05 ⴞ0.1 % of F.S. Range
Gain Adjustment Range (Figure 3) ± 0.25 ± 0.25 % of F.S. Range
Bipolar Zero Adjustment Range ± 0.15 ± 0.15 % of F.S. Range
REFERENCE INPUT
Input Impedance 15 20 25 15 20 25 kΩ
POWER DISSIPATION 180 300 180 300 mW
MULTIPLYING MODE PERFORMANCE (All Models)
Quadrants Two (2): Bipolar Operation at Digital Input Only
Reference Voltage 1 V to 10 V, Unipolar
Accuracy 10 Bits (± 0.05% of Reduced F.S.) for 1 V dc Reference Voltage
Reference Feedthrough (Unipolar Mode,
All Bits OFF, and 1 V to 10 V [p-p], Sine Wave
Frequency for l/2 LSB [p-p] Feedthrough) 40 kHz typ
Output Slew Rate 10%–90% 5 mA/µs
90%–10% 1 mA/µs
Output Settling Time (All Bits ON and a 0 V–10 V
Step Change in Reference Voltage) 1.5 µs to 0.01% F.S.
CONTROL AMPLIFIER
Full Power Bandwidth 300 kHz
Small-Signal Closed-Loop Bandwidth 1.8 MHz
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max
specifications are guaranteed, although only those shown in boldface are tested on all production units.
Specification subject to change without notice.

REV. E –5–
AD565A/AD566A
ABSOLUTE MAXIMUM RATINGS GROUNDING RULES
VCC to Power Ground . . . . . . . . . . . . . . . . . . . . . 0 V to +18 V The AD565A and AD566A use separate reference and power
VEE to Power Ground (AD565A) . . . . . . . . . . . . 0 V to –18 V grounds to allow optimum connections for low noise and high
Voltage on DAC Output (Pin 9) . . . . . . . . . . . . –3 V to +12 V speed performance. These grounds should be tied together at one
Digital Inputs (Pins 13 to 24) to point, usually the device power ground. The separate ground
Power Ground . . . . . . . . . . . . . . . . . . . . . . –1.0 V to +7.0 V returns minimize current flow in low level signal paths. In this
REF IN to Reference Ground . . . . . . . . . . . . . . . . . . . . ± 12 V way, logic return currents are not summed into the same return
Bipolar Offset to Reference Ground . . . . . . . . . . . . . . . ± 12 V path with analog signals.
10 V Span R to Reference Ground . . . . . . . . . . . . . . . . ± 12 V
20 V Span R to Reference Ground . . . . . . . . . . . . . . . . ± 24 V
REF OUT (AD565A) . . . . . Indefinite Short to Power Ground
Momentary Short to VCC
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW

AD565A ORDERING GUIDE

Max Gain Linearity

T.C. (ppm Temperature Error Max Package
Model1 of F.S./°C) Range @ +25°C Options2
AD565AJD 50 0°C to +70°C ± 1/2 LSB Ceramic (D-24)
AD565AJR 50 0°C to +70°C ± 1/2 LSB SOIC (RW-28)
AD565AKD 20 0°C to +70°C ± 1/4 LSB Ceramic (D-24)
AD565ASD 30 –55°C to +125°C ± 1/2 LSB Ceramic (D-24)
AD565ATD 15 –55°C to +125°C ± 1/4 LSB Ceramic (D-24)
NOTES
1
For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or current/883B data sheet.
2
D = Ceramic DIP, R = SOIC.

AD566A ORDERING GUIDE

Max Gain Linearity

T.C. (ppm Temperature Error Max Package
Model1 of F.S./°C) Range @ +25°C Option2
AD566AJD 10 0°C to +70°C ± 1/2 LSB Ceramic (D-24
AD566AKD 3 0°C to +70°C ± 1/4 LSB Ceramic (D-24)
AD566ASD 10 –55°C to +125°C ± 1/2 LSB Ceramic (D-24)
AD566ATD 3 –55°C to +125°C ± 1/4 LSB Ceramic (D-24)
NOTES
1
For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or current/883B data sheet.
2
D = Ceramic DIP.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the WARNING!
AD565A/AD566A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
ESD SENSITIVE DEVICE
recommended to avoid performance degradation or loss of functionality.

–6– REV.E
 AD565A/AD566A
PIN CONFIGURATIONS

24-Lead DIP 24-Lead DIP

NC 1 24 BIT 1 IN (MSB) NC 1 24 BIT 1 IN (MSB)

NC 2 23 BIT 2 IN NC 2 23 BIT 2 IN
VCC 3 22 BIT 3 IN REF GND 3 22 BIT 3 IN
REF OUT (+10V ±1%) 4 21 BIT 4 IN AMP SUMMING JUNCTION 4 21 BIT 4 IN
REF GND 5 20 BIT 5 IN REF V HI IN 5 20 BIT 5 IN
AD565A AD566A
REF IN 6 TOP VIEW 19 BIT 6 IN –VEE –15V IN (20mA) 6 TOP VIEW 19 BIT 6 IN
–VEE 7 (Not to Scale) 18 BIT 7 IN BIPOLAR OFFSET IN 7 (Not to Scale) 18 BIT 7 IN

BIPOLAR OFFSET IN 8 17 BIT 8 IN NC 8 17 BIT 8 IN

DAC OUT (–2mA F.S.) 9 16 BIT 9 IN DAC OUT (–2mA F.S.) 9 16 BIT 9 IN
10V SPAN R 10 15 BIT 10 IN 10V SPAN R 10 15 BIT 10 IN
20V SPAN R 11 14 BIT 11 IN 20V SPAN R 11 14 BIT 11 IN
PWR GND 12 13 BIT 12 IN (LSB) PWR GND 12 13 BIT 12 IN (LSB)

NC = NO CONNECT NC = NO CONNECT

28-Lead SOIC

NC 1 28 NC
NC 2 27 BIT 1 (MSB)
NC 3 26 BIT 2
VCC 4 25 BIT 3
REF OUT (10V) 5 24 BIT 4
REF GND 6 23 BIT 5
AD565A
REF IN 7 TOP VIEW 22 BIT 6
NC 8 (Not to Scale) 21 BIT 7

–VEE 9 20 BIT 8

BIPOLAR OFFSET IN 10 19 BIT 9

DAC OUT 11 18 BIT 10
NC 12 17 BIT 11
10V SPAN R 13 16 BIT 12 (LSB)
20V SPAN R 14 15 PWR GND

NC = NO CONNECT

REV. E –7–
AD565A/AD566A
CONNECTING THE AD565A FOR BUFFERED VOLTAGE
OUTPUT REF
R1
VCC 100⍀ BIPOLAR OFF
The standard current-to-voltage conversion connections using an OUT
operational amplifier are shown in Figures 1, 2, and 3 with the 20V SPAN
5k⍀
preferred trimming techniques. If a low offset operational amplifier 9.95k⍀ 10V SPAN
R2 10V
(OP77, AD741L, OP07) is used, excellent performance can be 100⍀ AD565A 5k⍀
obtained in many situations without trimming (an op amp with 10pF OUTPUT
less than 0.5 mV max offset voltage should be used to keep offset 19.95k⍀ 0.5mA IO 8k⍀ DAC –5V TO
OUT +5V
errors below 1/2 LSB). If a 50 Ω fixed resistor is substituted for REF IREF
DAC AD509
IN
the 100 Ω trimmer, unipolar zero is typically within ± 1/2 LSB 20k⍀
IOUT =
2.4k⍀
REF 4 ⴛ IREF
(plus op amp offset) and full-scale accuracy is within 0.1% GND
ⴛ CODE
(0.25% max). Substituting a 50 Ω resistor for the 100 Ω bipo- CODE
lar offset trimmer gives a bipolar zero error typically within POWER
GND
INPUT
± 2 LSB (0.05%).
–VEE MSB LSB
The AD509 is recommended for buffered voltage-output
applications that require a settling time to ± 1/2 LSB of
1 µs. The feedback capacitor is shown with the optimum value Figure 2. ± 5 V Bipolar Voltage Output
for each application; this capacitor is required to compen-
sate for the 25 pF DAC output capacitance. STEP I . . . OFFSET ADJUST
Turn OFF all bits. Adjust 100 Ω trimmer R1 to give –5.000 V
FIGURE 1. UNIPOLAR CONFIGURATION output.
This configuration provides a unipolar 0 V to 10 V output
range. In this mode, the bipolar terminal, Pin 8, should be STEP II . . . GAIN ADJUST
grounded if not used for trimming. Turn ON all bits. Adjust 100 Ω gain trimmer R2 to give a
reading of +4.9976 V.
+15V
100k⍀ R1
Please note that it is not necessary to trim the op amp to obtain
50k⍀ full accuracy at room temperature. In most bipolar situations,
100⍀
–15V an op amp trim is unnecessary unless the untrimmed offset drift
REF VCC BIPOLAR OFF
of the op amp is excessive.
OUT

20V SPAN
FIGURE 3. OTHER VOLTAGE RANGES
5k⍀
10V SPAN
The AD565A can also be easily configured for a unipolar 0 V to
9.95k⍀
R2 10V +5 V range or ± 2.5 V and ± 10 V bipolar ranges by using the
100⍀ AD565A 5k⍀
additional 5 kΩ application resistor provided at the 20 V span R
10pF OUTPUT
19.95k⍀ 0.5mA IO 8k⍀ DAC 0V TO terminal, Pin 11. For a 5 V span (0 V to +5 V, or ± 2.5 V), the
OUT +10V
REF IREF AD509
two 5 kΩ resistors are used in parallel by shorting Pin 11 to Pin 9
DAC
IN
IOUT =
2.4k⍀
and connecting Pin 10 to the op amp output and the bipolar
20k⍀
REF 4 ⴛ IREF offset either to ground for unipolar or to REF OUT for the
GND
ⴛ CODE
bipolar offset either to ground for unipolar or to REF OUT for
POWER
CODE
INPUT the bipolar range. For the ± 10 V range (20 V span) use the 5 kΩ
GND
resistors in series by connecting only Pin 11 to the op amp output
–VEE MSB LSB and the bipolar offset connected as shown. The ± 10 V option is
shown in Figure 3.
Figure 1. 0 V to 10 V Unipolar Voltage Output
R1
STEP I . . . ZERO ADJUST REF VCC 100⍀ BIPOLAR OFF
OUT
Turn all bits OFF and adjust zero trimmer R1 until the output
20V SPAN
reads 0.000 V (1 LSB = 2.44 mV). In most cases, this trim is not
5k⍀
needed, but Pin 8 should then be connected to Pin 12. R2 10V
9.95k⍀ 10V SPAN

100⍀ AD565A 5k⍀

STEP II . . . GAIN ADJUST 10pF
OUTPUT
19.95k⍀
Turn all bits ON and adjust 100 Ω gain trimmer R2 until the 0.5mA IO 8k⍀ DAC
OUT
–10V TO
+10V
REF IREF
output is 9.9976 V. (Full scale is adjusted to 1 LSB less than IN DAC AD509
IOUT =
nominal full scale of 10.000 V.) If a 10.2375 V full scale is desired REF 20k⍀
4 ⴛ IREF
3.0k⍀

(exactly 2.5 mV/bit), insert a 120 Ω resistor in series with the gain GND
ⴛ CODE
resistor at Pin 10 to the op amp output. CODE
POWER INPUT
GND
FIGURE 2. BIPOLAR CONFIGURATION
This configuration provides a bipolar output voltage from –VEE MSB LSB
–5.000 V to +4.9976 V, with positive full scale occurring with
all bits ON (all 1s). Figure 3. ± 10 V Voltage Output

–8– REV.E
 AD565A/AD566A
CONNECTING THE AD566A FOR BUFFERED VOLTAGE STEP II . . . GAIN ADJUST
OUTPUT Turn all bits ON and adjust 100 Ω gain trimmer, R2, until the
The standard current-to-voltage conversion connections using an output is 9.9976 V. (Full scale is adjusted to 1 LSB less than
operational amplifier are shown in Figures 4, 5, and 6 with the nominal full scale of 10.000 V.) If a 10.2375 V full scale is desired
preferred trimming techniques. If a low offset operational amplifier (exactly 2.5 mV/bit), insert a 120 Ω resistor in series with the
(OP77, AD741L, OP07) is used, excellent performance can be gain resistor at Pin 10 to the op amp output.
obtained in many situations without trimming (an op amp with
less than 0.5 mV max offset voltage should be used to keep offset FIGURE 5. BIPOLAR CONFIGURATION
errors below 1/2 LSB). If a 50 Ω fixed resistor is substituted for the This configuration provides a bipolar output voltage from
100 Ω trimmer, unipolar zero typically is within ±1/2 LSB (plus op –5.000 V to +4.9976 V, with positive full scale occurring with
amp offset), and full-scale accuracy is within 0.1% (0.25% max). all bits ON (all 1s).
Substituting a 50 Ω resistor for the 100 Ω bipolar offset trimmer
gives a bipolar zero error typically within ± 2 LSB (0.05%).
The AD509 is recommended for buffered voltage-output R1
100⍀ BIPOLAR OFF
applications that require a settling time to ± 1/2 LSB of 1 µs. The
20V SPAN
feedback capacitor is shown with the optimum value for each AD566A
application; this capacitor is required to compensate for the 9.95k⍀ 5k⍀
10V SPAN
25 pF DAC output capacitance.
R2 5k⍀
100⍀ REF 10pF
FIGURE 4. UNIPOLAR CONFIGURATION IN 19.95k⍀ 0.5mA IO 8k⍀ DAC
This configuration provides a unipolar 0 V to 10 V output range. OUT
IREF
In this mode, the bipolar terminal, Pin 7, should be grounded if not +V 10V EREF DAC AD509
AD561 IOUT =
used for trimming. 20k⍀ 4 ⴛ IREF 2.4k⍀
REF ⴛ CODE
+15V GND CODE
100⍀ 100k⍀ POWER INPUT
R1
GND
50k⍀
BIPOLAR OFF –15V –VEE MSB LSB

20V SPAN
AD566A
9.95k⍀ 5k⍀
Figure 5. ± 5 V Bipolar Voltage Output
10V SPAN

5k⍀ STEP I . . . OFFSET ADJUST

R2 REF 10pF Turn OFF all bits. Adjust 100 Ω trimmer R1 to give –5.000
IN 19.95k⍀ 0.5mA DAC
100⍀ IO 8k⍀
OUT
output V.
IREF
+V 10V EREF DAC AD509
AD561 IOUT = STEP II . . . GAIN ADJUST
20k⍀ 4 ⴛ IREF 2.4k⍀
REF ⴛ CODE
Turn ON all bits. Adjust 100 Ω gain trimmer R2 to give a read-
GND CODE ing of +4.9976 V.
POWER INPUT
GND Please note that it is not necessary to trim the op amp to obtain
–VEE MSB LSB
full accuracy at room temperature. In most bipolar situations,
an op amp trim is unnecessary unless the untrimmed offset drift
of the op amp is excessive.
Figure 4. 0 V to 10 V Unipolar Voltage Output

STEP I . . . ZERO ADJUST

Turn all bits OFF and adjust zero trimmer, R1, until the output
reads 0.000 V (1 LSB = 2.44 mV). In most cases, this trim is
not needed, but Pin 7 should then be connected to Pin 12.

REV. E –9–
AD565A/AD566A
FIGURE 6. OTHER VOLTAGE RANGES
The AD566A can also be easily configured for a unipolar 0 V to R1
+5 V range or ± 2.5 V and ± 10 V bipolar ranges by using the 5k⍀ BIPOLAR OFF

additional 5 kΩ application resistor provided at the 20 V span R 20V SPAN

terminal, Pin 11. For a 5 V span (0 V to +5 V or ± 2.5 V), the two AD566A
9.95k⍀ 5k⍀
5 kΩ resistors are used in parallel by shorting Pin 11 to Pin 9 and 14k⍀ 10V SPAN
10pF
connecting Pin 10 to the op amp output and the bipolar offset R2 5k⍀
resistor either to ground for unipolar or to VREF for the bipolar 5k⍀
REF
range. For the ±10 V range (20 V span), use the 5 kΩ resistors in IN 19.95k⍀ 0.5mA IO 8k⍀ DAC
OUT
series by connecting only Pin 11 to the op amp output and the IREF
EREF DAC
bipolar offset connected as shown. The ± 10 V option is shown –V 7.5V
AD561 IOUT =
AD509
20k⍀ 2.4k⍀
in Figure 6. 4 ⴛ IREF
REF ⴛ CODE
GND CODE
POWER INPUT R3
GND 26k⍀*

–VEE MSB LSB

* THE PARALLEL COMBINATION OF THE BIPOLAR OFFSET RESISTOR

AND R3 ESTABLISHES A CURRENT TO BALANCE THE MSB CURRENT.
THE EFFECT OF TEMPERATURE COEFFICIENT MISMATCH BETWEEN
THE BIPOLAR RESISTOR COMBINATION AND DAC RESISTORS IS
EXPANDED ON PREVIOUS PAGE.

Figure 6. ± 10 V Voltage Output

Table I. Digital Input Codes

DIGITAL INPUT ANALOG OUTPUT

MSB LSB Straight Binary Offset Binary Twos Complement*
000000000000 Zero –FS Zero
011111111111 Mid Scale – 1 LSB Zero – 1 LSB +FS – 1 LSB
100000000000 +1/2 FS Zero –FS
111111111111 +FS – l LSB +FS – 1 LSB Zero – 1 LSB
*Inverts the MSB of the offset binary code with an external inverter to obtain twos complement.

–10– REV.E
 AD565A/AD566A
OUTLINE DIMENSIONS

24-Lead Side-Brazed Solder Lid Ceramic DIP [DIP/SB]

(D-24)
Dimensions shown in inches and (millimeters)

0.005 (0.13) MIN 0.098 (2.49) MAX

24 13

0.610 (15.49)
0.500 (12.70)
PIN 1 1 12
0.620 (15.75)
1.290 (32.77) MAX 0.075 (1.91) 0.590 (14.99)
0.225 (5.72) 0.015 (0.38)
MAX 0.150
0.200 (5.08) (3.81)
0.120 (3.05) MIN
SEATING 0.015 (0.38)
0.023 (0.58) 0.100 (2.54) 0.070 (1.78)
PLANE 0.008 (0.20)
0.014 (0.36) BSC 0.030 (0.76)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

28-Lead Standard Small Outline Package [SOIC]

Wide Body
(RW-28)
Dimensions shown in millimeters and (inches)

18.10 (0.7126)
17.70 (0.6969)

28 15
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
1 14
10.00 (0.3937)

2.65 (0.1043) 0.75 (0.0295)

2.35 (0.0925) ⴛ 45ⴗ
0.25 (0.0098)
0.30 (0.0118)
0.10 (0.0039)
8ⴗ
1.27 (0.0500) 0.51 (0.0201) SEATING 0ⴗ 1.27 (0.0500)
COPLANARITY 0.32 (0.0126)
0.10
BSC 0.33 (0.0130) PLANE 0.40 (0.0157)
0.23 (0.0091)

COMPLIANT TO JEDEC STANDARDS MS-013AE

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

Revision History
Location Page
10/02—Data Sheet changed from REV. D to REV. E.
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
OUTLINE DIMENSIONS updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

REV. E –11–
–12–
PRINTED IN U.S.A. C00516–0–10/02(E)