LAB-1: Basic Gates
1. AND Gate
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AndGate_021304 is Port
( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end AndGate_021304;
architecture Behavioral of AndGate_021304 is
begin
y<=a and b;
end Behavioral;
RTL SCHEMATIC DIAGRAM:
Timing Diagram:
2. OR Gate
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity OrGate_021304 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end OrGate_021304;
architecture Behavioral of OrGate_021304 is
Begin
y<= a or b;
end Behavioral;
RTL SCHEMATIC DIAGRAM:
Timing Diagram:
3. NOT Gate
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity NotGate_021304 is
Port ( a : in STD_LOGIC;
y : out STD_LOGIC);
end NotGate_021304;
architecture Behavioral of NotGate_021304 is
Begin
y<= not a;
end Behavioral;
RTL SCHEMATIC DIAGRAM:
Timing Diagram:
4. NAND Gate
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity NandGate021304 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end NandGate021304;
architecture Behavioral of NandGate021304 is
Begin
y<=a nand b;
end Behavioral;
RTL SCHEMATIC DIAGRAM:
Timing Diagram:
5. NOR Gate
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity NorGate_021304 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end NorGate_021304;
architecture Behavioral of NorGate_021304 is
begin
y<=a nor b;
end Behavioral;
RTL SCHEMATIC DIAGRAM:
Timing Diagram:
6. X-OR Gate
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity XorGate_021304 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end XorGate_021304;
architecture Behavioral of XorGate_021304 is
begin
y<= a xor b;
end Behavioral;
RTL SCHEMATIC DIAGRAM:
Timing Diagram:
LAB-2: 1-Bit Comparator
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Comparator_021304 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : inout STD_LOGIC;
d : out STD_LOGIC;
e : inout STD_LOGIC);
end Comparator_021304;
architecture Behavioral of Comparator_021304 is
Begin
c<=(not a) and b;
e<=(not b) and a;
d<=c nor e;
end Behavioral;
RTL SCHEMATIC DIAGRAM:
Timing Diagram:
LAB-3: Half Adder and Full Adder
3.1 Half Adder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity HalfAdder_021304 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end HalfAdder_021304;
architecture Behavioral of HalfAdder_021304 is
Begin
process(a,b) begin
if a='0' and b='0' then
s<='0';
c<='0';
elsif a='0' and b='1' then
s<='1';
c<='0';
elsif a='1' and b='0' then
s<='1';
c<='0';
else
s<='0';
c<='1';
end if;
end process;
end Behavioral;
RTL SCHEMATIC DIAGRAM:
Timing Diagram:
3.2 Full Adder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FullAdder_021304 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
s : out STD_LOGIC;
cout : out STD_LOGIC);
end FullAdder_021304;
architecture Behavioral of FullAdder_021304 is
signal d,e,f:STD_LOGIC;
begin
d<= a xor b;
s<=d xor cin;
e<=d and cin;
f<=a and b;
cout<=e or f;
end Behavioral;
RTL SCHEMATIC DIAGRAM:
Timing Diagram:
LAB-4: Multiplexer and Demultiplexer(4:1)
4.1. 4:1 Multiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Multiplexer_021304 is
Port ( i3 : in STD_LOGIC;
i2 : in STD_LOGIC;
i1 : in STD_LOGIC;
i0 : in STD_LOGIC;
sl : in STD_LOGIC_vector(1 downto 0);
y : out STD_LOGIC);
end Multiplexer_021304;
architecture Behavioral of Multiplexer_021304 is
Begin
process(i3,i2,i1,i0,sl) begin
case sl is
when "00"=>y<=i3;
when "01"=>y<=i2;
when "10"=>y<=i1;
when "11"=>y<=i0;
when others=>null;
end case;
end process;
end Behavioral;
RTL SCHEMATIC DIAGRAM:
Timing Diagram:
4.2. 4:1 Demultiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Demultiplexer_021304 is
Port ( data : in STD_LOGIC;
sl : in STD_LOGIC_VECTOR(1 downto 0);
q3 : out STD_LOGIC;
q2 : out STD_LOGIC;
q1 : out STD_LOGIC;
q0 : out STD_LOGIC);
end Demultiplexer_021304;
architecture Behavioral of Demultiplexer_021304 is
begin
process(data,sl) begin
case sl is
when "00"=>q3<=data;
when "01"=>q2<=data;
when "10"=>q1<=data;
when "11"=>q0<=data;
when others=>null;
end case;
end process;
end Behavioral;D
RTL SCHEMATIC DIAGRAM:
Timing Diagram: