EIE/IC&E-S4

Digital Questions

Number Systems and Code

1. Subtract (5C)16 from (94)16. (2)

2. Convert (614)8 to decimal. (2)
3. Subtract 75 from 26 using 2’s complement method. (2)
4. Convert the following binary code into gray code: 101101. (2)
5. Perform the following arithmetic: (6)
(a) −14 − 17 by using 2’s complement.
(b) 25 − 19 by using 2’s complement.
(c) Decimal 55.35 to binary.
6. Perform the following subtraction using 2’s complement method: (4)
(a) (16)10 − (12)10
(b) (10)10 − (16)10
7. Perform the following conversion: (6)
(a) (2536)16 = (? )8
(b) (101101.101)2 = (? )8
(c) (25.625)8 = (? )10
(d) (1101001.11)2 = (? )16

Boolean Algebra & Logic Gates

1. Distinguish between: (4)

(a) Saturated and unsaturated logic,
(b) Positive and Negative logic.
2. Why NAND and NOR gates are called universal gates? Justify your answer with at least two
examples. (4)
3. Write the Boolean expressions for a six-input OR gate. (2)
4. How can you get Boolean expression from truth table? Explain with proper example. (4)
5. Describe the operation of Ex-OR gate as a controlled inverter. (2)
6. What is meant by fan out? (2)
7. Why ECL is faster than TTL? (2)
8. Draw the circuit diagram of TTL NAND gate. (4)
9. State and prove the DeMorgan’s theorems. (4)
10. Write down the postulates of Boolean algebra. (2)
11. Define: Propagation delay and Noise margin. (2)
12. Define fan in and fan out of a logic family. (2)

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Digital Questions

Combinational Logic Circuits

1. Draw the logic circuit for the POS expression. (2)

2. What do you mean by SOP and min terms? (2)
3. What do you mean by the following terms: (6)
(a) Max and Min terms, and
(b) Canonical SOP and POS form?
4. Design a full adder circuit by using NAND gates only. (6)
5. How you should implement full adder by using 2 half adder and an OR gate? (4)
6. Design a full adder circuit using logic gates. (6)
7. Design a adder/subtractor by using 4-bit Binary Parallel Adder. (6)
8. Design a BCD adder by using 4-bit Binary Parallel Adder. (5)
9. Draw the circuit diagram of a 4-bit BCD adder and explain the operation. (7)
10. What is meant by priority encoder? (2)
11. What is encoder? Give examples. (2)
12. Describe the operation of 4:2 encoder and design the logic diagram. (3)
13. Show that we can implement any Boolean function by using suitable decoder and OR gates
only (with suitable example). (6)
14. A decoder with enable input can act as a Demultiplexer – explain. (4)
15. Design a 3:8 decoder with enable input. Show that you can implement full adder circuit by
using this decoder. (6+4)
16. Design a logic circuit of a 2 bit magnitude comparator. (4)
17. Design 4-bit comparator which can compare two 4-bits number. (8)
̅̅̅̅̅
18. Simplify: 𝑝 = (𝑥̅ 𝑦̅𝑧) + 𝑧 + 𝑥𝑦 + 𝑤𝑥. (3)
̅ ̅ ̅ ̅ ̅
19. Simplify using Boolean algebra: 𝐴𝐵𝐶 + 𝐴𝐵𝐶 + 𝐴𝐵𝐶 + 𝐴𝐵𝐶. (3)
20. Convert AC+B into standard canonical form. (4)
21. Simplify the following using K-maps and implement it using basic gates only:
𝑓(𝑎, 𝑏, 𝑐, 𝑑) = ∑ 𝑚(0,1,3,4,5,7,10,13,14,15) (5)
22. Simplify the following using K-maps and implement it using basic gates only:
𝑓(𝑃, 𝑄, 𝑅, 𝑆) = Π𝑀(1,3,8,10,12,13,14,15) (5)
23. Simplify the following expression using K-map and implement the simplified expression
using NAND gates only: 𝑓(𝐴, 𝐵, 𝐶, 𝐷) = ∑ 𝑚(0,1,4,6,7,10,11,12,13,15) + ∑ 𝑑(2,5,9,14) (10)
24. Simplify the following by using K-map: (4+4)
(a) 𝑓(𝐴, 𝐵, 𝐶, 𝐷) = ∑ 𝑚(3,4,5,7,9,13,14,15) + 𝑑(0,2,8,11)
(b) 𝑓(𝐴, 𝐵, 𝐶, 𝐷) = Π𝑀(0,2,4,6,8,11) + 𝑑(5,14)
25. Simplify the following by using K-map: 𝑓(𝐴, 𝐵, 𝐶, 𝐷) = Π𝑀(0,1,2,3,5,6,7,8,12) (5)
26. Simplify the following by using K-map: (4+4)
(c) 𝑓 = ∑(1,4,5,6,7,8,11,12,13,15)
(d) 𝑓 = Π(2,5,4,7,8,11,12,14)

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 EIE/IC&E-S4
Digital Questions

Multiplexers & Demultiplexers

1. What is multiplexer? (2)

2. Design a 16:1 Multiplexer using 4:1 MUX and OR gate. (3)
3. Design a 16:1 Multiplexer using 8:1 and 2:1 MUX. (3)
4. Design a 4:1 MUX using 2:1 MUX. (3)
5. Design 8:1 MUX using logic gates. (5)
6. Design 8:1 MUX by using 4:1 MUXs only. (5)
7. Design 8:1 MUX with enable input. (5)
8. Implement a full adder using two 4:1 MUX. (4)
9. Show that you can implement full adder circuit by using two 8:1 MUX only. (5)
10. Implement the following functions with an 8:1 MUX
𝑓(𝑊, 𝑋, 𝑌, 𝑍) = ∑ 𝑚(0,1,3,4,5,8,9,15) (5)
11. Implement the following functions with an 8:1 MUX
𝑓(𝐴, 𝐵, 𝐶) = Π𝑀(2,4,5,7) (5)
12. Realize the following expression using multiplexer: 𝑓(𝐴, 𝐵, 𝐶, 𝐷) = ∑ 𝑚(0,1,3,4,8,9,15) (5)

A/D & D/A Converters

1. Describe the operation of Flash-type ADC. (7)

2. Discuss the advantages and disadvantages of Flash ADC. (3)
3. Describe the operation of dual slope type ADC. What are its advantages? State an
application of this ADC. (8+1+1)
4. Write the advantages of dual slope ADC over ramp type ADC. (2)
5. Describe the operation of successive approximation type ADC. (4)
6. Explain the operation of Binary weighted DAC. (5)
7. Explain the operation of R/2R DAC. (5)
8. State the specification of D/A converter. (2)
9. What do you mean by resolution and dynamic range of a D/A converter? (2)

Timing Circuits

1. Explain the working principle of IC555 timer as monostable multivibrator. (4)

2. Explain the working principle of IC 555 timer as astable multivibrator. (4)

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Digital Questions

Flip Flops & Sequential Logic Design

1. What is the difference between a counter and a shift register? (2)

2. Design a 4-bit PIPO register and explain its operation. (6)
3. Design a 4-bit PISO register and explain its operation. (6)
4. Discuss four types of registers in details. (4)
5. Design a synchronous MOD-3 UP counter using D flip-flops. (5)
6. Design a mod-11 synchronous counter by using JK flip-flops. (10)
7. Design 3-bit synchronous up counter. (6)
8. Design 3-bit synchronous counter. (6)
9. Design a MOD-6 synchronous counter. (6)
10. Design a 3-bit UP-DOWN counter. (6)
11. Explain the operation of divide by N counter. (4)
12. What is the difference between ripple counter and synchronous counter? (2)
13. Explain the operation of 3 bit Johnson counter. (5)
14. Explain the operation of Johnson counter. (5)
15. Explain the operation and data flow of 3 bit bidirectional Serial In Serial Out shift register. (5)
16. Briefly explain the difference between level triggering and edge triggering. (2)
17. Describe the operation of master slave J-K flip-flop. (6)
18. What is race condition? How does it get eliminated in Master-Slave J-K flip-flop? (3+7)
19. What are the ways to avoid race condition – explain. (3)
20. Design a sequence generator to generate the sequence 0-2-3-4-1 and avoid the lockout
condition using J-K flip-flop. (10)
21. Design a BCD to excess-3 code converter. (8)
22. Convert SR flip-flop into JK flip-flop. (4)
23. Convert SR flip-flop into T flip-flop. (4)
24. Explain RAM. (2)
25. What are the differences between RAM and ROM? (3)
26. Why is refreshing required in dynamic RAM? (2)
27. What are the different types of RAM? Explain each type. (5)
28. Explain the operation of three-state ROM. (3)
29. What are the difference between PAL and PLA? (2)
30. What is flash memory? (2)