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LDO Design: Key Specifications Explained

The document discusses the specifications and performance metrics of Low Drop-Out (LDO) regulators, including drop-out voltage, quiescent current, load and line regulation, and power supply rejection ratio (PSRR). It highlights the importance of stability analysis, the impact of noise on output, and the need for LDOs to maintain a stable output under varying conditions. Additionally, it emphasizes the significance of PSRR in rejecting input ripple and the challenges posed by thermal, shot, and flicker noise.

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Sudhansu Mishra
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6 views2 pages

LDO Design: Key Specifications Explained

The document discusses the specifications and performance metrics of Low Drop-Out (LDO) regulators, including drop-out voltage, quiescent current, load and line regulation, and power supply rejection ratio (PSRR). It highlights the importance of stability analysis, the impact of noise on output, and the need for LDOs to maintain a stable output under varying conditions. Additionally, it emphasizes the significance of PSRR in rejecting input ripple and the challenges posed by thermal, shot, and flicker noise.

Uploaded by

Sudhansu Mishra
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Lecture of LDO design

Specifications
An LDO is characterized by its drop-out voltage, quiescent current, load regulation, line
regulation, maximum current (which is decided by the size of the pass transistor), speed
(how fast it can respond as the load varies), voltage variations in the output because of
sudden
P transients in the load current, output capacitor and its equivalent series resistance.
[10] Speed is indicated by the rise time of the current at the output as it varies from 0 mA
S
load current (no load) to the maximum load current. This is basically decided by the
R
bandwidth of the error amplifier. It is also expected from an LDO to provide a quiet and
stable
R output in all circumstances (example of possible perturbation could be: sudden
change of the input voltage or output current). Stability analysis put in place some
=
performance metrics to get such a behaviour and involve placing poles and zeros
Δ
appropriately. Most of the time, there is a dominant pole that arise at low frequencies while
V
other poles and zeros are pushed at high frequencies.
I
N
2Power supply rejection ratio
Δ
PSRR refers to the LDO's ability to reject ripple it sees at its input.[11] As part of its
V
regulation, the error amplifier and bandgap attenuate any spikes in the input voltage that
O
deviate from the internal reference to which it is compared.[12] In an ideal LDO, the output
voltage
U would be solely composed of the DC frequency. However, the error amplifier is
limited in its ability to gain small spikes at high frequencies. PSRR is expressed as follows:
T
[11]
2
=
1
0
As an example, an LDO that has a PSRR of 55 dB at 1 MHz attenuates a 1 mV input
lripple at this frequency to just 1.78 μV at the output. A 6 dB increase in PSRR roughly
oequates to an increase in attenuation by a factor of 2.
g
Most LDOs have relatively high PSRR at lower frequencies (10 Hz – 1 kHz). However, a
⁡Performance LDO is distinguished in having high PSRR over a broad frequency spectrum
((10 Hz – 5 MHz). Having high PSRR over a wide band allows the LDO to reject high-
Δ
frequency noise like that arising from a switcher. Similar to other specifications, PSRR
V
fluctuates over frequency, temperature, current, output voltage, and the voltage differential.
I
Output
N noise
2
Δ
The
V noise from the LDO itself must also be considered in filter design. Like other electronic
devices, LDOs are affected by thermal noise, bipolar shot noise, and flicker noise.[9] Each
O
of these phenomena contribute noise to the output voltage, mostly concentrated over the
U
lower end of the frequency spectrum. In order to properly filter AC frequencies, an LDO
must both reject ripple at the input while introducing minimal noise at the output. Efforts to
T
2
)
d
B
attenuate ripple from the input voltage could be in vain if a noisy LDO just adds that noise
back again at the output.

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