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NET2888 USB Interface Controller Spec

Q: What role does the DMA controller play in the functionality of the NET2888, and how does it enhance performance?

The DMA controller plays a vital role in the NET2888 by facilitating automated data transfers between the local bus and the FIFO, thus offloading the CPU from manual intervention. This automation allows CPU resources to be used for other critical tasks, enhancing overall system performance. For instance, DMA can operate in a "fly-by demand" mode to transfer data only when requested by the NET2888, optimizing usage of the bus bandwidth by reducing unnecessary data movement. This mode allows continuous, high-speed data transfers without frequent CPU interruptions, improving efficiency and throughput in high-volume data applications .

Q: What mechanisms are in place to handle NAK or timeout conditions during bulk transfers in the NET2888 USB controller?

To handle NAK or timeout conditions during bulk transfers, the USB host will send another OUT token for host-to-device transfers, or another IN token for device-to-host transfers, and the NET2888 USB controller should attempt to receive or retransmit the same packet. This mechanism ensures that data can be successfully transferred even if initial attempts fail due to network congestion or other issues .

Q: Describe the process and conditions under which the NET2888 USB controller generates interrupts to the local CPU.

The NET2888 USB controller generates interrupts to the local CPU under several conditions. For instance, when the transmit FIFO becomes empty, signaled by an EOP (end of packet), an interrupt can be generated. Similarly, for receiving data, when the receive mailbox valid bit is set, it indicates data has been written by the host, prompting an interrupt. Additionally, when the FIFO reaches specific thresholds, such as almost full or empty, interrupts can be enabled to alert the CPU for timely action. These interrupts help manage the flow of data efficiently and ensure that data is processed promptly .

Q: How does the NET2888 USB controller utilize FIFO status registers to manage data flow and integrity?

The NET2888 USB controller uses FIFO status registers to manage data flow and integrity effectively. These registers indicate the current state of the FIFOs, such as whether they are full, empty, or nearing their capacity (almost full or almost empty). The local CPU can read these status bits to decide when to read from or write to the FIFO, thereby preventing overflow or underflow conditions. Additionally, these status registers can trigger interrupts that notify the CPU when certain thresholds are met, ensuring timely processing of data and maintaining data integrity across transfers .

Q: Analyze how the specification of the NET2888 ensures reliability in transferring 8-byte packets through its endpoint mailboxes.

The NET2888 specification ensures reliable transfer of 8-byte packets through its endpoint mailboxes by implementing several mechanisms. First, the bulk transfer method to endpoint 1 receive mailboxes sets a valid bit after data is written, causing a local bus interrupt. This bit must be cleared before another packet is accepted, preventing overwrites. Similarly, transmit mailboxes (endpoint 2) only allow data to be sent after previous data has been acknowledged. These measures guarantee sequential and reliable processing, with error handling (e.g., NAKs) ensuring packets are retransmitted as necessary .

Q: Evaluate the function of threshold registers in the NET2888 controller and their impact on data processing efficiency.

Threshold registers in the NET2888 controller, such as the Receive FIFO Almost Full Threshold and the Transmit FIFO Almost Empty Threshold, are critical for optimizing data processing efficiency. These registers define specific points at which interrupts are triggered, signaling the CPU to take corrective action before an overflow (for receiving) or an underflow (for transmitting) occurs. By preemptively alerting the CPU based on these thresholds, the system can manage data flows more effectively, reduce idle times waiting for data availability, and ensure that the FIFO is optimally utilized without data loss or delays .

Q: Explain the role of the EOT# signal in terminating a DMA transfer in the context of the NET2888 USB interface controller.

The EOT# signal is used to halt a DMA transfer within the NET2888 USB interface controller. It is typically provided by an external DMA controller and should be asserted while DACK# and IOR# or IOW# are simultaneously active to indicate that DMA activity has stopped. Despite the EOT# signal indicating the end of DMA transfer, the USB transfer isn't considered complete until the last byte is transferred from the FIFO to the USB bus. The EOT# signal also resets the DMA request enable bit in the NET2888, ensuring no further DMA requests are made. If the EOT# signal is not provided, DMA transfers can be halted manually by resetting the NET2888's DMA request enable bit .

Q: How does the NET2888 USB controller manage data flow when the local CPU stalls an endpoint during a transfer?

If the local CPU stalls an endpoint during a transfer, the NET2888 USB controller will not store any data into the FIFO and will respond with a STALL acknowledge to the USB host. This action is taken to prevent data overflow and ensure that data is processed in an orderly manner while indicating to the host that data cannot currently be accepted .

Q: What is the significance of the data toggle bits for endpoints in the NET2888 USB controller?

In the NET2888 USB controller, the data toggle bits for endpoints are significant for maintaining data transfer synchronization and integrity. Each endpoint has a data toggle bit that is used to indicate which data packet should be acknowledged (ACK) or negative-acknowledged (NAK) by the USB host. This helps in managing the sequence of data packets and ensures that if a packet is lost or corrupted, it is retransmitted. The data toggle mechanism prevents data duplication and ensures data continuity in the transfer process .

Q: In the context of the NET2888, how does the local CPU ensure that new data can be transmitted to the USB host without overwriting unread data?

The local CPU ensures new data is not overwritten by monitoring the Transmit FIFO Count register, which indicates the number of entries in the transmit FIFO. Before writing new data, the CPU must verify that there is enough space available in the FIFO. If the FIFO is full, the CPU must wait until space becomes available or risk overwriting unread data. This system prevents the data integrity issues that could arise from FIFO overflow .

The document provides the specifications for the NET2888 USB Interface Controller, detailing its features, functionalities, and revisions. It includes information about the device's compliance with USB specifications, data transfer capabilities, and local bus interface. The document also outlines the changes made from previous revisions, including modifications to register values and functional corrections.

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NET2888 USB Interface Controller Spec

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NetChip

Technology, Inc.
335 Pioneer Way
Mt View, California 94041
(650) 526-1490 Fax (650) 526-1494
e-mail: sales@[Link]
Internet: [Link]

NET2888 USB Interface Controller

Specification
for NET2888 Revision 3 IC

Doc #: 605-0002-0300
Revision: 3.0
Date: 12 / 17 / 97
Specification NET2888 USB Interface controller

This document contains material that is confidential to NetChip. Reproduction without the express written
consent of NetChip is prohibited. All reasonable attempts were made to ensure the contents of this
document are accurate, however no liability, expressed or implied is guaranteed. NetChip reserves the
right to modify this document, without notification, at any time.

Revision History

Revision Issue Date Comments

1.0 May 7, 1997 NET2888 Engineering Sample Specification
2.0 Draft 1 May 7, 1997 Initial Release for NET2888 Rev 2 Silicon
2.0 Draft 2 May 13, 1997 Add FIFO thresholds and interrupts, and USB string enable
2.0 Draft 3 June 13, 1997 Add some extended registers, add FIFO valid bit to EP4STAT,
TOGGLE bits
2.0 August 1, 1997 Final NET2888 Rev2 Specification.
2.1 November 19, 1997 Improved local bus timing specifications. Clarify USB Status
Register descriptions
3.0 December 17, 1997 Final NET2888 Rev3 Specification.

____________________________________________________________________________________ 2
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335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
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Specification NET2888 USB Interface controller

NET2888 USB Interface Controller

1. Highlights .............................................................................................................................................6
1.1 Features...........................................................................................................................................6
1.2 Overview.........................................................................................................................................6
1.3 NET2888 Block Diagram ................................................................................................................7
1.4 NET2888 Typical System Block Diagram........................................................................................7
1.5 Changes from Rev 2 to Rev 3 ..........................................................................................................8
1.5.1 Pin Changes..............................................................................................................................8
1.5.2 Register Changes ......................................................................................................................8
1.5.3 Functional Changes ..................................................................................................................8
1.6 Changes From Rev 1 to Rev 2..........................................................................................................8
1.6.1 Pin Changes..............................................................................................................................8
1.6.2 Register Changes ......................................................................................................................8
1.6.3 Functional Changes ..................................................................................................................9
2. Pin Connection Diagram .....................................................................................................................10
3. Pin Description ...................................................................................................................................11
4. Functional Description ........................................................................................................................14
4.1 USB Interface................................................................................................................................14
4.2 Local Bus ......................................................................................................................................14
4.2.1 CPU Controlled USB to Local Bus Transfers ..........................................................................14
4.2.2 CPU Controlled Local Bus to USB Transfers ..........................................................................15
4.2.3 DMA Controlled USB to Local Bus Transfers.........................................................................15
4.2.4 DMA Controlled Local Bus to USB Transfers.........................................................................16
4.2.5 Terminating DMA Transfers ..................................................................................................16
4.2.6 USB Endpoint 1 Receive Mailboxes........................................................................................16
4.2.7 USB Endpoint 2 Transmit Mailboxes......................................................................................16
4.3 Suspend Mode ...............................................................................................................................17
4.3.1 The Suspend Sequence............................................................................................................17
4.3.2 Device-Remote Wake-Up........................................................................................................17
4.3.3 Host-Initiated Wake-Up ..........................................................................................................17
4.4 NET2888 Power Configuration .....................................................................................................17
4.4.1 Bus-Powered Device ...............................................................................................................18
4.4.2 Self-Powered Device ...............................................................................................................18
5. Local Registers....................................................................................................................................19
5.1 Register Description ......................................................................................................................19
5.2 Register Summary .........................................................................................................................19
5.3 (Address 00h; DCTL) DMA Control Register................................................................................20
5.4 (Address 01h; IRQENB1) Interrupt Enable Register 1 ...................................................................20
5.5 (Address 02h; IRQSTAT1) Interrupt Status Register 1 ..................................................................22
5.6 (Address 03h; IRQENB2) Interrupt Enable Register 2 ...................................................................22
5.7 (Address 04h; IRQSTAT2) Interrupt Status Register 2 ..................................................................22
5.8 (Address 08h; EP1IDX) Endpoint 1 Index Register .......................................................................23
5.9 (Address 09h; EP1DATA) Endpoint 1 Receive Mailbox Data........................................................23
5.10 (Address 0Ch; EP2IDX) Endpoint 2 Index Register.....................................................................23
5.11 (Address 0Dh; EP2DATA) Endpoint 2 Transmit Mailbox Data...................................................24
5.12 (Address 0Eh; EP2POLL) Endpoint 2 Interrupt Polling Interval Register ....................................24
____________________________________________________________________________________ 3
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Specification NET2888 USB Interface controller

5.13 (Address 10h; EP3DATA) Endpoint 3 Receive FIFO Data Register.............................................24

5.14 (Address 11h; EP3COUNT) Endpoint 3 Receive FIFO Count Register ........................................24
5.15 (Address 12h; EP3STAT) Endpoint 3 Receive FIFO Status Register............................................24
5.16 (Address 13h; EP3PKSZ) Endpoint 3 Maximum Packet Size Register.........................................25
5.17 (Address 14h; EP4DATA) Endpoint 4 Transmit FIFO Data Register...........................................25
5.18 (Address 15h; EP4COUNT) Endpoint 4 Transmit FIFO Count Register ......................................25
5.19 (Address 16h; EP4STAT) Endpoint 4 Transmit FIFO Status Register..........................................25
5.20 (Address 17h; EP4PKSZ) Endpoint 4 Maximum Packet Size Register.........................................25
5.21 (Address 18h; REVISION) Revision Register ..............................................................................26
5.22 (Address 19h; USBSTAT) USB Status Register...........................................................................26
5.23 (Address 1Ah; FRAMEMSB) Frame Counter MSB Register .......................................................26
5.24 (Address 1Bh; FRAMELSB) Frame Counter LSB Register..........................................................26
5.25 (Address 1Ch; EXTIDX) Extended Register Index ......................................................................27
5.26 (Address 1Dh; EXTDATA) Extended Register Data....................................................................27
5.26.1 (Address 1Dh, Index 00h; VIDMSB) Vendor ID MSB..........................................................27
5.26.2 (Address 1Dh, Index 01h; VIDLSB) Vendor ID LSB ............................................................27
5.26.3 (Address 1Dh, Index 02h; PIDMSB) Product ID MSB ..........................................................27
5.26.4 (Address 1Dh, Index 03h; PIDLSB) Product ID LSB ............................................................27
5.26.5 (Address 1Dh, Index 04h; RELMSB) Release Number MSB.................................................27
5.26.6 (Address 1Dh, Index 05h; RELLSB) Release Number LSB ...................................................28
5.26.7 (Address 1Dh, Index 06h; RCVAFTH) Receive FIFO Almost Full Threshold .......................28
5.26.8 (Address 1Dh, Index 07h; XMTAETH) Transmit FIFO Almost Empty Threshold ................28
5.26.9 (Address 1Dh, Index 08h; USBCTL) USB Control................................................................28
5.26.10 (Address 1Dh, Index 09h; MAXPWR) Maximum Power Consumption...............................28
5.26.11 (Address 1Dh, Index 0Ah; PKTCTL) Packet Control..........................................................29
5.26.12 (Address 1Dh, Index 0Bh; LOCALCTL) Local-Side Control ..............................................29
5.26.13 (Address 1Dh, Index 0Ch; FIFOCTL) FIFO Control ...........................................................29
6. Standard Device Requests ...................................................................................................................30
6.1 Control ‘IN’ Transactions..............................................................................................................30
6.1.1 Get Device Status....................................................................................................................30
6.1.2 Get Interface Status.................................................................................................................30
6.1.3 Get Endpoint 0,1,2,3,4 Status .................................................................................................30
6.1.4 Get Device Descriptor (18 Bytes) ............................................................................................30
6.1.5 Get Configuration Descriptor (46 bytes)..................................................................................31
6.1.6 Get String Descriptor 0 ...........................................................................................................33
6.1.7 Get String Descriptor 1 ...........................................................................................................33
6.1.8 Get String Descriptor 2 ...........................................................................................................33
6.1.9 Get Configuration ...................................................................................................................33
6.1.10 Get Interface .........................................................................................................................33
6.2 Control ‘OUT’ Transactions ..........................................................................................................34
6.2.1 Set Address.............................................................................................................................34
6.2.2 Set Configuration....................................................................................................................34
6.2.3 Set Interface............................................................................................................................34
6.2.4 Device Clear Feature...............................................................................................................34
6.2.5 Device Set Feature ..................................................................................................................34
6.2.6 Endpoint 0,1,2,3,4 Clear Feature ............................................................................................34
6.2.7 Endpoint 0,1,2,3,4 Set Feature ................................................................................................34
6.3 Endpoint 1 ‘OUT’ Transactions (Receive Mailboxes) ....................................................................35
6.4 Endpoint 2 ‘IN’ Transactions (Transmit Mailboxes)......................................................................35
6.5 Endpoint 3 ‘OUT’ Transactions (Receive FIFO)............................................................................35
6.6 Endpoint 4 ‘IN’ Transactions (Transmit FIFO) .............................................................................35
7. Vendor Device Requests......................................................................................................................35
7.1 Device Clear Feature .....................................................................................................................35

____________________________________________________________________________________ 4
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Specification NET2888 USB Interface controller

7.2 Device Set Feature.........................................................................................................................35

8. Electrical Specifications ......................................................................................................................36
8.1 Absolute Maximum Ratings ..........................................................................................................36
8.2 Recommended Operating Conditions.............................................................................................36
8.3 DC Specifications..........................................................................................................................37
8.3.1 Core DC Specifications...........................................................................................................37
8.3.2 USB Port DC Specifications....................................................................................................37
8.3.3 Local Bus (+3.3V) DC Specifications......................................................................................38
8.3.4 Local Bus (+5.0V) DC Specifications......................................................................................38
8.4 AC Specifications..........................................................................................................................39
8.4.1 USB Port AC Specifications....................................................................................................39
8.4.2 USB Port AC/DC Specification Notes .....................................................................................40
8.4.3 USB Port AC Waveforms........................................................................................................40
8.4.4 Local Bus Write to Register ....................................................................................................42
8.4.5 Local Bus Read from Register.................................................................................................43
8.4.6 DMA Write to FIFO ...............................................................................................................44
8.4.7 DMA Read from FIFO............................................................................................................45
9. Mechanical Drawing ...........................................................................................................................46

____________________________________________________________________________________ 5
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335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
[Link]
Specification NET2888 USB Interface controller

1. Highlights

1.1 Features

• USB Specification Version 1.0 Compliant

• Bridges between a Processor-Independent local bus and a USB bus
• USB device bandwidth of up to 12Mb/sec
• USB Bulk, Isochronous, Interrupt, and Control transfers.
• Independent 64 byte transmit and receive FIFOs to maximize throughput.
• Supports local CPU or DMA data transfers.
• Low power CMOS in 48-Pin Plastic QFP Package
• 3.3V operating voltage

1.2 Overview

The NET2888 USB Interface Controller allows bulk or isochronous data transfers between a
generic local bus and a Universal Serial Bus (USB). The NET2888 supports the connection
between a host computer and an intelligent peripheral such as a digital camera or scanner.
The three main components of the NET2888 are the USB Bus Interface, the dual 64 byte FIFOs,
and a Local Bus Interface.
The USB Interface is responsible for the following functions:

• Host to device Communication

• Bulk or isochronous endpoints to access FIFOs
• Interrupt endpoint to access Local to USB Mailboxes
• Bulk endpoint to access USB to Local Mailboxes

The Local Bus Interface is responsible for the following functions:

• FIFO Control
• Local CPU interface
• Local DMA controller interface
• Interrupts

____________________________________________________________________________________ 6
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Specification NET2888 USB Interface controller

1.3 NET2888 Block Diagram

D[7:0] 64 Byte
A[4:0] Receive FIFO

CS#
IOR#
64 Byte
IOW# Transmit FIFO
USB Serial D+
DRQ Interface Engine USB PORT
and Controller D-
DACK#
8-Byte Mailbox,
Bulk Endpoint
EOT#
IRQ# Local Bus
Controller
RESET# 8-Byte Mailbox,
Interrupt Endpoint
ISO#
WAKEUP#

SUSP#
DEVCFG#
BUSPWR#
PWRGOOD#
LCLK

LRESET#

1.4 NET2888 Typical System Block Diagram

Scanner/Camera
Shared Memory Microprocessor
Controller

Data Bus

DMA Controller
(Optional)
NET2888

USB PORT

____________________________________________________________________________________ 7
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TEL (650) 526-1490 FAX (650) 526-1494
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Specification NET2888 USB Interface controller

1.5 Changes from Rev 2 to Rev 3

The following changes have been made to the NET2888 from Revision 2 to Revision 3.

1.5.1 Pin Changes

No pin changes.

1.5.2 Register Changes

• Modified default value of VIDMSB, VIDLSB to 0x05, 0x25 to match the Vendor ID assigned to
NetChip by USB-IF.
• Modified default value of RELMSB register to 0x03 for new silicon revision.

1.5.3 Functional Changes

• Corrected a bit-stuffing error caused when a stuffed bit is required after the last data bit of a packet.
• Relaxed Endpoint 0 stall clearing: any SETUP packet clears a STALL condition on Endpoint 0.

1.6 Changes From Rev 1 to Rev 2

The following changes have been made to the NET2888 from Revision 1 to Revision 2.

1.6.1 Pin Changes

CLKOUT: The oscillator stops during a suspend.
RESET#: Must assert for at least one ms when oscillator is stopped.
D[7:0]: Removed pull-up resistors.
A[4:0]: Removed pull-up resistors.
DRQ: Not driven during suspend.
IRQ#: Removed pull-up resistor.
USBOE#: Added pull-up resistor, not driven during suspend.
DEVCFG#: Added pull-down resistor, not driven during suspend.
SUSP#: Added pull-down resistor, not driven during suspend.
LRESET#: Added pull-up resistor, not driven during suspend.
LCLK: Added pull-down resistor, not driven during suspend.
ISO#: Removed pull-up resistor.
BUSPWR#: Removed pull-up resistor.
PWRGOOD#: Removed pull-up resistor.

1.6.2 Register Changes

IRQENB1: Added SOF interrupt, Suspend-Request interrupt, removed global interrupt
enable.
IRQSTAT1: Added SOF interrupt, Suspend-Request interrupt, removed global interrupt
enable.
IRQENB2: Added FIFO threshold interrupts.
IRQSTAT2: Added FIFO threshold interrupts.
USBSTAT: Replace Suspended bit with Suspend Control bit.
FRAMEMSB: Added.
FRAMELSB: Added.

____________________________________________________________________________________ 8
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Specification NET2888 USB Interface controller

EXTIDX: Added.
EP4STAT: Added EP4 Valid bit
EXTDATA: Added the following extended data registers
VIDMSB: Vendor ID MSB
VIDLSB: Vendor ID LSB
PIDMSB: Product ID MSB
PIDLSB: Product ID LSB
RELMSB: Release Number MSB
RELLSB: Release Number LSB
RCVAFTH: Receive FIFO Almost Full Threshold
XMTAETH: Transmit FIFO Almost Empty Threshold
STRCTL: USB Descriptor String Control
FIFOCTL: FIFO control register
MAXPWR: Maximum power-consumption register

1.6.3 Functional Changes

• Oscillator stops during suspend mode.
• Several outputs are not driven during suspend, including LCLK.
• USB enable bit prevents device descriptor reads and configuration descriptor reads.
• Suspend operation enhanced (see section 4.3), including ability to force device suspend from register
(USBSTAT, bit 7).
• Added capability to read USB frame number (see FRAMEMSB, FRAMELSB registers).
• Added capability to modify configuration information reported by device descriptor (see EXTIDX,
EXTDATA registers).
• Added FIFO thresholds and interrupts.
• Added capability to disable USB string descriptors.
• Added new FIFO mode – see the FIFOCTL register
• Updated and clarified DC Specifications.

____________________________________________________________________________________ 9
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Specification NET2888 USB Interface controller

2. Pin Connection Diagram

VDD(LOCAL)
WAKEUP#

DEVCFG#
LRESET#

USBOE#
RESET#

SUSP#

TEST

IRQ#
ISO#

VDD
VSS
36

25
VDD 37 24 VSS

A0 38 23 PWRGOOD#

A1 39 22 BUSPWR#

A2 40 21 EOT#

A3 41 20 DACK#

A4 42
NET 2888 19 DRQ
QFP12 - 48 pin
43 18
VDD
(Top View) IOW#

CLK IN 44 17 IOR#

CLK OUT 45 16 LCLK

VSS 46 15 CS#

NC 47 14 D0

VSS 48 13 VDD
10

12
1

9
VDD

VSS
D1
DM
NC

____________________________________________________________________________________ 10
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Specification NET2888 USB Interface controller

3. Pin Description
Pin Type Description
I Input
O Output
I/O Bi-Directional
S Schmitt Trigger
TS Tri-State
TP Totem-Pole
OD Open-Drain
PD 50K Pull-Down
PU 50K Pull-Up
# Active low

NOTE: Input pins that do not have an internal pull-up or pull-down resistor (designated by PU or PD in
the ”Type” column below) must be driven externally when the Net2888 is in the suspended state.

Signal Name Pin Type Description

CLKIN 44 I 48 MHz Oscillator input. Connect to 48 MHz crystal.

CLKOUT 45 O 48 MHz Oscillator output. Connect to 48 MHz crystal. The
oscillator stops when the device is suspended by the USB Host.
RESET# 35 I,S, PU Reset. External reset. Connect to local or power-on reset. To reset
when oscillator is stopped (initial power-up or in suspend state),
assert for at least one ms. When oscillator is running, assert for at
least five 48-MHz clock periods.
DP,DM 3,4 I/O USB Data Port
DP and DM are the differential data signals of the USB data port
NOTE: An external 1.5 KΩ resistor must be connected from DP to
3.3V. This pull-up resistor indicates to the host or upstream hub that
a full-speed device is connected to the USB.
D[7:0] 5-11, I/O, 12mA, Data Bus. The bi-directional 8-bit data bus is used by devices on the
14 TS local bus to read or write registers or the FIFO in the NET2888. D7
is the most-significant bit.
A[4:0] 42-38 I Address Bus. The local address bus is used by devices on the local
bus to select registers within the NET2888.
CS# 15 I, PU Chip Select. The chip select is used by devices on the local bus to
enable access to registers within the NET2888. This signal is ignored
if DACK# is asserted.
IOR# 17 I, PU I/O Read. The I/O read strobe is asserted along with CS# and A[4:0]
when a device on the local bus reads from an internal register or the
FIFO. It also allows the FIFO to be read during DMA transfers when
DACK# is asserted.

____________________________________________________________________________________ 11
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Specification NET2888 USB Interface controller

IOW# 18 I, PU I/O Write. The I/O write strobe is asserted along with CS# and
A[4:0] when a device on the local bus writes to an internal register or
the FIFO. It also allows the FIFO to be written during DMA transfers
when DACK# is asserted.
DRQ 19 O, 12mA, DMA Request. This signal indicates to an external DMA controller
TP that a byte should be transferred to/from the FIFO. During a transfer,
DRQ remains asserted until the DACK# input goes active. This
output floats when the device is suspended by the USB Host.
DACK# 20 I, PU DMA Acknowledge. This signal from the external DMA controller
is used to transfer data to/from the FIFO in response to DRQ. IOR#
and IOW# determine the direction of the DMA transfer.
EOT# 21 I, PU End of Transfer. This signal from the external DMA controller is
used to terminate a DMA transfer. If it is asserted during a DMA
cycle, the current byte will be transferred, but no additional bytes will
be requested. EOT# can be programmed to cause a USB interrupt.
IRQ# 26 O, 12mA, Interrupt Request Output. The interrupt request output is used to
OD interrupt a processor on the local bus. There are several sources of
this interrupt which are described in the Register Description Section.
USBOE# 27 O, 12mA, USB Port Output Enable. This active low output is true when the
TP, PU NET2888 is driving the USB port data lines. This signal is not driven
while the device is suspended, but will be pulled high by the internal
pull-up resistor.
DEVCFG# 28 O, 12mA, Device Configured. This active low output is true when the
TP, PD NET2888 has been configured by the USB host. This signal is not
driven while the device is suspended, but will be pulled low by the
internal pull-down resistor.
SUSP# 33 O, 12mA, Device Suspended. This active low output is true when the
TP, PD NET2888 has been suspended by the USB host. This signal is not
driven while the device is suspended, but will be pulled low by the
internal pull-down resistor.
LCLK 16 O, 12mA, Local Clock. This pin is a buffered output from the internal 48 MHz
TP, PD oscillator. This signal is not driven while the device is suspended, but
will be pulled low by the internal pull-down resistor.
LRESET# 32 O, 12mA, Local Reset. This active low output is asserted when either the
TP, PU RESET# pin is asserted, or a USB port reset is detected. This signal is
not driven while the device is suspended, but will be pulled high by
the internal pull-up resistor.
ISO# 29 I Isochronous Mode Select. This active low input selects isochronous
mode for USB transfers to and from the FIFOs.
WAKEUP# 34 I, PU Wakeup. This active low input causes the NET2888 to perform a
USB remote wakeup.
BUSPWR# 22 I Bus Powered. This active low input indicates that the logic external
to the NET2888 is powered by the USB bus. If this input is high,
then the external logic is self-powered.

____________________________________________________________________________________ 12
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Specification NET2888 USB Interface controller

PWRGOOD# 23 I Power Good. This active low input indicates that an external power
supply used for self-powered mode is operational.
TEST 30 I, PD Test. For normal operation, connect this pin to ground.
NC 2, 47 -- No connect.
VDD 1, 13, Power Core Supply Voltage. Connect this pin to the +3.3V supply voltage
(USB, Core) 25, to supply the core and the USB interface.
37,43
VDD 31 Power Local Supply Voltage. Connect this pin to the +3.3V or +5.0V
(Local) supply voltage to supply the local interface.
VSS 12, 24, GND Device Ground. Connect this pin to ground.
36,
46,48

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Specification NET2888 USB Interface controller

4. Functional Description

4.1 USB Interface

The NET2888 is a USB function device, and as a result is always a slave to the USB host. All USB data
transfers to and from the NET2888 USB port are initiated by the USB host. There are five USB endpoints
associated with the NET2888:

• Endpoint 0. This control endpoint is used to initialize the device, and provides access to USB
configuration, control and status registers.
• Endpoint 1. This endpoint supports bulk transfers from the USB host to the NET2888 receive
mailboxes.
• Endpoint 2. This endpoint supports interrupt transfers from the NET2888 transmit mailboxes to the
USB host.
• Endpoint 3. This endpoint supports bulk or isochronous data transfers from the USB host to the
NET2888 Receive FIFO.
• Endpoint 4. This endpoint supports bulk or isochronous data transfers from the NET2888 Transmit
FIFO to the USB host.

4.2 Local Bus

Bulk or isochronous data passes between the local bus and the USB bus through a pair of 64 byte FIFOs.
A CPU on the local bus can provide data to or accept data from the USB bus via the FIFOs in the
NET2888. A pair of 8-byte mailbox registers provide a means for the local and host CPUs to exchange
messages. The receive mailbox is implemented as a Bulk Data endpoint, and the transmit mailbox as an
Interrupt endpoint.

4.2.1 CPU Controlled USB to Local Bus Transfers

For host to device transfers, the local and host CPUs first arrange to transfer a block of data from host
memory to local shared memory. The USB host performs a bulk or isochronous data transfer over the
USB bus to the receive FIFO in the NET2888.

If the interrupt status bit from the previous packet is not cleared, then the NET2888 will return a USB
NAK acknowledge to the host, signaling that the data could not be accepted. If the FIFO fills up during
an ISO transfer, the endpoint NAK status bit will be set in the USB Status Register, but no handshaking to
the host will occur.

If the local CPU has stalled this endpoint, the NET2888 will not store any data into the FIFO, and will
respond with a STALL acknowledge.

The local CPU can either start polling for valid FIFO data immediately after setting up the transfer with
the USB host, or can wait for a packet complete interrupt. As the FIFO is filling up from the USB side,
the local CPU can poll the FIFO status register to determine when a byte is available. Otherwise it can
wait until the packet complete interrupt and read the entire packet at once.

Once an end of packet occurs, an interrupt can be generated to the local CPU. The local CPU can read a
status port to detect whether the packet was acknowledged with an ACK, NAK, or STALL. If none of
these acknowledge bits are set, then a timeout has occurred. For NAK or timeout conditions at the
completion of bulk transfers, the USB host will send another OUT token, and the NET2888 should receive
the same packet again.

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Specification NET2888 USB Interface controller

4.2.2 CPU Controlled Local Bus to USB Transfers

For device to host transfers, the local CPU first writes the data block from local memory into the transmit
FIFO. While writing data into the NET2888, the local CPU must keep track of whether there is space
available in the FIFO by monitoring the Transmit FIFO Count register.

After the block has been loaded into the transmit FIFO, the local and host CPUs arrange to transfer the
block of data from the transmit FIFO to host memory. The USB host sends an IN token to the NET2888
and starts a USB bulk or isochronous read from the transmit FIFO. The CPU writes and USB read
operations could occur concurrently if the local CPU can provide data at a fast enough rate to keep up with
the USB bus.

When the transmit FIFO becomes empty, the NET2888 will terminate the packet with an EOP (end of
packet), signaling that there is no more data available. Once an end of packet occurs, an interrupt can be
generated to the local CPU. The local CPU can read a status port to detect whether the packet was
acknowledged with an ACK from the host, or whether the NET2888 responded to the IN token with a
NAK or STALL. If none of these acknowledge bits are set, then a timeout has occurred. For NAK or
timeout conditions at the completion of bulk transfers, the USB host will send another IN token, and the
NET2888 should re-transmit the same packet.

4.2.3 DMA Controlled USB to Local Bus Transfers

A Direct Memory Access (DMA) controller may be used on the local bus to transfer data to and from the
NET2888. For host to device transfers, the local and host CPUs first arrange to transfer a block of data
from host memory to local shared memory. The local CPU then programs the DMA controller for fly-by
demand mode transfers. In this mode, transfers occur only when the NET2888 requests them, and the
data is read from the NET2888 receive FIFO and written into local memory during the same bus
transaction. The DMA address counter is programmed to point to the destination memory block in local
shared memory, and the byte count to the number of bytes in the block to be transferred.

After the DMA controller has been programmed, the DMA request enable bit is set in the NET2888. The
USB host performs USB bulk or isochronous data transfers over the USB bus to the receive FIFO in the
NET2888. If the interrupt status bit from the previous packet is not cleared, then the NET2888 will
return a USB NAK acknowledge to the host, signaling that the data could not be accepted. If the FIFO
fills up during an ISO transfer, the endpoint NAK status bit will be set in the USB Status Register, but no
handshaking to the host will occur.

If the local CPU has stalled this endpoint, the NET2888 will not store any data into the FIFO, and will
respond with a STALL acknowledge.

As long as there is data available in the FIFO, the NET2888 will request local DMA transfers by asserting
DRQ. The DMA controller then requests the local bus from the local CPU. After the DMA controller has
been granted the bus, it drives a valid memory address and asserts DACK#, IOR#, and MEMW#, thus
transferring a byte from the NET2888 receive FIFO to memory. This process continues until the DMA
byte count reaches zero. A local bus interrupt may be programmed to occur when the DMA has finished.

An early end-of-packet (EOP) can be detected by the local CPU if the DMA count is non-zero. The local
and host CPUs should then decide how to proceed.
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Specification NET2888 USB Interface controller

4.2.4 DMA Controlled Local Bus to USB Transfers

For device to host transfers, the local and host CPUs first arrange to transfer a block of data from local
memory to host memory. The local CPU then programs the DMA controller for fly-by demand mode
transfers. In this mode, transfers occur only when the NET2888 requests them, and the data is read from
local memory and written into the NET2888 FIFO during the same bus transaction. The DMA address
counter is programmed to point to the source memory block in local memory, and the byte count to the
number of bytes in the block to be transferred. After the DMA controller has been programmed, the DMA
request enable bit is set in the NET2888. As long as there is space available in the FIFO and the byte
count is non-zero, the NET2888 will request DMA transfers by asserting DRQ. The DMA controller then
requests the local bus from the local CPU. After the DMA controller has been granted the bus, it drives a
valid memory address and asserts DACK#, MEMR#, and IOW#, thus transferring a byte from memory to
the NET2888 Transmit FIFO.

After the DMA has been started, the local CPU can signal the USB host to start a bulk read using
endpoint 2. Isochronous packets occur at pre-arranged intervals, so no signaling is required. The USB
host sends an IN token to the NET2888 and starts a USB bulk or isochronous data transfer from the
transmit FIFO. The DMA transfers continue until the DMA byte count reaches zero. An interrupt can be
generated to the local CPU when the DMA has finished.

4.2.5 Terminating DMA Transfers

The EOT# signal is used to halt a DMA transfer, and is typically provided by an external DMA controller.
It should be asserted while DACK# and IOR# or IOW# are simultaneously active to indicate that DMA
activity has stopped. Although an EOT# signal indicates that DMA has terminated, the USB transfer is
not complete until the last byte has been transferred from the FIFO to the USB bus. The EOT# resets the
NET2888 DMA request enable bit.

If no EOT# signal is provided by the DMA controller, the DMA transfer can be halted at any time by
resetting the NET2888 DMA request enable bit. If the NET2888 DMA request enable bit is cleared during
the middle of a DMA cycle, the current cycle will complete before DMA requests are terminated.

4.2.6 USB Endpoint 1 Receive Mailboxes

Endpoint 1 is used for bulk transfers from the USB host to a set of 8 receive mailbox registers which are
read by the local CPU. The format of the data written to the mailbox is user defined. To transfer an 8
byte packet, the host first performs a USB 8-byte bulk transfer to the endpoint 1 receive mailbox registers.
A receive mailbox valid bit (bit 1 of register IRQSTAT1) is then set which can cause a local bus
interrupt. If the USB host tries to write to these registers when the valid bit is set, a NAK acknowledge
will be returned. When the local CPU receives the interrupt, it reads the 8 bytes and clears the valid bit..
The USB host can then send another 8-byte packet to this endpoint. An index pointer is used to access the
receive mailboxes. It must be initialized by the local CPU, and is automatically incremented after the
local CPU reads the receive mailbox data register

4.2.7 USB Endpoint 2 Transmit Mailboxes

Endpoint 2 is used for interrupt transfers to the USB host from a set of 8 transmit mailbox registers which
are written by the local CPU. To transfer an 8 byte packet, the local CPU writes data into the 8 registers
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Specification NET2888 USB Interface controller

and sets the transmit mailbox valid bit. The host performs a USB 8-byte interrupt transfer from the
endpoint 2 transmit mailbox registers. After the USB interrupt transfer has completed, the transmit
mailbox valid bit is cleared. The CPU should only write to the transmit mailbox registers when the valid
bit is not set. This guarantees that a previous interrupt transfer has completed before the register values
are changed. If the USB host tries to read endpoint 2 when the valid bit is not set, a NAK acknowledge is
returned. An index pointer is used to access the transmit mailboxes. It must be initialized by the local
CPU, and is automatically incremented after the local CPU reads or writes the transmit mailbox data
register

4.3 Suspend Mode

When there is a three millisecond period of inactivity on the USB, the USB specification requires a device
to enter into a low-power suspended state. The device may not draw more than 500 µA of current while in
this state. To facilitate this, the NET2888 provides a suspend - request interrupt and a suspend bit in the
USB status register. Additionally, the NET2888 allows the local CPU to send a “device remote wake-up”
request -- a request from the local CPU to wake-up the USB.

4.3.1 The Suspend Sequence

The typical sequence of operation is as follows: during device configuration, the local CPU will configure
the NET2888 to interrupt on a suspend request (using the IRQENB1 register). When the USB is idle for
three milliseconds, the NET2888 will generate a suspend - request interrupt.

The local CPU accepts this interrupt by clearing the corresponding bit in the IRQSTAT1 register, and
performs the tasks required to ensure that not more than 500 µA of current is drawn from the USB power
bus. Then it writes a 1 to bit 7 of the USB status register (USBSTAT) to initiate the suspend.

In suspend mode, the NET2888’s oscillator shuts down, and most output pins are tri-stated to conserve
power (see section 3, Pin Description, above). The SUSP# output pin will be low while the device is in
the suspended state. Note that input pins on the NET2888 which do not have an internal pull-up or pull-
down resistors should not be allowed to float during suspend mode. The NET2888 will leave suspend
mode by detecting traffic on the USB bus or by a device remote wake-up from the local CPU.

4.3.2 Device-Remote Wake-Up

The local CPU signals a device remote wake-up by driving the WAKEUP# input pin low. The NET2888
will send a 10-ms wake-up signal to the USB host, and concurrently re-start its local oscillator. Two
milliseconds after the WAKEUP# pin is asserted, the SUSP# line is driven high to indicate that the
NET2888 has completed its wake-up.

4.3.3 Host-Initiated Wake-Up

The host may wake-up the NET2888 by any non-idle state on the USB. The NET2888 will detect the
host’s wake-up request, and re-start its internal oscillator. Two milliseconds later, the SUSP# output
signal is driven high to indicate that the NET2888 has completed its wake-up.

4.4 NET2888 Power Configuration

The USB specification defines both bus-powered and self-powered devices. A bus-powered device is a
peripheral which derives all of its power from the upstream USB connector, while a self-powered device
has an external power supply. The NET2888 is well-suited for both types of applications.

The most significant consideration when deciding whether to build a bus-powered or a self-powered
device is power consumption. The USB specification lays out the following requirements for maximum
current draw:

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Specification NET2888 USB Interface controller

• A peripheral not configured by the host (signified on the NET2888 by the DEVCFG# output
pin) can draw only 100 mA from the USB power pins.
• A device may not draw more than 500 mA from the USB connector’s power pins.
• In suspend mode, the peripheral may not draw more than 500 µA from the USB connector’s
power pins
If these power considerations can be met without the use of an external power supply, the peripheral can
be bus-powered; otherwise a self-powered design should be implemented.

4.4.1 Bus-Powered Device

If the local bus is powered at 3.3 Volts, the VDD and VDD,LOCAL pins of the device are connected to a 3.3
Volt regulated source derived from the USB 5.0 Volt power pin. For a 5.0 Volt local bus, the VDD,LOCAL
pins may be connected directly to the USB 5.0 Volt power pin, and VDD pins must still be connected to 3.3
Volts through a regulator. The rest of the local-side circuitry is also connected to the USB power pin,
either through a regulator or directly. Therefore, the peripheral’s local circuitry and the NET2888 will all
power up simultaneously, and initialization can occur normally with a power-on reset.

4.4.2 Self-Powered Device

Generally, a peripheral with higher power requirements will be self-powered. In a self-powered device,
the NET2888 VDD and VDD,LOCAL pins of the NET2888 are powered by the local power supply. This allows
the local bus to continue accessing the NET2888, even when the device is not connected to the USB bus.
The USB connector’s power pin is left unconnected.

While the peripheral is connected to the USB, the NET2888 will automatically request suspend mode
when appropriate, as described in section 4.3.

In power-sensitive applications, the NET2888 can be forced to enter low-power suspend mode when
disconnected from the USB. Setting bit 7 of the USBSTAT register when USB power has been removed
forces the NET2888 to enter low-power suspend mode. The NET2888 will automatically wake-up when
the peripheral is re-connected to the USB. Do not force suspend mode unless the peripheral is
disconnected from the USB.

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Specification NET2888 USB Interface controller

5. Local Registers

5.1 Register Description

The NET2888 occupies a 32 byte local register space which can be accessed by a CPU on the local bus.
The Endpoint 1 Receive Mailbox Registers are written by the USB host, and the Endpoint 2 Transmit
Mailbox Registers are read by the USB host. After the NET2888 is powered-up or reset, the registers are
set to their default values.

Writes to unused registers are ignored, and reads from unused registers return a value of 0. For
compatibility with future revisions, unused bits within a register should always be written with a zero.

NOTE: The USB device and configuration descriptors cannot be read by the USB
host until the USBENB bit in the DMA control register is set. Until then, the device
enumeration process cannot complete, so the device will not be recognized on the
USB.

5.2 Register Summary

Address Register Register Description USB
Name Endpoint
0 DCTL DMA Control
1 IRQENB1 Interrupt Enable 1
2 IRQSTAT1 Interrupt Status 1
3 IRQENB2 Interrupt Enable 2
4 IRQSTAT2 Interrupt Status 2
5-7 Reserved
8 EP1IDX Endpoint 1 Index Register
9 EP1DATA Endpoint 1 Receive Mailbox Data Port 1
(USB to Local)
A-B Reserved
C EP2IDX Endpoint 2 Transmit Mailbox Index
Register
D EP2DATA Endpoint 2 Transmit Mailbox Data Port 2
(Local to USB)
E EP2POLL Endpoint 2 Interrupt Polling Interval
F Reserved
10 EP3DATA Endpoint 3 Receive FIFO Data 3
11 EP3COUNT Endpoint 3 Receive FIFO Count
12 EP3STAT Endpoint 3 Receive FIFO Status
13 EP3PKSZ Endpoint 3 Maximum Packet Size
14 EP4DATA Endpoint 4 Transmit FIFO Data 4
15 EP4COUNT Endpoint 4 Transmit FIFO Count
16 EP4STAT Endpoint 4 Transmit FIFO Status
17 EP4PKSZ Endpoint 4 Maximum Packet Size
18 REVISION Chip Revision
19 USBSTAT USB Status
1A FRAMEMSB Frame Counter MSB
1B FRAMELSB Frame Counter LSB
1C EXTIDX Extended Register Index
1D EXTDATA Extended Register Data
1E-1F Reserved

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Specification NET2888 USB Interface controller

5.3 (Address 00h; DCTL) DMA Control Register

Default
Bits Description Read Writ Value
e
7 Reserved. Yes No 0
6 Software EOT. This bit determines the response to an IN request to Endpoint 4 Yes Yes 0
when the transmit FIFO is empty. If either this bit or the DMA EOT input pin are
asserted, the NET2888 responds to an In request to Endpoint 4 with an ACK and a
zero length packet if the FIFO is empty. If neither this bit nor the DMA EOT input
are asserted, the NET2888 responds to an In request from Endpoint 4 with an NACK
if the FIFO is empty, indicating that it expects to transmit more data. This bit can be
cleared by an I/O write with a data value of 0. It is automatically cleared when the
NET2888 responds to the host with a zero length packet when the FIFO is empty.
5 USB Enable. Any device or configuration descriptor reads from the host will be Yes Yes 0
acknowledged with a NAK until this bit is set. This allows time for the local CPU to
set up the interrupt polling register, maximum packet size registers, and other
configuration registers (e.g. Product ID and Vendor ID) before the host reads the
descriptors.
4 Endpoint 4 Stall. If this bit is set, host bulk reads from the transmit FIFO will result Yes Yes 0
in a STALL acknowledge by the NET2888. No data will be returned to the USB
host.
3 Endpoint 3 Stall. If this bit is set, host bulk writes to the receive FIFO will result in Yes Yes 0
a STALL acknowledge by the NET2888. Receive data will be discarded.
2 DMA Request. This status bit reflects the state of the DRQ output pin, and allows a Yes No 0
CPU on the local bus to monitor DMA transfers.
1 DMA Request Enable. Writing a 1 to this bit causes the NET2888 to start Yes Yes 0
requesting DMA cycles from a DMA controller on the local bus. If the EOT# input is
asserted, this bit is automatically reset. A CPU on the local bus may also explicitly
reset this bit to terminate a DMA transfer. This bit can be read to determine whether
a DMA transfer is still in progress.
0 DMA Direction. This bit determines the direction of data flow during a DMA Yes Yes 0
transfer. 1 = Local bus to USB; 0 = USB to Local bus

5.4 (Address 01h; IRQENB1) Interrupt Enable Register 1

Default
Bits Description Read Write Value
7 Suspend Request Interrupt Enable. When set, this bit enables a local interrupt to Yes Yes 0
be set when the USB host is requesting the NET2888 to enter suspend mode.
6 SOF Interrupt Enable. When set, this bit enables a local interrupt to be set when Yes Yes 0
a start-of-frame packet is received by the NET2888.
5 EOT Interrupt Enable. When set, this bit enables the local IRQ signal to be Yes Yes 0
asserted when EOT# signal is received from the DMA controller.
4 Endpoint 4 Interrupt Enable. When set, this bit enables a local interrupt to be set Yes Yes 0
when a USB Endpoint 4 Data Packet has been sent by the NET2888.
3 Endpoint 3 Interrupt Enable. When set, this bit enables a local interrupt to be set Yes Yes 0
when a USB Endpoint 3 Data Packet has been received by the NET2888.
2 Endpoint 2 Interrupt Enable. When set, this bit enables a local interrupt to be set Yes Yes 0
when the USB Endpoint 2 Receive Mailbox registers have been read by the USB
host.
1 Endpoint 1 Interrupt Enable. When set, this bit enables a local interrupt to be set Yes Yes 0
when the USB Endpoint 1 Transmit Mailbox registers have been written to by the
USB host.

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0 Reserved. Yes No 0

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Specification NET2888 USB Interface controller

5.5 (Address 02h; IRQSTAT1) Interrupt Status Register 1

NOTE: These status bits are set independently of the corresponding interrupt enable bits. Writing a 0 to
these bits has no effect.
Default
Bits Description Read Write Value
7 Suspend Request Interrupt Status. This bit indicates when a suspend-request has Yes Yes/CLR 0
been received by the NET2888. This status bit is cleared by writing a 1.
6 SOF Interrupt Status. This bit indicates when a start-of-frame packet has been Yes Yes/CLR 0
received by the NET2888. This status bit is cleared by writing a 1.
5 EOT Interrupt Status. This bit indicates when the EOT# input has been asserted Yes Yes/CLR 0
simultaneously with DACK# and either IOR# or IOW#, indicating the completion
of a DMA transfer. This status bit is cleared by writing a 1.
4 Endpoint 4 Interrupt Status. This bit indicates when a USB Endpoint 4 Data Yes Yes/CLR 0
packet has been sent by the NET2888. This status bit is cleared by writing a 1.
3 Endpoint 3 Interrupt Status (Receive FIFO Valid). This bit indicates when a Yes Yes/CLR 0
USB Endpoint 3 Data packet has been received by the NET2888. No more packets
to endpoint 3 will be accepted until this bit is cleared. This status bit is cleared by
writing a 1.
2 Endpoint 2 Interrupt Status. This bit indicates when the USB Endpoint 2 Yes Yes/CLR 0
Mailbox registers have been read by the USB host. This status bit is cleared by
writing a 1.
1 Endpoint 1 Interrupt Status (Receive Mailbox Valid). This bit indicates when Yes Yes/CLR 0
the USB Endpoint 1 Mailbox registers have been written to by the USB host. This
status bit is cleared by writing a 1.
0 Upper Interrupt Active. At least one interrupt status bit is set in the IRQSTAT2 Yes No 0
register.

5.6 (Address 03h; IRQENB2) Interrupt Enable Register 2

Default
Bits Description Read Write Value
7:2 Reserved. Yes No 0
1 Transmit FIFO Almost Empty Interrupt Enable. When set, this bit enables a Yes Yes 0
local interrupt to be generated when the Transmit FIFO Almost Empty status bit is
set.
0 Receive FIFO Almost Full Interrupt Enable. When set, this bit enables a local Yes Yes 0
interrupt to be generated when the Receive FIFO Almost Full status bit is set.

5.7 (Address 04h; IRQSTAT2) Interrupt Status Register 2

NOTE: These status bits are set independently of the corresponding interrupt enable bits. Writing a 0 to
these bits has no effect.
Default
Bits Description Read Write Value
7:2 Reserved. Yes No 0

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Specification NET2888 USB Interface controller

1 Transmit FIFO Almost Empty Status. This bit is set when the number of bytes Yes Yes/Clr 0
in the Transmit FIFO is equal to the Transmit FIFO Almost Empty Threshold, and
another byte is sent to the USB bus from the FIFO. This status bit is cleared by
writing a 1.
0 Receive FIFO Almost Full Status. This bit is set when the number of bytes in the Yes Yes/Clr 0
Receive FIFO is equal to the Receive FIFO Almost Full Threshold, and another byte
is received from the USB bus into the FIFO. This status bit is cleared by writing a
1.

5.8 (Address 08h; EP1IDX) Endpoint 1 Index Register

Default
Bits Description Read Write Value
7:3 Reserved. Yes No 0
2:0 Endpoint 1 Index Register. This register determines which Endpoint 1 Receive Yes Yes 0
Mailbox is accessed when the Endpoint 1 Receive Mailbox Data port is read. This
register is automatically incremented after the Endpoint 1 Receive Mailbox Data
port is read. This index register wraps around to zero when it reaches the
maximum count.

5.9 (Address 09h; EP1DATA) Endpoint 1 Receive Mailbox Data

Default
Bits Description Read Write Value
7:0 Endpoint 1 Receive Mailbox Data. This port is used to read data from one of the Yes USB 0
receive mailbox registers. Data is returned from the register selected by the
Endpoint 1 Index Register. The eight receive mailbox registers are written by a
USB bulk transfer to endpoint 1, and can be used to pass messages from the USB
host to the local CPU. The format and content of the messages are user defined. If
enabled, USB writes to this register can generate a local interrupt.

5.10 (Address 0Ch; EP2IDX) Endpoint 2 Index Register

Default
Bits Description Read Write Value
7:3 Reserved. Yes No 0
2:0 Endpoint 2 Index Register. This register determines which Endpoint 2 Transmit Yes Yes 0
Mailbox is accessed when the Endpoint 2 Transmit Mailbox Data Port is read or
written. This register is automatically incremented after the Endpoint 2 Transmit
Mailbox Data port is read or written. This index register wraps around to zero
when it reaches the maximum count.

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Specification NET2888 USB Interface controller

5.11 (Address 0Dh; EP2DATA) Endpoint 2 Transmit Mailbox Data

Default
Bits Description Read Write Value
7:0 Endpoint 2 Transmit Mailbox Data. This port is used to read or write one of the Yes Yes 0
transmit mailbox registers. The register being accessed is selected by the Endpoint
2 Index Register. The eight Transmit Mailbox Registers are written by the local
CPU and are read by a USB interrupt transfer from endpoint 2. They can be used to
pass messages from the local CPU to the USB host. The format and content of the
messages are user defined. If enabled, USB reads from this register can generate a
local interrupt.

5.12 (Address 0Eh; EP2POLL) Endpoint 2 Interrupt Polling Interval

Register
Default
Bits Description Read Write Value
7:0 Interrupt Polling Interval Register. This register specifies the Endpoint 2 Yes Yes 0xFF
interrupt polling interval in milliseconds. It can read by the host through the
endpoint 2 descriptor.

5.13 (Address 10h; EP3DATA) Endpoint 3 Receive FIFO Data Register

Default
Bits Description Read Write Value
7:0 Endpoint 3 Receive FIFO Data Register. This register is used by the local CPU Yes No 0
to read data from the USB receive FIFO. The FIFO is written by the USB host
using bulk or isochronous transfers to endpoint 3.

5.14 (Address 11h; EP3COUNT) Endpoint 3 Receive FIFO Count Register

Default
Bits Description Read Write Value
7:0 Receive FIFO Count. This register returns the number of receive FIFO entries Yes No 0
containing valid entries. Values range from 0 (empty) to 64 (full).

5.15 (Address 12h; EP3STAT) Endpoint 3 Receive FIFO Status Register

Default
Bits Description Read Write Value
7:5 Reserved. Yes No 0
4 Receive FIFO Flush. Writing to this bit causes the receive FIFO to be flushed. Yes Yes/Clr 0
Reading this bit always returns a 0.
3 Receive FIFO Overflow. If set, this bit indicates that an attempt was made by the Yes Yes/Clr 0
USB host to write to the receive FIFO when the receive FIFO was full. Writing a 1
clears this bit.
2 Receive FIFO Underflow. If set, this bit indicates that an attempt was made to Yes Yes/Clr 0
read the receive FIFO when the receive FIFO was empty. Writing a 1 clears this
bit.
1 Receive FIFO Full. If set, this bit indicates that the receive FIFO is full. Yes No 0
0 Receive FIFO Empty. If set, this bit indicates that the receive FIFO is empty. Yes No 1

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Specification NET2888 USB Interface controller

5.16 (Address 13h; EP3PKSZ) Endpoint 3 Maximum Packet Size Register

Default
Bits Description Read Write Value
7:0 Endpoint 3 Max Packet Size Register. This register specifies the maximum Yes Yes 0x08
packet size for endpoint 3 in units of 8 bytes (default = 64 bytes). It can be read by
the host through the endpoint 3 descriptor.

5.17 (Address 14h; EP4DATA) Endpoint 4 Transmit FIFO Data Register

Default
Bits Description Read Write Value
7:0 Transmit FIFO Data Register. This register is used by the local CPU to write No Yes 0
data to the transmit FIFO. The FIFO is read by the USB host using bulk or
isochronous transfers from endpoint 4.

5.18 (Address 15h; EP4COUNT) Endpoint 4 Transmit FIFO Count Register

Default
Bits Description Read Write Value
7:0 Transmit FIFO Count. This register returns the number of transmit FIFO entries Yes No 0
containing valid entries. Values range from 0 (empty) to 64 (full).

5.19 (Address 16h; EP4STAT) Endpoint 4 Transmit FIFO Status Register

Default
Bits Description Read Write Value
7:6 Reserved. Yes No 0
5 Transmit FIFO Valid. If set, this bit allows the data in the FIFO to be read by the Yes Yes 0
next read from the host. This bit is automatically cleared by a host read. This bit is
only used if bit 0 in register FIFOCTL is set.
4 Transmit FIFO Flush. Writing to this bit causes the transmit FIFO to be flushed. Yes Yes/Clr 0
Reading this bit always returns a 0.
3 Transmit FIFO Overflow. If set, this bit indicates that an attempt was made by Yes Yes/Clr 0
the local CPU to write to the transmit FIFO when the transmit FIFO was full.
Writing a 1 clears this bit.
2 Transmit FIFO Underflow. If set, this bit indicates that an attempt was made by Yes Yes/Clr 0
the USB host to read the transmit FIFO when the transmit FIFO was empty.
Writing a 1 clears this bit.
1 Transmit FIFO Full. If set, this bit indicates that the transmit FIFO is full. Yes No 0
0 Transmit FIFO Empty. If set, this bit indicates that the transmit FIFO is empty. Yes No 1

5.20 (Address 17h; EP4PKSZ) Endpoint 4 Maximum Packet Size Register

Default
Bits Description Read Write Value
7:0 Endpoint 4 Max Packet Size Register. This register specifies the maximum Yes Yes 0x08
packet size for endpoint 4 in units of 8 bytes (default = 64 bytes). It can be read by
the host through the endpoint 4 descriptor.

____________________________________________________________________________________ 25
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Specification NET2888 USB Interface controller

5.21 (Address 18h; REVISION) Revision Register

Default
Bits Description Read Write Value
7:0 Chip Revision. This register returns current silicon revision number of the Yes No Current
NET2888. Revision

5.22 (Address 19h; USBSTAT) USB Status Register

Default
Bits Description Read Write Value
7 Suspend Control. If set, this bit indicates that there is a pending suspend request Yes Yes/Clr 0
from the USB host. Writing a 1 clears this bit and causes the NET2888 to enter
suspended mode.
6 USB Endpoint 4 STALL. The last USB IN token could not be serviced because Yes Yes/Clr 0
the endpoint was stalled (DCTL register bit 4 set), and was acknowledged with a
STALL. Writing a 1 clears this bit.
5 USB Endpoint 4 NAK. The last USB packet transmitted (IN packet) encountered Yes Yes/Clr 0
a FIFO underrun condition, and was acknowledged with a NAK. Writing a 1 clears
this bit.
4 USB Endpoint 4 ACK. The last USB packet transmitted (IN packet) was Yes Yes/Clr 0
successfully acknowledged with an ACK from the USB host. Writing a 1 clears this
bit.
3 USB Endpoint 3 STALL. The last USB packet received (OUT packet) could not Yes Yes/Clr 0
be accepted because the endpoint was stalled (DCTL register bit 3 set), and was
acknowledged with a STALL. Writing a 1 clears this bit.
2 USB Endpoint 3 NAK. The last USB packet received (OUT packet) could not be Yes Yes/Clr 0
accepted, and was acknowledged with a NAK.. Writing a 1 clears this bit.
1 USB Endpoint 3 ACK. The last USB packet received (OUT packet) was Yes Yes/Clr 0
successfully acknowledged with an ACK. Writing a 1 clears this bit.
0 Endpoint 2 Valid. When this bit is set, the 8-byte endpoint 2 mailbox registers Yes Yes 0
have been written by the local CPU, but not yet read by the USB host. The local
CPU should not write into these registers while this bit is set.

5.23 (Address 1Ah; FRAMEMSB) Frame Counter MSB Register

Default
Bits Description Read Write Value
7:3 Reserved. Yes No 0
2:0 Frame Counter MSB. This register contains the most-significant bits of the frame Yes No 0
counter from the most recent start-of-frame packet.

5.24 (Address 1Bh; FRAMELSB) Frame Counter LSB Register

Default
Bits Description Read Write Value
7:0 Frame Counter LSB. This register contains the least-significant bits of the frame Yes No 0
counter from the most recent start-of-frame packet.

____________________________________________________________________________________ 26
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Specification NET2888 USB Interface controller

5.25 (Address 1Ch; EXTIDX) Extended Register Index

Default
Bits Description Read Write Value
7:0 Extended Register Index. This register selects which extended data register is Yes Yes 0
accessed when the EXTDATA port is read or written.

5.26 (Address 1Dh; EXTDATA) Extended Register Data

Default
Bits Description Read Write Value
7:0 Extended Data. This port provides access to one of the extended data registers. The See See See
index of the current register is held in the EXTIDX register. Below Below Below

5.26.1 (Address 1Dh, Index 00h; VIDMSB) Vendor ID MSB

Default
Bits Description Read Write Value
7:0 Vendor ID MSB. This register determines the most significant byte of the Vendor Yes Yes 0x05
ID during a ‘Get Device Descriptor’ request.

5.26.2 (Address 1Dh, Index 01h; VIDLSB) Vendor ID LSB

Default
Bits Description Read Write Value
7:0 Vendor ID LSB. This register determines the least significant byte of the Vendor Yes Yes 0x25
ID during a ‘Get Device Descriptor’ request.

5.26.3 (Address 1Dh, Index 02h; PIDMSB) Product ID MSB

Default
Bits Description Read Write Value
7:0 Product ID MSB. This register determines the most significant byte of the Product Yes Yes 0x28
ID during a ‘Get Device Descriptor’ request.

5.26.4 (Address 1Dh, Index 03h; PIDLSB) Product ID LSB

Default
Bits Description Read Write Value
7:0 Product ID LSB. This register determines the least significant byte of the Product Yes Yes 0x88
ID during a ‘Get Device Descriptor’ request.

5.26.5 (Address 1Dh, Index 04h; RELMSB) Release Number MSB

Default
Bits Description Read Write Value
7:0 Release Number MSB. This register determines the most significant byte of the Yes Yes REL
device release number during a ‘Get Device Descriptor’ request. NUM
MSB

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Specification NET2888 USB Interface controller

5.26.6 (Address 1Dh, Index 05h; RELLSB) Release Number LSB

Default
Bits Description Read Write Value
7:0 Release Number LSB. This register determines the least significant byte of the Yes Yes REL
device release number during a ‘Get Device Descriptor’ request. NUM
LSB

5.26.7 (Address 1Dh, Index 06h; RCVAFTH) Receive FIFO Almost Full
Threshold
Default
Bits Description Read Write Value
7:6 Reserved. Yes No 0x00
5:0 Receive FIFO Almost Full Threshold. This register determines the threshold at Yes Yes 0x3C
which the receive FIFO almost full status bit is set.

5.26.8 (Address 1Dh, Index 07h; XMTAETH) Transmit FIFO Almost Empty
Threshold
Default
Bits Description Read Write Value
7:6 Reserved. Yes No 0x00
5:0 Transmit FIFO Almost Empty Threshold. This register determines the threshold Yes Yes 0x04
at which the transmit FIFO almost empty status bit is set.

5.26.9 (Address 1Dh, Index 08h; USBCTL) USB Control

Default
Bits Description Read Write Value
7:1 Reserved. Yes No 0x00
0 USB String Enable. When set, this bit allows the default Vendor and Product ID Yes Yes 0x1
String Descriptors to be returned to the host. When this bit is cleared, the string
index values in the Device Descriptor are set to zero, and string descriptor reads are
acknowledged with a stall.

5.26.10 (Address 1Dh, Index 09h; MAXPWR) Maximum Power Consumption

Default
Bits Description Read Write Value
7:0 Maximum Current. The amount of current drawn by the peripheral from the USB Yes Yes 0xFA
port in increments of 2 mA. The NET2888 reports this value to the host controller
in the configuration descriptor. The default is 500 mA (0xFA * 2 mA).

____________________________________________________________________________________ 28
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Specification NET2888 USB Interface controller

5.26.11 (Address 1Dh, Index 0Ah; PKTCTL) Packet Control

Default
Bits Description Read Write Value
7 EP4 Data Toggle Bit. Contains the value of the Data Toggle bit to be sent in Yes Yes 0x0 / 0x1
response to the next IN token to endpoint 4 from the USB host. (Toggle)
6 EP3 Data Toggle Bit. Contains the value of the Data Toggle bit expected in the Yes Yes 0x0 / 0x1
next DATA packet to endpoint 3 from the USB host. (Toggle)
5 EP2 Data Toggle Bit. Contains the value of the Data Toggle bit to be sent in Yes Yes 0x0 / 0x1
response to the next IN token to endpoint 2 from the USB host. (Toggle)
4 EP1 Data Toggle Bit. Contains the value of the Data Toggle bit expected in the Yes Yes 0x0 / 0x1
next DATA packet to endpoint 1 from the USB host. (Toggle)
3 EP4 Data Toggle Mode. When set, this bit resets the Data Toggle bit to zero at the Yes Yes 0x0
end of a USB transfer from EP4. When cleared, the Data Toggle bit strictly toggles.
2 EP3 Data Toggle Mode. When set, this bit resets the Data Toggle bit to zero at the Yes Yes 0x0
end of a USB transfer to EP3. When cleared, the Data Toggle bit strictly toggles.
1 Reserved. Yes No 0x0
0 EP1 Data Toggle Mode. When set, this bit resets the Data Toggle bit to zero at the Yes Yes 0x0
end of a USB transfer to EP1. When cleared, the Data Toggle bit strictly toggles.

5.26.12 (Address 1Dh, Index 0Bh; LOCALCTL) Local-Side Control

Default
Bits Description Read Write Value
7:1 Reserved. Yes No 0x00
0 Local Clock Output. This bit controls the output of the LCLK pin. Yes Yes 0x0
0 = 48 MHz clock derived from CLKIN signal
1 = 12 MHz clock derived from USB bitstream (for testing purposes)

5.26.13 (Address 1Dh, Index 0Ch; FIFOCTL) FIFO Control

Default
Bits Description Read Write Value
7:1 Reserved. Yes No 0x00
0 Transmit FIFO Valid Mode. When set, this bit causes a NAK response to a host Yes Yes 0x0
read request from the transmit FIFO (EP4) unless the FIFO Valid bit (in register
EP4STAT) is set. When this bit is cleared, any data waiting in the transmit FIFO
will be sent in response to a host read request, and the FIFO Valid bit is ignored.

____________________________________________________________________________________ 29
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Specification NET2888 USB Interface controller

6. Standard Device Requests

6.1 Control ‘IN’Transactions

6.1.1 Get Device Status

Offset Number of Description Default Value
Bytes
0 2 bits 15:2 = Reserved 0x0001
bit 1 = Device Remote Wakeup enabled
bit 0 = Device is operating in Self-Powered mode.
(depends on PWRGOOD# input pin)

6.1.2 Get Interface Status

Offset Number of Description Default Value
Bytes
0 2 bits 15:0 = Reserved 0x0000

6.1.3 Get Endpoint 0,1,2,3,4 Status

Offset Number of Description Default Value
Bytes
0 2 bits 15:1 = Reserved 0x0000
bit 0 = Endpoint is stalled

6.1.4 Get Device Descriptor (18 Bytes)

Offset Number of Description Default Value
Bytes
0 1 Length 0x12
1 1 Type (device) 0x01
2 2 USB Specification Release Number 0x0100
4 1 Class Code 0xFF
5 1 Sub Class Code 0x00
6 1 Protocol 0x00
7 1 Maximum Endpoint 0 Packet Size 0x08
8 2 Vendor ID Determined by Local
Register VIDMSB, VIDLSB
10 2 Product ID Determined by Local
Register PIDMSB, PIDLSB
12 2 Device Release Number Determined by Local
Register RELMSB, RELLSB
14 1 Index of string descriptor describing manufacturer 0x01 (if USBCTL bit 0 is
‘1’)
0x00 (if USBCTL bit 0 is
‘0’)
15 1 Index of string descriptor describing product 0x02 (if USBCTL bit 0 is
‘1’)
0x00 (if USBCTL bit 0 is
‘0’)
16 1 Index of string descriptor describing serial number 0x00
17 1 Number of configurations 0x01

____________________________________________________________________________________ 30
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Specification NET2888 USB Interface controller

6.1.5 Get Configuration Descriptor (46 bytes)

Note that all interface and endpoint descriptors are returned when this request is issued

Offset Number of Description Default Value

Bytes
Configuration Descriptor
0 1 Length 0x09
1 1 Type (configuration) 0x02
2 2 Total length returned for this configuration 0x002E
4 1 Number of Interfaces 0x01
5 1 Number of this configuration 0x01
6 1 Index of string descriptor describing this configuration 0x00
7 1 Attributes 0x60 (if self powered)
bit 7 = Bus Powered (depends on BUSPWR# input pin) 0xA0 (if bus powered)
bit 6 = Self-Powered (depends on BUSPWR# input pin)
bit 5 = Remote-Wakeup
bits 4:0 = Reserved
8 1 Maximum USB power required (in 2 mA units) Determined by Local
(depends on BUSPWR# input pin) Register MAXPWR
Interface 0 Descriptor
0 1 Size of this descriptor in bytes 0x09
1 1 Type (interface) 0x04
2 1 Number of this interface 0x00
3 1 Alternate Interface 0x00
4 1 Number of endpoints used by this interface (excluding 0x04
endpoint 0)
5 1 Class Code 0x00
6 1 Sub Class Code 0x00
7 1 Device Protocol 0x00
8 1 Index of string descriptor describing this interface 0x00
Endpoint 1 Descriptor
0 1 Size of this descriptor 0x07
1 1 Descriptor Type (endpoint) 0x05
2 1 Endpoint Address 0x01
bit 7 = direction (1 = IN, 0 = OUT)
bits 6:4 = reserved
bits 3:0 = endpoint number
3 1 Endpoint Attributes 0x02
bits 7:2 = reserved
bits 1:0
00 = Control
01 = Isochronous
10 = Bulk
11 = Interrupt
4 2 Maximum packet size of this endpoint 0x0008
6 1 Interval for polling endpoint (not used) 0x00

____________________________________________________________________________________ 31
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Specification NET2888 USB Interface controller

Get Configuration Descriptor (continued)

Offset Number of Description Default Value
Bytes
Endpoint 2 Descriptor
0 1 Size of this descriptor 0x07
1 1 Descriptor Type (endpoint) 0x05
2 1 Endpoint Address 0x82
bit 7 = direction (1 = IN, 0 = OUT)
bits 6:4 = reserved
bits 3:0 = endpoint number
3 1 Endpoint Attributes 0x03
bits 7:2 = reserved
bits 1:0
00 = Control
01 = Isochronous
10 = Bulk
11 = Interrupt
4 2 Maximum packet size of this endpoint 0x0008
6 1 Interval for polling endpoint Determined by Local
Register EP2POLL
Endpoint 3 Descriptor
0 1 Size of this descriptor 0x07
1 1 Descriptor Type (endpoint) 0x05
2 1 Endpoint Address 0x03
bit 7 = direction (1 = IN, 0 = OUT)
bits 6:4 = reserved
bits 3:0 = endpoint number
3 1 Endpoint Attributes 0x02 for bulk
bits 7:2 = reserved 0x01 for isochronous
bits 1:0
00 = Control
01 = Isochronous
10 = Bulk
11 = Interrupt
4 2 Maximum packet size of this endpoint for bulk mode Determined by Local
Bus Time for isochronous mode Register EP3PKSZ
6 1 Interval for polling endpoint 0x00 for bulk
0x01 for isochronous
Endpoint 4 Descriptor
0 1 Size of this descriptor 0x07
1 1 Descriptor Type (endpoint) 0x05
2 1 Endpoint Address 0x84
bit 7 = direction (1 = IN, 0 = OUT)
bits 6:4 = reserved
bits 3:0 = endpoint number
3 1 Endpoint Attributes 0x02 for bulk
bits 7:2 = reserved 0x01 for isochronous
bits 1:0
00 = Control
01 = Isochronous
10 = Bulk
11 = Interrupt
4 2 Maximum packet size of this endpoint for bulk mode Determined by Local
Bus Time for isochronous mode Register EP4PKSZ
6 1 Interval for polling endpoint 0x00 for bulk
0x01 for isochronous

____________________________________________________________________________________ 32
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Specification NET2888 USB Interface controller

6.1.6 Get String Descriptor 0

Offset Number of Description Default Value
Bytes
0 4 Language ID (English = 09, U.S. = 04) 0x04, 0x03,
0x0409

6.1.7 Get String Descriptor 1

Offset Number of Description Default Value
Bytes
0 38 Manufacturer Descriptor 0x26, 0x03,
“Netchip
Technology”

6.1.8 Get String Descriptor 2

Offset Number of Description Default Value
Bytes
0 66 Product Descriptor 0x42, 0x03,
“NET2888 USB
Interface
Controller”

6.1.9 Get Configuration

Offset Number of Description Default Value
Bytes
0 1 Returns current device configuration 0x00

6.1.10 Get Interface

Offset Number of Description Default Value
Bytes
0 1 Returns current alternate setting for the specified 0x00
interface

____________________________________________________________________________________ 33
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Specification NET2888 USB Interface controller

6.2 Control ‘OUT’Transactions

6.2.1 Set Address

Offset Number of Description Default Value
Bytes
-- 0 Sets USB address of device --
Value = device address, Index = 0

6.2.2 Set Configuration

Offset Number of Description Default Value
Bytes
-- 0 Sets the device configuration --
Value = Configuration value (0 or 1 supported),

6.2.3 Set Interface

Offset Number of Description Default Value
Bytes
-- 0 Selects alternate setting for specified interface --
Value = Alternate setting, Index = specified interface

6.2.4 Device Clear Feature

Offset Number of Description Default Value
Bytes
-- 0 Clear the selected device feature --
Value = feature selector
FS = 1 --> Device Remote Wakeup (disable)

6.2.5 Device Set Feature

Offset Number of Description Default Value
Bytes
-- 0 Set the selected device feature --
Value = feature selector
FS = 1 --> Device Remote Wakeup (enable)

6.2.6 Endpoint 0,1,2,3,4 Clear Feature

Offset Number of Description Default Value
Bytes
-- 0 Clear the selected endpoint feature --
Value = feature selector, Index = endpoint number
FS = 0 --> Endpoint stall (clears stall bit)

6.2.7 Endpoint 0,1,2,3,4 Set Feature

Offset Number of Description Default Value
Bytes
-- 0 Set the selected endpoint feature --
Value = feature selector, Index = endpoint number
FS = 0 --> Endpoint stall (sets stall bit)

____________________________________________________________________________________ 34
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Specification NET2888 USB Interface controller

6.3 Endpoint 1 ‘OUT’Transactions (Receive Mailboxes)

Offset Number of Description Default Value
Bytes
-- 8 Host writes 8 bytes to the receive mailboxes using bulk --
OUT transactions

6.4 Endpoint 2 ‘IN’Transactions (Transmit Mailboxes)

Offset Number of Description Default Value
Bytes
-- 8 Host reads 8 bytes from the transmit mailboxes using --
interrupt IN transactions

6.5 Endpoint 3 ‘OUT’Transactions (Receive FIFO)

Offset Number of Description Default Value
Bytes
-- up to 64 Host writes data into the receive FIFO using bulk or --
isochronous OUT transactions

6.6 Endpoint 4 ‘IN’Transactions (Transmit FIFO)

Offset Number of Description Default Value
Bytes
-- up to 64 Host reads data from the transmit FIFO using bulk or --
isochronous IN transactions

7. Vendor Device Requests

7.1 Device Clear Feature

Offset Number of Description Default Value
Bytes
-- 0 Clear the selected device feature --
Value = feature selector
FS = 0x80 --> Timing test mode (clears test bit)

7.2 Device Set Feature

Offset Number of Description Default Value
Bytes
-- 0 Set the selected device feature --
Value = feature selector
FS = 0x80 --> Timing test mode (sets test bit)

____________________________________________________________________________________ 35
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Specification NET2888 USB Interface controller

8. Electrical Specifications

8.1 Absolute Maximum Ratings

Conditions that exceed the Absolute Maximum limits may destroy the device.

Symbol Parameter Conditions Min Max Unit

VDDC Core/USB Supply Voltage With Respect to Ground -0.5 4.6 V
VDDLCL Local Supply Voltage (+5V) With Respect to Ground -0.5 7.0 V
VI DC input voltage With Respect to Ground -0.5 VDD+0.5 V
IOUT DC Output Current, per pin -25 25 mA
TSTG Storage Temperature No bias -65 150 °C
TAMB Ambient temperature Under bias °C
TJ Junction temperature Under bias °C
PD Power Dissipation Under bias mW
VESD ESD Rating R = 1.5K, C = 100pF 2 KV

8.2 Recommended Operating Conditions

Conditions that exceed the Operating limits may cause the device to function incorrectly.

Symbol Parameter Conditions Min Max Unit

VDDC Core/USB Supply Voltage 3.0 3.6 V
VDDLCL Local Bus Supply Voltage 5.0V operation 4.75 5.25 V
VDDLCL Local Bus Supply Voltage 3.3V operation 3.0 3.6 V
VIH High Level Input Voltage 2 V
VIL Low Level Input Voltage 0.8 V
VI Input Voltage 0 VDDL V
VO Output Voltage 0 VDDL V
IOH High Level Output Current -8 mA
IOL Low Level Output Current 8 mA
TA Operating Temperature 0 70 °C
tR Input rise time 1 10 ns/V
tF Input fall time 1 10 ns/V

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Specification NET2888 USB Interface controller

8.3 DC Specifications

8.3.1 Core DC Specifications

Operating Conditions: VDDC: 3.3V ± 5%, TA = 0°C to 70°C
All typical values are at VDDC = 3.3V and TA = 25°C
Operating Conditions: Notes 1, 2, 9.

Symbol Parameter Conditions Min Typ Max Unit

IDDC VDDC Supply Current VDDC = 3.3V 30 50 mA

IDDCS VDDC Supply Current (Suspend) Device suspended 50 µA

8.3.2 USB Port DC Specifications

Operating Conditions: VDDC: 3.3V ± 5%, TA = 0°C to 70°C
All typical values are at VDDC = 3.3V and TA = 25°C
Operating Conditions: Notes 1,2.

Symbol Parameter Conditions Min Typ Max Unit

VDI Differential Input Sensitivity | (D+) - (D-) | 0.2 V

VCM Differential Common Mode Includes VDI range 0.8 2.5 V

Range

VSE Single Ended Receiver Threshold 0.8 2.0 V

VOH Static Output High RL of 15 KΩ to GND 2.8 3.6 V

VOL Static Output Low RL of 1.5 KΩ to 3.6V 0.3 V

ILO Hi-Z State Data Line Leakage 0V < VIN < 3.3V -10 +10 µA

CIO I/O Capacitance Pin to GND 20 pF

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Specification NET2888 USB Interface controller

8.3.3 Local Bus (+3.3V) DC Specifications

Operating Conditions: VDDL: 3.3V ± 5%, TA = 0°C to 70°C
All typical values are at VDDL = 3.3V and TA = 25°C
Operating Conditions: Note 9

Symbol Parameter Conditions Min Typ Max Unit

VOH Output High Voltage IOH = -8mA 2.0 V

VOL Output Low Voltage IOL = 8mA 0.4 V

IIH Input High Leakage VIH = 3.3V 10 µA

IIL Input Low Leakage VIL = 0V 10 µA

IOZ Hi-Z State Data Line Leakage 0V < VIN < 3.3V -10 +10 µA

IDDLS VDDL Supply Current (Suspend) Device suspended 10 µA

IDDL VDDL Supply Current VDDC = 3.3V 10 20 mA

CIO I/O Capacitance Pin to GND 5 pF

CIN Input Capacitance Pin to GND 10 pF

8.3.4 Local Bus (+5.0V) DC Specifications

Operating Conditions: VDDL: 5.0V ± 5%, TA = 0°C to 70°C
All typical values are at VDDL = 5.0V and TA = 25°C
Operating Conditions: Note 9

Symbol Parameter Conditions Min Typ Max Unit

VOH Output High Voltage IOH = -8mA 4.0 V

VOL Output Low Voltage IOL = 8mA 0.4 V

IIH Input High Leakage VIH = 5.0V 10 µA

IIL Input Low Leakage VIL = 0V 10 µA

IOZ Hi-Z State Data Line Leakage 0V < VIN < 5.0V -10 +10 µA

IDDLS VDDL Supply Current (Suspend) Device suspended 10 µA

IDDL VDDL Supply Current VDDC = 3.3V 15 25 mA

CIO I/O Capacitance Pin to GND 5 pF

CIN Input Capacitance Pin to GND 10 pF

____________________________________________________________________________________ 38
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Specification NET2888 USB Interface controller

8.4 AC Specifications

8.4.1 USB Port AC Specifications

Operating Conditions: VDD: 3.3V ± 5%, TA = 0°C to 70°C
All typical values are at VDD = 3.3V and TA = 25°C
Operating Conditions: Notes 1,2,3.

Symbol Parameter Conditions Waveform Min Typ Max Unit

TR Rise & Fall Times CL = 50 pF Figure 8-1 4 20 ns

TF Notes 4,5 4 20

TRFM Rise/Fall time matching (TR/ TF) Figure 8-1 90 110 %

VCRS Output Signal Crossover Voltage 1.3 2.0 V

ZDRV Driver Output Resistance Steady State Drive 28 43 Ω

TDRATE Data Rate 11.97 12 12.03 Mbs

TDDJ1 Source Differential Driver Jitter Notes 6,7. Figure 8-2 -3.5 0 3.5 ns
to Next Transition

TDDJ2 Source Differential Driver Jitter Notes 6,7 Figure 8-2 -4.0 0 4.0 ns
for Paired Transitions

TDEOP Differential to EOP Transition Note 7 Figure 8-3 -2 0 5 ns

Skew

TEOPT Source EOP Width Note 7 Figure 8-3 160 167 175 ns

TJR1 Receiver Data Jitter Tolerance to Note 7 Figure 8-4 -18.5 0 18.5 ns
Next Transition

TJR2 Receiver Data Jitter Tolerance for Note 7 Figure 8-4 -9 0 9 ns

Paired Transitions

TEOPR1 EOP Width at Receiver; Must Note 7 Figure 8-3 40 ns

reject as EOP

TEOPR2 EOP Width at Receiver; Must Note 7 Figure 8-3 80 ns

accept as EOP

____________________________________________________________________________________ 39
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Specification NET2888 USB Interface controller

8.4.2 USB Port AC/DC Specification Notes

1. All voltages measured from the local ground potential, unless otherwise specified.
2. All timings use a capacitive load (CL) to ground of 50 pF, unless otherwise specified.
3. Full Speed timings have a 1.5 kΩ pull-up to 3.3 V on the D+ data line.
4. Measured from 10% to 90% of the data signal.
5. The rising and falling edges should be smoothly transitioning (monotonic).
6. Timing difference between the differential data signals.
7. Measured at crossover point of differential data signals.
8. The maximum load specification is the maximum effective capacitive load allowed that meets the
target hub VBUS droop of 330 mV.
9. VDDC and IDDC refer to core power supply (pins designated VDD). VDDL and IDDL refer to local bus
power supply (pins designated VDD, LOCAL).

8.4.3 USB Port AC Waveforms

Rise Time Fall Time

CL 90% 90%

Differential
Data Lines

10% 10%
CL
tR tF

Full Speed: 4 to 20ns at C L = 50pF

Figure 8-1. Data Signal Rise and Fall Time

____________________________________________________________________________________ 40
 NetChip Technology, Inc., 1998
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
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Specification NET2888 USB Interface controller

TPERIOD
Crossover
Points
Differential
Data Lines

Consecutive
Transitions
N*TPERIOD+TxJR1
Paired
Transitions
N*TPERIOD+TxJR2

Figure 8-2. Differential Data Jitter

TPERIOD Crossover
Point Extended
Crossover
Point
Differential
Data Lines

Diff. Data to
SE0 Skew Source EOP Width: T EOPT
N*TPERIOD+TDEOP

Receiver EOP Width: T EOPR1, TEOPR2

Figure 8-3. Differential to EOP Transition Skew and EOP Width

TPERIOD

Differential
Data Lines

TJR TJR1 TJR2

Consecutive
Transitions
N*TPERIOD+TJR1
Paired
Transitions
N*TPERIOD+TJR2

Figure 8-4. Receiver Jitter Tolerance

____________________________________________________________________________________ 41
 NetChip Technology, Inc., 1998
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
[Link]
Specification NET2888 USB Interface controller

8.4.4 Local Bus Write to Register

NAME DESCRIPTION MIN MAX UNIT

T1 Address setup to write enable* 10 ns
T2 Address hold from end of write enable* 3.5 ns
T3 Write enable width* 24 ns
T4 Chip select hold from end of IOW# 1 ns
T5 Data setup to end of write enable* 5 ns
T6 Data hold time from end of IOW# 5.5 ns
T7 I/O Recovery Time 60 ns

• Write enable is the occurrence of both IOW# and CS#.

A[4:0]

T1 T2

CS#

T3 T4

T7
IOW#

T5 T6

D[7:0]

____________________________________________________________________________________ 42
 NetChip Technology, Inc., 1998
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
[Link]
Specification NET2888 USB Interface controller

8.4.5 Local Bus Read from Register

NAME DESCRIPTION MIN MAX UNIT

T1 Address setup to read enable* 10 ns
T2 Address hold from end of read enable* 1 ns
T3 Chip select hold from end of IOR# 1 ns
T4 Data access time from read enable* 13 ns
T5 Data tri-state time from end of IOR# 10 ns
T6 I/O Recovery Time 60 ns

• Read enable is the occurrence of both IOR# and CS#

A[4:0]

T1 T2

CS#

T6
IOR#

T4 T5

D[7:0]

____________________________________________________________________________________ 43
 NetChip Technology, Inc., 1998
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
[Link]
Specification NET2888 USB Interface controller

8.4.6 DMA Write to FIFO

NAME DESCRIPTION MIN MAX UNIT

T1 DRQ false from DACK# true 60 ns
T2 DACK# false to DRQ true 30 ns
T3 Write enable width* 25 ns
T4 DACK# hold from end of IOW# 0 ns
T5 Data setup to end of write enable* 5 ns
T6 Data hold time from end of IOW# 5 ns
T7 Width of EOT# pulse (see note) 25 ns
T8 DACK# recovery time 30 ns
T9 DMA recovery time 60 ns

* Write enable is the occurrence of both IOW# and DACK#.

Note: EOT#, IOW#, and DACK# must be concurrently true for at least T7 for proper recognition for the EOT# pulse.

DRQ

T1 T2

T8
DACK#

T3 T4

T9
IOW#

T5 T6

D[7:0]

EOT#

____________________________________________________________________________________ 44
 NetChip Technology, Inc., 1998
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
[Link]
Specification NET2888 USB Interface controller

8.4.7 DMA Read from FIFO

NAME DESCRIPTION MIN MAX UNIT

T1 DRQ false from DACK# true 60 ns
T2 DACK# false to DRQ true 30 ns
T3 DACK# hold time from end of IOR# 0 ns
T4 Data access time from read enable* 10 ns
T5 Data hold time from end of IOR# 10 ns
T6 Width of EOT# pulse (see note) 25 ns
T7 DACK# recovery time 30 ns
T8 DMA recovery time 60 ns
* Read enable is the occurrence of both IOR# and DACK#.
Note: EOT#, IOR#, and DACK# must be concurrently true for at least T6 for proper recognition of the EOT# pulse.

DRQ

T1 T2

T7
DACK#

T8
IOR#

T4 T5

D[7:0]

EOT#

____________________________________________________________________________________ 45
 NetChip Technology, Inc., 1998
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
[Link]
Specification NET2888 USB Interface controller

9. Mechanical Drawing

9±0.4

7±0.1
36

25
37 24

9±0.4
7±0.1
INDEX

48 13
12
1

0.5 +0.1
0.18 -0.05
1.7 max

1.4±0.1

0.125±0.05
0o
10o
0.1

0.5±0.2

All dimensions in millimeters.

____________________________________________________________________________________ 46
 NetChip Technology, Inc., 1998
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490 FAX (650) 526-1494
[Link]

Common questions