Unit – I

Unit I: Architecture of 8086 Microprocessor

Question 1: Draw the micro-architecture of 8086. Explain the functions of

Execution Unit (EU) and Bus Interface Unit (BIU). (S-12/10M)
Question 2: Draw and explain micro-architecture of 8086. How 8086 supports
parallel processing? (W-12/10M)
Question 3: Draw and explain internal architecture of 8086 microprocessor.
(S-13/10M)

1. Architecture of 8086 Microprocessor

It is also called as internal architecture of 8086 microprocessor, i.e. circuit building blocks that
implement the software and hardware architectures. Figure 1 shows the internal architecture of 8086
microprocessors.
Bus
Execution Instruction Pipeline Interface
Unit Unit

System Bus

Figure 1: Internal Architecture of 8086

The 8086 microprocessors works on parallel processing, i.e., it is implemented with a number of
simultaneously operating processing units. As shown in Figure 1, it consists of following two processing
units:
1. Bus Interface Unit (BIU) and
2. Execution Unit (EU)
Each unit has dedicated functions and operate at the same time, this parallel processing effectively
fetch and execute instructions independent of operations. This results in efficient use of the system bus and
higher performance for 8086 microcomputer systems.

a) Bus Interface Unit (BIU)

It is the interface unit of 8086 and connected to the outside world. Interface means, the path by
which it connects to external devices. It is responsible for performing all external bus operations, such as
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instruction fetching, reading and writing of data operands for memory, and inputting or outputting data for
input/output peripherals.
The information transfers take place over the system bus which includes a 16-bit bidirectional data
bus, 20-bit address bus, and the signals needed to control transfers over the bus.
Other functions related to instruction and data acquisition are also performed by the bus interface
unit. For example, it is responsible for instruction queuing and address generation. As shown in the Figure 2,
it contains:
1. Segment registers
2. Instruction pointer
3. Address generation adder
4. Bus control logic, and
5. Instruction queue

Execution Unit Bus Interface Unit

General Segment
Registers Registers

Instruction
Pointer

Address
Generation
And Bus
Control

Operands

Instruction
Queue
ALU

Flags

Figure 2: Execution and Bus Interface Unit

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It uses an instruction queue to implement a pipelined architecture which permits to prefetch up to 6

bytes for the 8086 of instruction code and whenever the queue is not full, it has room for at least 2 more
bytes, and, at the same time, the execution unit is not asking it to read or write data from memory.
Perfected instructions are held in the first-in first-out (FIFO) queue.
Whenever a byte is loaded at the input end of the queue, it is automatically shifted up through the
FIFO to the empty location nearest to the output and code is held until the execution unit is ready to accept
it. If the queue is full and the EU is not requesting access to data in memory, the BIU does not need to
perform any bus operations. The intervals of no bus activity, which occur between bus operations, are
known as idle states.

b) Execution Unit (EU)

It consists of the arithmetic logic unit (ALU), status and control flags, general-purpose registers, and
temporary-operand registers and it is responsible for decoding and executing instructions.
It accesses instructions from the output end of the instruction queue and data from the general-
purpose registers or memory. It reads instruction, decodes them, generates data addresses if necessary,
passes them to the BIU and requests it to perform the read or write operations to memory or I/O, and
performs the operation specified by the instruction.
The ALU performs the arithmetic, logic, and shift operations required by an instruction. During
execution of the instruction, the EU may test the status and control flags, and updates these flags based on
the results of executing the instruction. If the queue is empty, the execution unit waits for the next
instruction byte to be fetched and shifted to the top of the queue.

Question 4: Draw and explain software model of 8086. (W-12/7M)

2. Software Model of the 8086 Microprocessor

The software model helps the programmer in understanding the operation of the microcomputer
system from a software point of view. To program a microprocessor, it is not necessary to know all of its
hardware architectural details.
For example, we do not need to know the function of the signals at its various pins, their electrical
connections, or their electrical switching characteristics. It is important for the programmer to know the
various registers within the device and to understand their purpose, functions, operating capabilities, and
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limitations. It is essential that the programmer know how external memory and input/output peripherals
are organized, how information is arranged in registers, memory and input/output, and how memory and
I/O are addressed to obtain instructions and data. This information represents the software architecture of
the processor.
Figure 3 shows the software model of the 8086 microprocessor. It consists of microprocessor unit,
I/O address space unit and 14 16-bit internal registers as:
o 1 Instruction Pointer (IP),
o 4 Data Registers (AX, BX, CX, and DX),
o 2 Pointer Registers (BP and SP),
o 2 Index Registers (SI and DI),
o 4 Segment Registers (CS, DS, SS, and ES) and
o 1 Status Register (SR)
External Memory 0000016
Address Space
8086 MPU Code Segment
15 0
(64 Kbytes)
IP
000016
CS Data Segment
DS
(64 Kbytes)
SS
ES Input/Output
15 7 0 Address Space
AH AL AX
BH BL BX Stack Segment (64 Kbytes)
CH CL CX
(64 Kbytes)
DH DL DX

SP FFFF16
BP
SI Extra Segment
DI
(64 Kbytes)
9 0
SR
FFFFF16
Figure 3: Software Model of 8086 Microprocessor

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Question 5: Explain in detail memory address space in 8086/88 based system.

What are the fundamental data formats supported by 8086? How these data
formats can be organized in memory? (S-12/7M)
Question 6: Explain Physical Memory Organisation of 8086. (W-13/7M)

3. Memory Address Space and Data Organization

The 8086 microprocessors support 1 Mbyte of external memory with data stored at consecutive
addresses over the range (00000)16 to (FFFFF)16 as shown in Figure 4. Memory is organized as 8-bit bytes,
not as 16-bit words.
FFFFF
FFFFE
FFFFD
FFFFC

4
3
2
1
0
Figure 4: Memory Address space for 8086 microprocessor
The 8086 can access any two consecutive bytes as a word of data. In this case, the lower-addressed
byte is the least significant byte of the word, and the higher-addressed byte is its most significant byte of the
word.
Figure 5 shows how a word of data is stored in memory. The storage location at the lower address,
(00624)16, contains the value (10000110)2 = (86)16. The contents of the next-higher-addressed storage
location, (00625)16, are (01110100)2 = (74)16, these two bytes represent the word
(0111010010000110)2 = (7486)16.
Address Memory Memory
Most Significant Byte 0062516 0111 0100 7 4
Least Significant Byte 0062416 1000 0110 8 6

Figure 5: Storing word of data in Memory

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a) Even Address and Odd Address Boundary

Words of data can be stored at even or odd addressed word boundaries to make efficient use of
memory. The least significant bit of the address determines the type of word boundary.
If this bit is 0, the word is at an even-address boundary i.e. word at an even-address boundary
corresponds to two consecutive bytes, with the least significant byte located at an even address.
For example, the word shown in Figure 5 has its least significant byte at address (00624)16, Thus, it is
stored at an even-address boundary.
A word of data stored at an even-address boundary, such as 0000016, 0000216, 0000416, and so on, is
said to be an aligned word-that is, all aligned words are located at an address that is a multiple of 2.
A word of data stored at an odd-address boundary, such as 0000116, 0000316, or 0000516 and so on, is
called a misaligned word. Figure 6 shows some aligned and misaligned words of data. Examples of aligned-
data words are 0, 2, 4, and 6, while misaligned words are 1, 3 and 5.
Address Physical Memory Aligned Words Misaligned Word
00008H Byte 8
00007H Byte 7
Word 4
00006H Byte 6
Word 5
00005H Byte 5
00004H Byte 4 Word 3
Word 3
00003H Byte 3
Word 2
00002H Byte 2
Word 1
00001H Byte 1
Word 1
00000H Byte 0
Figure 6: Examples of Aligned and Misaligned Word
The double word corresponds to four consecutive bytes of data stored in memory; for example, a
pointer. A pointer is a two-word address element that is used to access data or code in memory. The word
of this pointer that is stored at the higher address is called the segment base address, and the word at the
lower address is called the offset address.
A double word can be aligned or misaligned. An aligned double word is located at an address that is
a multiple of 4 e.g., 0000016, 0000416, and 0000816. Figure 7 shows examples of some aligned and

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misaligned double words of data. Examples of aligned-data double words are 0 and 4, while misaligned
double words are 1 and 5.
Figure 8 shows the storage of a double word in memory. The higher addressed word represents the
segment base address, stored at even-address boundary 0000616, the most significant byte of this word is
at address 0000716 and equals 000110112 = 1B16. Its least significant byte is at address 0000616 and equals
001011002 = 2C16. Combining these two values, we get the segment base address, which equals
00111011010011002 = 1B2C16.
Address Physical Memory Aligned Double Words Misaligned Double Word
00008H Byte 8
00007H Byte 7
Word 5
00006H Byte 6
00005H Byte 5 Word 4
00004H Byte 4
00003H Byte 3
00002H Byte 2 Word 1
Word 0
00001H Byte 1
00000H Byte 0
Figure 7: Examples of Aligned and Misaligned Double Word
Address Memory Memory
(Binary) (Hexadecimal)
0000716 0001 1011 1 B
0000616 0010 1100 2 C
0000516 0000 0000 0 0
0000416 1000 0001 8 1

Figure 8: Storing 32-bit pointer in memory

The offset part of the double word is the lower-addressed word. Its least significant byte is stored at
address 0000416 which contains 100000012 = 8116, the most significant byte is at address 00005l6, which
contains 000000002 = 0016, the resulting offset is 00000000100000012 = 008116. The complete double word
is 1B2C008116. This double word starts at address 0000416 is an example of an aligned double word of data.

4. Data Types
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Unit – I

The 8086 microprocessor directly processes data expressed in a number of different data types.
There are three basic data types in 8086 microprocessor, they are:
1. Byte (8 bits),
2. Word (16 bits), and
3. Double word (32 bits).

a) Integer Data Type (Signed and Unsigned Integer)

The 8086 can process integer data as either unsigned or signed integer numbers; each type of integer
can be either byte-wide or word-wide. Figure 9(a) shows an unsigned byte integer; this data type can be used
to represent decimal numbers in the range 0 through 255. The unsigned word integer is shown in Figure
9(b) and can be used to represent decimal numbers in the range 0 through 65,535.
MSB LSB
D7 D0
Figure 9(a): Unsigned byte integer
MSB LSB
D15 D0
Figure 9(b): Unsigned word integer
The signed byte integer and signed word integer are shown in Figure 10 (a) and (b) are similar to the
unsigned integer data types, here the most significant bit is a sign bit. A 0 (zero) in this bit position identifies
a positive number.
MSB LSB
D7 D0
Figure 10(a): Signed byte integer
Sign Bit
MSB LSB
D15 D0

Sign Bit
Figure 10(b): Signed word integer
The signed integer byte can represent decimal numbers in the range +127 to –128, and the signed
integer word permits numbers in the range +32,767 to –32,768. For example, the number +3 expressed as a

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signed integer byte is 000000112 = (03)16. The 8086 always expresses negative numbers in 2's-complement
notation. So, 3 is coded as 111111012 = (FD)16.

b) Binary Coded Decimal (BCD) Data Type

Figure 11(a) shows the BCD values for decimal numbers from 0 to 9. BCD data can be stored in either
unpacked or packed form. The unpacked BCD byte in Figure 11(b), shows that a single BCD digit is stored in
the four least significant bits, and the upper four bits are set to 0.
Figure11(c) shows a byte with packed BCD digits. Here two BCD numbers are stored in a byte. The
upper four bits represent the most significant digit of a two-digit BCD number.

Decimal BCD
0 0000 MSB LSB
1 0001 D3 D2 D1 D0
2 0010
3 0011 Figure 11(b) BCD Digit
4 0100
5 0101 MSB LSB
6 0110 D7 D6 D5 D4 D3 D2 D1 D0
7 0111
8 1000 BCD Digit 1 BCD Digit 0
9 1001 Figure 11(c)
Figure 11(a)
Example:
 5 decimal Number is equivalent to 0101 BCD (Unpacked BCD)
 78 decimal Number is equivalent to 0111 1000 BCD (Packed BCD)

c) ASCII Data Type

Figure 12 shows how numbers, letters, and control characters are coded in ASCII.
b7 0 0 0 0 1 1 1 1
b6 0 0 1 1 0 0 1 1
b5 0 1 0 1 0 1 0 1
H1
b4b3b2b1 0 1 2 3 4 5 6 7
H0
0 0 0 0 0 NUL DLE SP 0 @ P P
0 0 0 1 1 SOH DC1 ! 1 A Q a Q

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0 0 1 0 2 STX DC2 “ 2 B R b R
0 0 1 1 3 ETX DC3 # 3 C S c S
0 1 0 0 4 EOT DC4 $ 4 D T d T
0 1 0 1 5 ENQ NAK % 5 E U e U
0 1 1 0 6 ACK SYN & 6 F V f V
0 1 1 1 7 BEL ETB ‘ 7 G W g W
1 0 0 0 8 BS CAN ( 8 H X h X
1 0 0 1 9 HT EM ) 9 I Y i Y
1 0 1 0 A LF SUB * : J Z j Z
1 0 1 1 B V ESC + ; K [ k }
1 1 0 0 C FF FS , < L \ l |
1 1 0 1 D CR GS - = M ] m {
1 1 1 0 E S0 RS . > N ^ n ~
1 1 1 1 F S1 US / ? O - o DEL
Figure 12(a): ASCII representation of numbers, letters, and control characters
Example: Number 5 is coded as
H1H0 = 011 01012
where H denotes that the ASCII-coded number is in hexadecimal form. As shown in Figure 12(b), ASCII data
are stored as one character per byte.
MSB LSB
D7 D0

ASCII Digit
Figure 12(b)

Question 6: Explain how memory is segmented and accessed in 8086 giving

suitable example. (S-13/7M)
Question 7: Explain the concept of Memory Segmentation used in 8086.
(W-13/7M)
Question 8: What are segment registers? Why memory is segmented? How
memory segmentation is done? (W-12/7M)

5. Segment Registers and Memory Segment

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The 8086 has a 1 Mbytes address space and not all this memory is active at one time. The 1 Mbytes
of memory is divided into 64 Kbytes segments. A segment represents an independently addressable unit of
memory consisting of 64 Kbytes consecutive byte-wide storage locations. Figure 13 shows the four
segments of memory that are active.
Each segment is assigned a base address that identifies its starting point. Only four of these 64
Kbytes segments are active at a time these are:
1. Code segment
2. Stack segment
3. Data segment and
4. Extra segment.
The segments are identified according to addresses stored in the 8086’s four internal segment
registers: CS(code segment), SS(stack segment), DS(data segment), ES(extra segment). Each of these
registers contains a 16-bit base address that points to the starting addressed of the segment in memory.
Four segments give a maximum of 256 Kbytes of active memory.
0000016

Code Segment
(64 Kbytes)
15 0
Code Segment(CS) Data Segment
Data Segment(DS)
(64 Kbytes)
Stack Segment(SS)
Extra Segment(ES)

Stack Segment
(64 Kbytes)

Extra Segment
(64 Kbytes)

FFFFF16

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Unit – I

Figure 13: Active Four Segment Register

Out of this 256 Kbytes of active memory, 64 Kbytes are for program storage, 64 Kbytes are for stack
and 128 Kbytes are for data storage. The values held in these registers are referred as the current segment
registers values; For example, the value in CS points to the first word wide storage location in the current
code segment. Code is always fetched from memory as words not as bytes.
The segment registers are said to be user accessible as programmer can change their contents
through software. For a program to gain access to another part of memory, simply change the value of the
appropriate register. For example, a new data space, with up to 128 Kbytes, is brought in simply by
changing the values in DS and ES.

6. Instruction Pointer
It is 16 bit register and finds the location of the next instruction to be fetched from the memory. It is 16
bits in length and is similar to a program counter; it contains the offset of the next instruction instead of its
actual address. This is because IP and CS are both 16-bits in length, but a 20-bit address is needed to access
memory. The offset address in IP is combined with the current value in code segment (CS) to generate the
address of the instruction code. The value of the address for the next code access is denoted as CS : IP.
15 0
Instruction Pointer (IP)
Figure 14: Instruction Pointer
The 8086 fetches instructions from the code segment of memory, stores them in its instruction
queue, and executes them one after the other. Every time a word of code is fetched from memory, the 8086
updates the value in IP i.e., IP is incremented by 2. The 8086 prefetches up to four bytes of instruction code
into its internal code queue and hold them for execution.
After an instruction is read from the output of the instruction queue, it is decoded; operands are read
from either the data segment of memory or internal registers.
Next, the operation specified in the instruction is performed on the operands and the result is
written back either in an internal register or a storage location in memory. The 8086 is now ready to execute
the next instruction in the code queue.

Question 9: Explain the register organisation of 8086. (S-13/W-13/7M/8M)

12 Assembly Language Programming

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7. Data Registers or General Purpose Registers

The 8086 has four general-purpose data registers (AX, BX, CX, and DX). Each of these registers can be
accessed either as a whole (16 bits) for word data operations or as two 8-bit registers for byte-wide
operations. An X after the register letter indicates a register as a word; For example, the 16-bit accumulator
is referenced as AX. Similarly, other three word registers are referred to as BX, CX, and DX.
An H or L after the register letter indicates a register as high byte and low byte. For the A register,
the most significant byte is referred to as AH and the least significant byte as AL; the other byte wide register
are BH and BL, CH and CL, and DH and DL. When software places a new value in one byte of a register, for
example AL, the value in the other byte (AH) does not change.
Data registers hold temporary values of frequently used intermediate results during program
execution. Software can read, load, or modify their contents. Any of the registers can be used as the source or
destination of an operand during an arithmetic operation such as ADD or a logic operation such as AND. For
example, the values of data, A and B, could be moved from memory into data registers and operations such
as addition, subtraction, and multiplication performed on them. The advantage of storing these data in
internal registers instead of memory during processing is that they can be accessed much faster.
15 8 7 0 15 0
AH AL Accumulator Register AX
BH BL Base AL
Register A
BX
CH CL CountBL
Register B
CX
DH DL Data CL
Register CL
DX
8-bit (H) 8-bit (L) DL DL
16-bit
Figure 15: General Purpose Register
 The accumulator register (AX) can be used for multiplication, division and I/O operations.
 The base register (BX) can be used for indirect addressing.
 The count register (CX) can be used as a counter in LOOP instructions and for string operations. CL
register holds the count for shift and rotate instructions.
 The data register (DX) can be used for multiplication, division and indirect I/O operations.

8. Pointer and Index Registers

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The 8086 has two pointer registers (Stack Pointer and Base Pointer) and two index registers (Source
Index and Destination Index) as shown in Figure 16. They store the offset addresses. An offset address
represents the displacement of a storage location in memory from the segment base address in a segment
register.
15 0
SP Stack Pointer
BP Base Pointer
SI Source Index
DI Destination Index
Figure 16: Pointer and Index Register
Software uses the value held in index register, to reference data in memory relative to the data
segment or extra segment register; a pointer register to access memory locations relative to the stack
segment register.
The values held in these registers can be read, loaded, or modified through software. The pointer
and index registers are only accessed as words. To use the offset address in a register, the instruction simply
specifies the register that contains the value.
The values in SP and BP are used as offsets from the current value of SS during the execution of
instructions. These involve the stack segment of memory and permit easy access to storage locations in the
stack part of memory. The value in SP always represents the offset of the next stack location that is to be
accessed.
Base Pointer represents an address with in the stack segment; but, it is used to access data within
the stack segment of memory. This register also used in base addressing mode. BP is use to reference
parameters that are passed to a subroutine by way of the stack. In this case, instructions are included in the
subroutine that use based addressing to access the values of parameters from the stack.
The index registers are used to hold offset addresses for instructions that access data stored in the
data segment of memory and are automatically combined with the value in the DS or ES register during
address calculation.
In instructions that involve the indexed addressing, the source index (SI) register holds an offset
address that identifies the location of a source operand, and the destination index (DI) register holds an
offset for a destination operand.

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Any of the data registers can be used as the source or destination of an operand during an arithmetic
operation such as ADD, or a logic operation such as AND. But, for some operations, an operand that is to be
processed may be stored in memory instead of the internal register.
An index address is used to identify the location of the operand in memory; For example, string
instructions use the index registers to access operands in memory. SI and DI are the pointers to the source
and destination locations in memory.
The index registers can also be source or destination registers in arithmetic and logical operations.
For example, an instruction may add 2 to the offset value in SI to increment its value to point to the next
word-wide storage location in memory.

Question 10: Explain 8086 flag register in brief. (S-13/7M)

9. Status/Flag Register
The status or flag register indicates the condition of microprocessor and controls its operation. It is
16-bit in length and only nine of its bits are implemented. Six of these bits represent status flags:
 The carry flag (CF)
 Parity flag (PF)
 Auxiliary carry flag (AF)
 Zero flag (ZF)
 Sign flag (SF), and
 Overflow flag (OF)
The logic state of these status flags indicate conditions that are produced as a result of executing an
instruction. That is, after executing an instruction, such as ADD, specific flag bits are reset (logic 0) or set
(logic 1) based on the result that is produced.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IE TF SF ZF AC PF CF
Figure 17: Flag Register

a) Status Flag Register

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1. Carry Flag (CF): CF is set to 1 if there is a carry-out during addition or a borrow-in during subtraction
for the most significant bit of the result during the execution of an instruction. Otherwise, CF is reset
to 0.
2. Parity Flag (PF): PF is set to 1 if the result produced by the instruction has even parity i.e., if it
contains an even number of bits at the 1 logic level. If parity is odd, PF is reset to 0.
3. Auxiliary Carry Flag (AF): AF is set to 1 if there is a carry-out from the low nibble into the high nibble
or a borrow-in from the high nibble into the low nibble of the lower byte in a 16-bit word. Otherwise,
AF is reset to 0.
4. Zero Flag (ZF): ZF is set to 1 if the result produced by an instruction is zero. Otherwise, ZF is reset to
0.
5. Sign Flag (SF): If it is set, it indicates that the sign of result is negative. It is reset to 0 if the sign is
positive.
6. Overflow Flag (OF): When OF is set to 1, it indicates that the result is out of range. If the result is not
out of range, OF is reset to 0.

b) Control Flag Register

The other three control flag bits are the direction flag (DF), the interrupt enable flag (IF), and the trap
flag (TF). These three flags provide control functions of the 8086:
1. Trap Flag (TF): If TF is set to 1, the 8086 goes into the single-step mode M operation. When it is in
the single-step mode, it executes an instruction and then jumps to a special service routine that may
determine the effect of executing the instruction. This type of operation is very useful for debugging
programs.
2. Interrupt Flag (IF): It is used to enable or disable maskable interrupt request at INTR pin. If it is set to
1, the interrupt request is recognized (enabled). If reset to 0, the request is ignored (disabled).
3. Direction Flag (DE): The logic level of DF determines the direction in which string operations will
occur. When set, the string instruction automatically decrements the address; so, the string data
transfers proceed from high address to low address. On the other hand, resetting DF causes the
string address to be incremented i.e., data transfers proceed from low address to high address.

Question 11: Explain how physical address generation unit of 8086 work. With
16 suitable example explain how 8086 generates a physical address
Assembly toProgramming
Language fetch an
instruction from memory. (S-12/7M)
 Unit – I

10. Memory Address Generation

In the 8086 microcomputer system, a segment base address and an offset address describe a logical
address. Figure 18 shows both the segment base address and offset address, they are 16-bit in length and
the physical address that is used to access memory is 20 bits in length.
15 0
16 Offset Address Value Offset

15 0
Segment Register 0000 Segment Address

ADDER

19 0
20-Bit
Physical Memory Address

Figure 18: Generating Physical Address

The generation of the physical address involves combining a 16-bit offset address value that is
located in the instruction pointer, base register, source index, destination index, base pointer or stack
pointer register and a 16-bit segment base address value always resides in one of the segment registers: CS,
DS, SS, or ES. Following formula can be used to calculate 20-bit physical address.

20-bit Physical Address = 16-bit Offset Address + 16-bit Segment Address * 10

Figure 20 shows how a segment base address value in a segment register and an offset address
value are combined to form a physical address. The value in the segment register is shifted left by four bits a
Assembly Language Programming 17
Unit – I

position, with its LSB’s filled with zeros. This gives a segment address, the location where the segment
starts. The offset value is then added to the 16-bit LSB’s of the shifted segment value. The result of this
addition is the 20-bit physical address.
Example:
When an instruction execution takes place, the source of the segment base address is always the
code segment (CS) register, and the source of the offset address is always the instruction pointer (IP). This
physical address can be denoted as CS : IP.
Shift left 4 bits 1 2 3 4 Segment Base Address
1 2 3 4 0 15 0 Logical
19 0 0 0 2 2 Offset Address Address
15 0
0 0 2 2
15 0

1 2 3 6 2 Physical Address
19 0
To Memory
Figure 19: Example of physical address calculation
The example in the above figure represents a segment base address value of 123416 and an offset
address value of 002216.
First, express the segment base address value in binary form. We get,
123416 = 00010010001101002
Shifting left four positions and filling with zeros results in the segment address.
000100100011010000002 = 1234016
The offset address in binary form is
002216 = 00000000001000102
Adding segment address and the offset address, we get
000100100011010000002 + 00000000001000102 = 000100100011011000102
= 1236216
= 12362H
a) Steps for calculating 20-bit physical address
Step 1: Add 0 (zero) at the end of given segment address or multiply by 10. For example, if the
18 segment address is 123416 then after adding 0 at the end or byLanguage
Assembly multiplying by 10, we
Programming
get 1234016.
Step 2: Represent the result obtained in step 1 in binary number system.
Step 3: Represent the offset address in binary number system.
Step 4: Perform the binary addition of results obtained in step 2 and step 3 which is the
required 20-bit physical address.
 Unit – I

Example:
Given Segment Address = 1020 and Offset Address = 1234.
Calculate Physical Address.
Solution:
Step 1: Adding 0 at the end of segment address or multiplying segment address by 10, we get 1020016.
Step 2: Representing the 1020016 in binary number system as:
1020016 = 0001 0000 0010 0000 00002
Step 3: Representing the offset address 1234 in binary number system as:
123416 = 0001 0010 0011 01002
Step 4: Performing binary addition of result obtained in step 2 and step 3 we get,
0001 0000 0010 0000 00002 + 0001 0010 0011 01002 = 0001 0001 0100 0011 01002
= 1143416

Solution to Questions asked in University Examination

Question 1: Consider the following table and answer the questions:
Memory Address Data
0072DH 1101 1111
0072CH 0101 0101
i) What is the data word shown in the table?
ii) Express the data word in Hex.
iii) Is it stored at even or odd address?
iv) Is it aligned or misaligned word of data? (S-12/4M)

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Solution:
The most significant byte of the word is stored at address 0072D16 and equals
110111112 = DF16 = DFH
Its least significant byte is stored at address 0072C16 and is
010101012 = 5516 = 55H
Together the two bytes give the word
11011111010101012 = DF5516 = DF55H
Expressing the address of the least significant byte in binary form gives
0072CH = 0072C16 = 000000000111001011002
Because the rightmost bit (LSB) is logic 0, the word is stored at an even-address boundary in
memory; so, it is an aligned word of data.

Question 2: Find the unknown value for each of the following physical addresses:
i) ? : 14DA = 235DA ii) D765 : ? = DABC0
iii) ? : CD21 = 32D21 iv) B2C0 : FA12 = ? (W-12/4M)

Solution:
By using the steps given in generating memory address and the following formula:
Physical Address = Segment Address * 10 + Offset Address
i) Given Offset Address = 14DA, Physical Address = 235DA, Segment Address = ?
Segment Address * 10 = Physical Address – Offset Address
Segment Address * 10 = 235DA – 14DA = 22100
Segment Address = 2210H

ii) Given Segment Address = D765, Physical Address = DABC0, Offset Address = ?
Offset Address = Physical Address – Segment Address * 10
Offset Address = DABC0 – D765 * 10 = DABC0 – D7650 = 3570
Offset Address = 3570H

iii) Given Offset Address = CD21, Physical Address = 32D21, Segment Address = ?
Segment Address * 10 = Physical Address – Offset Address
20 Assembly Language Programming
 Unit – I

Segment Address * 10 = 32D21 – CD21 = 26000

Segment Address = 2600H
iv) Given Segment Address = B2C0, Offset Address = FA12, Physical Address = ?
Physical Address = B2C0 * 10 + FA12 = B2C00 + FA12 = C2612H

Question 3: Consider that the contents of various registers are as below:

[CS] = 03E0H; [IP] = 1 F20 H; [SP] = 3 FFEH [SS] = 0400H;
[BP] = 3420H; [DI] = 4000 H [DS]=2400H.
Answer the following:
i) From what address is the next instruction fetched?
ii) Where is the top of stack located?
Solution:
i) CS : IP which is 03E0H : 1F20H; Physical Address can be calculated as:
Physical Address = Segment Address * 10 + Offset Address
= 03E0 * 10 + 1F20 = 03E00 + 1F20 = 05D20H
ii) SS: SP which is 0400H : 3FFEH. Stack top address can be calculated0 as:
Physical Address (Stack Top Address) = 0400 * 10 + 3FFEH = 04000 + 3FFE = 07FFEHH

Question 4: Calculate the value of each of the physical addresses that follows. Assume all numbers are
hexadecimal numbers:
i) 1000:1234 ii) 0100:ABCD iii) A200:12CF iv) B2C0: FA12
Solution:
By using the steps given in generating memory address and the following formula:
Physical Address = Segment Address * 10 + Offset Address
i) Given Segment Address = 1000, Offset Address = 1234, Physical Address = ?
Physical Address = 1000 * 10 + 1234 = 10000 + 1234 = 11234

ii) Given Segment Address = 0100, Offset Address = ABCD, Physical Address = ?
Physical Address = 0100 * 10 + ABCD = 01000 + ABCD = 0BBCD

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Unit – I

iii) Given Segment Address = A200, Offset Address = 12CF, Physical Address = ?
Physical Address = A200 * 10 + 12CF = A2000 + 12CF = A32CF

iv) Given Segment Address = B2C0, Offset Address = FA12, Physical Address = ?
Physical Address = B2C0 * 10 + FA12 = B2C00 + FA12 = C2612
Question 5: The contents of memory location B0000H are FF16 and those at B0001 Here 0016. What is the
data word stored at address B0000H? Is the word aligned or misaligned?
Solution:
The data word at address B0000H is 00FF. Starting address of data word is B0000H, which is even
address so data word is stored at even address boundary; therefore it is aligned word data. This is shown in
figure.
Address Memory
B00000H FF
B00001H 00

Question 6: What would be the offset required to map to physical address location 002C316 if the contents
of the corresponding segment register are 002A16?
Solution:
Given Segment Address = 002A and Physical Address = 002C3,
Offset Address = ?
Offset Address = Physical Address – Segment Address * 10
Offset Address = 002C3 – 002A * 10 = 002C3 – 002A0 = 0023
Offset Address = 002316

Question 7: Show how a double word 12345678H is stored in memory starting at address 0ABCDEH. Is the
double word aligned or misaligned? Explain.
Solution:
The double word 12345678H is stored at address 0ABCDEH as shown in following figure. This data is
stored by using byte swapping concept.

22 Assembly Language Programming

 Unit – I

Starting address of double word is 0ABCDEH, which is even address so double word is stored at even
address boundary; therefore it is aligned double word data. This is shown in figure.
Address Memory
0ABCDEH 78
0ABCDFH 56
0ABCE0H 34
0ABCE1H 12

Question 8: Show how the word ABCD16 is stored in memory starting at address 0A00216. Is the double
word aligned or misaligned?
Solution:
The word ABCD16 is stored at address 0A00216 as shown in following figure. Starting address of
double word is 0A00216, which is even address so word is stored at even address boundary; therefore it is
aligned word data. This is shown in figure.
Address Memory
0A002H CD
0A003H AB

Question 9: If the current values in the code segment register and the instruction pointer are 020016 and
01AC16, what physical address is used in the next instruction fetch?
Solution:
Given Segment Address (CS) = 020016, Instruction Pointer (IP) = 01AC16, Physical Address = ?
Physical Address = Offset Address + Segment Address * 10
Physical Address = 01AC16 + 020016 * 10 = 01AC16 + 0200016 = 021AC16
Physical Address = 021AC16

Previous University Examination Question

Papers
(Summer – 2012)

Assembly Language Programming 23

Unit – I

Q. a) Draw the micro-architecture of 8086. Explain the functions of Execution Unit (EU) and Bus Interface
Unit (BIU). 10
b) Consider the following table and answer the questions:
Memory Address Data
0072DH 1101 1111
0072CH 0101 0101
i) What is the data word shown in the table?
ii) Express the data word in Hex.
iii) Is it stored at even or odd address?
iv) Is it aligned or misaligned word of data? 4
OR
Q. a) Explain how physical address generation unit of 8086 work. With suitable example explain how 8086
generates a physical address to fetch an instruction from memory. 7
b) Explain in detail memory address space in 8086/88 based system. What are the fundamental data
formats supported by 8086? How these data formats can be organized in memory? 7

(Winter – 2012)
Q. a) Draw and explain micro-architecture of 8086. How 8086 supports parallel processing? 10
b) Find the unknown value for each of the following physical addresses:
i) ? : 14DA = 235DA ii) D765 : ? = DABC0
iii) ? : CD21 = 32D21 iv) B2C0 : FA12 = ? 4
OR
Q. a) What are segment registers? Why memory is segmented? How memory segmentation is done? 7
b) Draw and explain software model of 8086. 7

(Summer – 2013)
Q. a) Draw and explain internal architecture of 8086 microprocessor. 10
b) Explain 8086 flag register in brief. 4
OR
Q. a) Explain the register organisation of 8086. 7

24 Assembly Language Programming

 Unit – I

b) Explain how memory is segmented and accessed in 8086 giving suitable example. 7

(Winter – 2013)
Q. a) Explain Physical Memory Organisation of 8086. 7
b) Explain the concept of Memory Segmentation used in 8086. 7
OR
Q. a) Explain the following pin configuration of 8086:

i) DT / R

ii) M / I / O

iii) LOCK 6
b) Explain Register Organisation of 8086. 8

Assembly Language Programming 25