Proceedings of the 6th International Conference on Communication and Electronics Systems (ICCES-2021)

IEEE Xplore Part Number: CFP21AWO-ART; ISBN: 978-0-7381-1405-7

Reversible 2:4 Decoder Using Universal Fredkin

Gate
Gudipati Nikhil B. Sharanya
Electronics and communication engineering Electronics and communication engineering
Vardhaman college of engineering Vardhaman college of engineering
Hyderabad, Telangana Hyderabad, Telangana
gudipatinikhil@[Link] sharanyabalagoni19@[Link]

P. Bharath Reddy R. Phani Vidyadhar

2021 6th International Conference on Communication and Electronics Systems (ICCES) | 978-1-6654-3587-1/21/$31.00 ©2021 IEEE | DOI: 10.1109/ICCES51350.2021.9489226

Electronics and communication engineering Electronics and communication engineering

Vardhaman college of engineering Vardhaman college of engineering
Hyderabad, Telangana Hyderabad, Telangana
bharathreddyp007@[Link] rphaniv@[Link]

Abstract: The technologies like quantum computing, sequential circuits, as result various reversible logic[6]
Nanotechnology is emerging due to the greater research in designs can be optimized.
reversible logic. It has the power reduction capability the
same mechanism is also having in the quantum computing. In Basic concepts it introduces the concepts of basic
Designing a quantum circuit among various combinational reversible gates used, where the proposed work section
circuits the decoder has capability to change binary gives the complete design of 2:4 decoder[10] and at last
information of input lines to distinct output lines and also compared with other designs.
there are many applications where decoder is the main basic
component. In this paper a comprehensive introduction of
II. BASIC CONCEPTS
basic gates used to design n to 2 n Universal Quantum A. Fredkin gate
decoder, here n represents the no of inputs are mentioned.
The proposed 2:4 decoder circuit is designed using a For reversible computing the Fredkin gate is one among
universal reversible Fredkin gates and Feynman gate . The the various computational circuits which is advisable. As
proposed work is simulated using IBM Quantum Composer.
In comparison to existing quantum decoders the proposed Fredkin gate realizes all the basic logical operations it is
decoder design has optimum values in all the parameters known as universal gate. This gate consists of 3 input
considered. lines, 3 output lines where the first output line will be
replica of first input line and the last two output lines gets
swap if the first input line is 1. This gate is also knowns as
Keywords—Reversible, Quantum, Fredkin gate, Feynman controlled swap gate[14] because it maps the 3 input lines
gate, Combinational Circuits, Decoder, Quantum cost, (C, A, B) with the 3 output lines (R, P, Q). The output
Garbage outputs, Comparators.
lines will be
I. INT RODUCT ION
In Quantum designing the important parameters which are R=C,
to be consider are QuantumCost(QC), no of garbage P=AC`+BC,
Outputs(GO) and no of Constants(NC)[15]. So, while Q=AC+BC`.
designing a quantum circuit the objective is to be deplete
the QC, GO, NC[16]. In reversible computing systems the
combinational circuits namely comparators, multipliers,
subtractors, adders are the essential circuit components.

The research in reversible combinational logic circuits is

being performed from many years by various
researchers[4,6]. As there is a scope of optimizing the
existing designs, we have chosen 2:4 decoders among
various combinational circuits.
This paper introduces a reversible 2:4 decoder circuit with
optimized QC, GO, NC using lesser number of gates . A
decoder can be used in various combinational or
Fig. 1. Fredkin Gate

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 Proceedings of the 6th International Conference on Communication and Electronics Systems (ICCES-2021)
IEEE Xplore Part Number: CFP21AWO-ART; ISBN: 978-0-7381-1405-7

The below table shows the Fredkin gate truth table. C. Decoder

Decoder performs the reverse operation of encoder which

C A B R P Q consists ‘n’ input lines and 2n number of output lines. In
decoder only one of the output lines will be 1 (high) and
0 0 0 0 0 0
other output lines will be 0 (low) if it is active high and
0 0 1 0 0 1 vice versa for active low.
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 1 0 0
1 0 1 1 1 0
1 1 0 1 0 1
1 1 1 1 1 1

Table.1[17]
Fig.3. 2:4 decoder
B. Feynman gate
.
Controlled-not gate (CNOT) is the other name of The truth table of 2:4 decoder[18] as shown below
Feynman gate. This gate consists of 2 input lines and 2
output lines, where the first output line will be same as I1 I0 Y3 Y2 Y1 Y0
first input line and the second output line will be 0 0 0 0 0 1
depending on both input lines as it gives XOR of both
input lines. This gate is named Controlled-not gate 0 1 0 0 1 0
because the not operation of second input line depends on
the first input line (acts as control). If control is 1 not 1 0 0 1 0 0
operation performed and vice versa. The output lines will 1 1 1 0 0 0
be

P=A Table.3
Q=A XOR B
From the truth table[18], the output lines can be realized
by following expressions.

Y3 = I1. I0
Y2 = I1. I0`
Y1 = I1. I0
Y0 = I1. I0`
Ref[11]
Fig. 2. Feynman Gate[1] .

The below table shows the Feynman gate truth table[16]. III. Proposed Work

In this proposed work, the description of 2:4 decoder

designed using 1 Feynman gate (FEYG) and 2 Fredkin
A B P Q gates (FG), also about the [21]Quantum Cost, Garbage
Outputs and Constant Inputs of proposed design. The fig
0 0 0 0 shows I0 and I1 are the encoded input given to FG1 at C
and A terminals. The B input of FG1 and FG2 are ‘0’,
0 1 0 1 then P of FG1 is AC’=D2 and Q is AC=[Link] Feynman
gate output Q will be I1’ as the Q of FeyG will be (A ⊕1)
1 0 1 1 which is propagated to FG2 at A terminal. Then at P
terminal of FG2 (A⊕1) C’=A’C’=D0 and at Q terminal
(A⊕1) C=A’C=D1 are observed.
1 1 1 0

Table.2[17]

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 Proceedings of the 6th International Conference on Communication and Electronics Systems (ICCES-2021)
IEEE Xplore Part Number: CFP21AWO-ART; ISBN: 978-0-7381-1405-7

IV. Conclusion and Future Scope

When compared to the existing 2:4 decoder designs, the

existing designs either have more quantum cost or they
used more no of gates to design a decoder. In the proposed
design, we can see that the parameter quantum cost is less
compared to the quantum cost of the existing design ,
similarly for garbage outputs and constant inputs. In the
proposed design number of gates is comparatively
reduced when compared to existing designs. The proposed
2:4 decoder is having optimal values in all the parameters
being consider like quantum cost, no of constant inputs,
no of garbage outputs. The values obtained in this design
are quantum cost(QC)= 11, number of garbage
outputs(GO)=1 and constant inputs (CI)= 2 they are in
Fig.4. 2:4 decoder using Fredkin gate between which satisfies all the parameters.
The reversible quantum 2:4 decoder proposed in this
paper can be used in future to implement various other
The Decode input terminals are I1 I0 and the output reversible logic designs, converting analog to digital, in
terminals are D3=AC, D2=AC’, D1=A’C, D0=A’C’. The address decoder circuits and also has many other
proposed design [21,9]Quantum cost, Garbage outputs, applications in quantum computing.
Constant inputs, no of gate are 11, 1, 2, 3.
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 Proceedings of the 6th International Conference on Communication and Electronics Systems (ICCES-2021)
IEEE Xplore Part Number: CFP21AWO-ART; ISBN: 978-0-7381-1405-7

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