2.

Resisler File : Atoce qeneral p po

RISC-V batapath resisters that can be read n wrHen
resister
A Gng le core proces or contains : by speciyhng the number
batapatlk (braw): harduae ’ read: in put: reg. emn. outpur.
necbars to perJam operatiod dron reQ. fle with waue that has
OContraf(braio): tells the daBapalk been read
w hal nee ds to be done.
-Wrile: input: reg. num reg. to
One Tnstruction per cyde RISCV be written on + re. nm t daa.
machine
Peod

Comaiak bal RRes,d

Read
daa A
loqne 1sgisles,2
blocki Reqjskes

bala
stale
elenent
CeK

every tiek 3 current outpud

fepeat sTate elementa divea input to cl
1Atauy there wnh rising edoe SIYl : read oay Lfeeli
all state elemena 3. bata memory bn E: lcadiag (read)
updaled e
with curent eL out put tsteri g lwr te dota wz
’ead : emRecd=
batapath Elemen: uni b that Addres3 wrteiRmWcie= A
opeake /hald data wthin a aocesor BoBo Tw data bw
LyInstfuch tn memory Write
2- bala memog bala

3. Regis ler le Iem Read

4o ALu
5. Adders Sraga & Instruction execution
G. PC do Feteh (IF): nsructon co ma ia1
PC to o addres, cpu Atna
SBate element:
daa in instruction memory
A. PC: 32 bit regsler hotdi ag the 2. becode (I)+ ead resis larc : Fgure
adtees a cuscent nst
wçite enable out which operahiÝn is asted to be
made read wrte ...
baBa In bata Ou
3. Exeute EX)+ ALL: instruchi on u
louput peraned.
bw
CeK
yo Remog acces (ner): etriee /
doa in =out Atae dara (not aluay)
’ write EnableA, ?
ele data out = Cur rent value 5. Wce Back to Regivter (wB):
sa< explanotay (nat alway)
Buiedine a dalapath : miig hhew to resgsker
a

menory instactiond (lwisuw) ’ store

arth mehic isical instruct oesladd sub)
Cond. branch inst. (bes) 2. bype:I s
Implementakion: 3./
An2Fetoh t deeode
3" dependA on insto clas Wi te Sases
[Link] nem Rw =
do not yon wi res
ug muthpleres duh rs 2 to memoíy resisters ?=
wnit controled depending n inst.
(i.e: rend load, wrtestorei to compue e branch
reg-fe wrtten on load /AL instrucin farqer addres elah e to branch
inSt. addres
p)
I ALu perams oAe
Con[Link] unit has inst. as branch targeB:szt etd insr t
input deleimines how to set the
Confrel wnes do punchon l unit cnd addres the branch.
two f the mieiplexex,
check side nm
fset fieeds ere
4 to doube their eyecke an
-ihe branch target adtes eplaca the
’fehch the instrchion Rom RC when the branch co ndition u
mémoryi incement Pe pont mek ele PC s incremented.
to next insrruchon 4by tes larer - resister lee proaes operands
j these compue e men ory
fa compi son dia Au { by subs trachio
add res by ading the BK to the
A. IR PCSee - taken, updoate PC
he inS [Link]. to Au outpur, elye updae to nert
insruchion PC t4.
resster ile t ALU t unit to Q. Buied imm fom B ty pe instruch, on
Aen erterd the A2 lait retd to
a 32- lait nmed oalue in the inst. 3- Co npute branch ifeed to Cont
Compute PC +im m
+ data memory
4. bon't wri te o memoy/ ressters
’ load;
A. Tncrement to nert inst add |sub
Q. Immediale Generation block A. Tncement pc to next ins trucion
builds 32 it in fhedi ate
3. ALu omputes eddras au =R[sA instruchion decoding
into Reg hRk
+ immm 3. Spur iastruchion to in der
to ALU
4. Feed read resisrer walue
4. Read memy addres
addres at au 5. wri te ALu ourput to dest. rapit
5. Wite loaded memory vaue ka Bo contro!, une ALUsee select ohih
Al cmet On to Ouroul
 ’ addi

3, conrl ine Bsel - A

selec
generated immediate imn to ALetheinpulß
4o Wrte Au output to
det naton
rskr
Jal:
[Link] PC nto bloeks wike Au
out ut to PC
2. Genente byle
20- it PC relaki eotet imm pr
jump
3. Compule PC +imm
4. Wite C+4 to des [Link]
raister
’jali

3. Com pte s+ imm

(T fama)

A. Tnceent pC to nextinstuctin
2. Generate imm with wpper do ots
(u- famot}
3. Erab only itmm ( AlUsel -8)

’ auipc :

3. Add PC + iomvm

The compleie RV3A Jalaath Ahagy

the (orrect g,cs