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System-Level Early Power Estimation for Memory Subsystem in Embedded

Systems

Conference Paper · November 2008

DOI: 10.1109/SEC.2008.48 · Source: IEEE Xplore

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 Fifth IEEE International Symposium on Embedded Computing

System-level Early Power Estimation for Memory Subsystem in Embedded

Systems

Jinsong Ji1,2+ Chao Wang1,2 Xuehai Zhou1,2

1 2
Dept. of Computer Science Embedded System Laboratory
University of Science and Technology of China Suzhou Institute for Advanced Study,USTC
Hefei, Anhui, 230027, China Suzhou, Jiangsu, 215223,China
jsji@[Link] xhzhou@[Link]
saintwc@[Link]

Abstract

Early power estimation is important to guide architec-

tural design, especially for embedded systems. Since the
power consumption of memory subsystem dominates, while
DRAM and NAND Flash are the two main storage medi-
ums nowadays, we analyze the power model of DRAM and
propose a power model for NAND Flash, considering its
system-level behaviors. Experimental results show that the
accuracy of model proposed can be up to 95% .

Figure 1. Typical Memory Hierarchy

1. Introduction

Nowadays, power consumption is already one of the

leading constraints in designing embedded systems[8]. And In this paper, we propose a mathematical power model
memory system cost is a major factor in the total power for typical memory subsystem in embedded systems, which
consumption[12, 7].A share of up to 80% of the total power can help designers gain accurate power budgets in early
has been attributed to the memory subsystem in the sig- stage of architecture design, requiring only the knowledge
nal processing domain [2]. So system designers are paying of system level behaviors and related medium parameters.
more and more attention to memory subsystem powers. We first analyze the main components of modern memory
In order to create power efficient designs, accurate power hierarchy, then describe the power model of DRAM pro-
budgets for the memory subsystem are essential, whether it vided by Micron[5] and propose our model of NAND Flash
is for calculating battery life, planning cooling system, or in details; after that we show our experimental results which
determining the power supply. verified the models presented.
Though there have been several different power estima-
tion techniques[6, 9, 15, 16, 3, 12, 11] and different related
tools, such as SimplePower[14], Wattch[1], JouleTrack[13], 2 System-level Power Models
VPR[10] et al; most of them focus on micro-architecture
level power estimation. System designers usually could not As shown in Fig.1, the typical memory hierarchy of to-
utilize these techniques or tools in early design stage, be- day’s embedded systems consists of three or more type of
cause they may not have enough micro-architecture infor- memory: Cache, RAM, Flash et [Link] power consumption
mation, or enough time to run a whole simulation for the of Cache is usually calculated within controllers or proces-
design. Another problem is that most of the tools focus [Link], we would like to focus on RAM and Flash
on processors or controllers, memory subsystems are ig- in the following sections. As to RAM, though there are sev-
nored,to say nothing about memory hierarchies. eral kinds of RAM, such as SRAM, DRAM, VRAM et al,

978-0-7695-3348-3/08 $25.00 © 2008 IEEE 370

DOI 10.1109/SEC.2008.48
 Meanwhile, DRAM have to refresh in the background. We
assume that the device is in precharge power-down state
most time except when the actual REFRESH commands are
executed. Thus, the average extra power for refresh com-
mand is:

PREF = (IREF − Ipre−pdn ) × VDD

2.1.2 Activate Power

All DRAM banks have to be activated (ACT) first before
read/write access. After the ACT command, a large amount
of current is used to decode the command/address and trans-
fer data from the DRAM array to sense [Link] this
is complete, the DRAM is maintained in an active state and
draws Iact−pre until a PRE command is issued. The PRE
command restores the data from the sense amplifiers into
the memory array and resets the bank for the next ACT
command. Once this is complete, the device is returned
to precharge state. This cycle is then repeated at tRC inter-
vals between ACT commands. Notice that CKE is always
held HIGH during this period, we have to subtract the back-
Figure 2. Typical State Machine of DRAM[4]. ground current it draws. Therefore, the activate power is:

PACT = (Iact−pre − Iact−stby ) × VDD

most of them are more or less working in the same mech- But as DRAM may work in lower clock frequency or bank
anism; and the DRAMs are the most prevalent ones, so we interleave mode, the interval between two ACT commands
decided to analyze the DRAM power model as a represen- is not always tRC. Fortunately, it is easy to scale the ACT
tative. As for Flash, many current designs are moving to- current for other modes of operation.
wards NAND Flash to take advantage of its higher density nREAD
and lower cost, so we choose to model NAND Flash instead PACT = (Iact−pre − Iact−stby ) × × VDD
nACT
of NOR Flash.
2.1.3 Read/Write Power
2.1 DRAM Power Model
During read/write access, assume that the currents are
Iread and Iwrite respectively. The the read/write pow-
According to the working mechanisms of DRAM, its
ers can be calculated as follows:
power consists of three key components: background
power, activate power, read/write power. nREAD
PREAD = (IREAD − Iact−stby ) × × VDD
nACT
nW RIT E
2.1.1 Background Power PW RIT E = (IW RIT E − Iact−stby ) × × VDD
nACT
As shown in Fig.2, CKE signal is the master on-off switch But the equations above are not the complete answer. To
of DRAM. When CKE is LOW(CKEL), the DRAM goes drive the outputs, additional DQ currents are required.
into PowerDown state; and when it is HIGH(CKEH), the
DRAM goes into Active state. The current changes during PperDQ = VOU T × IOU T
these transitions even without read/write access. So we can nREAD
PDQ = PperDQ × (nDQ + nDQS ) ×
calculated these background powers easily. nACT

Ppre−pdn = Ipre−pdn × VDD 2.1.4 Total Power of DRAM

Pact−pdn = Iact−pdn × VDD
After showing the basic components above, it is now in
Ppre−stby = Ipre−stby × VDD place to calculate the total power. Considering different us-
Pact−stby = Iact−stby × VDD age conditions, the parameters as in Table 1 are needed for

371
 Table 1. Parameters for DRAM Model
Typical
Symbol Comments
Values
ppre Percentage of time all anks are precharged 40%
pckpre Percentage of the PRE time when CKE is LOW 50%
pckact Percentage of the ACT time when CKE is LOW 0%
tACT The average time between ACT commands 120 ns
pREAD Percentage of CK cycles that output read data 1%
pW RIT E Percentage of CK cycles that input write data 24%

input. The total power of DRAM is:

Ptotal = Pbg + PACT + PR/W

where:
Figure 3. Flash Operation Diagram
Pbg = Ppre−pdn × ppre × pckpre
+ Ppre−stby × ppre × (1 − pckpre )
+ Pact−pdn × (1 − ppre ) × pckact where
+ Pact−stby × (1 − ppre ) × (1 − pckact ) ∗
PREAD ∗
= IW ∗
cmd+addr RIT E × VDD
+ PREF ∗
PREAD ∗
= IREAD ∗
× VDD
data
PR/W = (PREAD + PDQ ) × pREAD + PperDQ × (n∗DQ + n∗DQS )
∗

+ PW RIT E × pW RIT E ∗
PperDQ ∗
= VOU ∗
T × IOU T

∗
Most of the parameters in the equations can be found in Here, VDD is the maximum voltage which can be found in
∗ ∗ ∗ ∗
DRAM’s datasheet, others such as read/write percentage the datasheet. IW RIT E , IREAD , VOU T , IOU T , are also
∗ ∗
can be easily estimated in early design stage. provided by vendor. pREADcmd+addr and pREADdata are
the percentage of time consumed in each stage. They could
2.2 NAND Flash Power Model be calculated easily from the timing diagrams, and are al-
most constant. n∗DQ and n∗DQS are the pin number of
Compared to DRAM model, NAND Flash are simpler. outputs and their strobes.
In standby state, the Flash could not be accessed, the current
∗
Istandby is usually small enough to be ignored. In operation 2.2.2 Program Power
state, as shown in Fig.3, a typical flash operation includes at
least three stages: command, address, data. Notice that the For PROGRAM and ERASE operations, we have to include
command and address stages are almost the same for all op- the stage of status, when some specific bits of status regis-
erations (READ/PROGRAM/ERASE), except for different ters are read to confirm the success of operation.
command codes, we denote them as cmd+addr stage. PP∗ ROG = PP∗ ROGcmd+addr × p∗P ROGcmd+addr
+ PP∗ ROGdata × p∗P ROGdata
2.2.1 Read Power
+ PP∗ ROGstatus × p∗P ROGstatus
The read operation consists of only two major stages, so the
average power can be calculated according to their percent- where
ages:
PP∗ ROGcmd+addr ∗
= IW ∗
RIT E × VDD
∗
PREAD ∗
= PREAD × p∗READcmd+addr PP∗ ROGdata ∗
= IW ∗
RIT E × VDD
cmd+addr
∗
+ PREAD × p∗READdata + PperDQ × (nDQ + n∗DQS )
∗ ∗
data

1 We consider only the typical interface defined by ONFI(Open NAND Flash In-
PP∗ ROGstatus ∗
= IREAD ∗
× VDD
∗
terface). + PREAD × p∗polling

372
 Table 2. Parameters for NAND Flash Model Table 3. Measured Power data of DDR DRAM
Typical Assembly Binary Current Power
Symbol Comments Operations
Values Code Code (A) (W)
p∗READ Percentage of READ operation 1% Only Bootloop 0.87 4.35
p∗P ROG Percentage of PROGRAM operation 24% No Memroy Access BRI 0 B8000000 0.9 4.5
p∗ERASE Percentage of ERASE operation 24% ADDIK r3,r0,0 30600000
IMM 10240 B0002800
Write all ”0” 1.21 6.05
SWI r3,r0,0 F8600000
Here all parameters have the same meanings with READ BRI -8 B800FFF8
operation, except for p∗polling . p∗polling is the ratio of data
ADDIK r3,r0,-1 3060FFFF
polling during the whole programming progress, it depends
on the software implementation. If user uses R/B pins to IMM 10240 B0002800
Write all ”1” 1.16 5.8
determine the end of operation, then there would be only SWI r3,r0,0 F8600000
one polling operation; otherwise user has to read the status BRI -8 B800FFF8
register time and time again to check whether the program- IMM 10240 B0002800
ming is still in progress. The maximum number of polling Read 1.35 6.75
LWI r3,r0,0 E8600000
is k = t∗status /t∗polling , where tstatus is the total time of
BRI -8 B800FFF8
status checking and tpolling is the time of one single data
polling. So, a The Working Voltage of Development Board is 5 V

t∗polling × k
p∗polling = where k ∈ [1, t∗status /t∗polling ].
t∗status
3.1 DRAM Model
2.2.3 Erase Power
We developed benchmarks in assembly within Xilinx
ERASE operation is mostly the same as PROGRAM, ex- EDK, debugged them with XMD and measured the current.
cept that ERASE doesn’t have data stage. So, First, we downloaded the bootloop program into its embed-
∗ ∗ ded CPU, measured the current of board without DRAM
PERASE = PERASE × p∗ERASEcmd+addr
cmd+addr module to gain the basic power for all other modules on
∗
+ PERASEstatus
× p∗ERASEstatus board. Then we installed the DRAM module and down-
where loaded a benchmark with one single loop, without access-
∗ ∗ ∗
ing DRAM, to measure the background power of DRAM.
PERASEcmd+addr
= IW RIT E × VDD After that, we downloaded benchmarks reading and writ-
∗ ∗ ∗
PERASEstatus
= IREAD × VDD ing DRAM to gain the related powers. Finally, we got the
∗
+ PREAD × p∗polling results in Table 3 and related powers calculated below:

Pbg = (4.5 − 4.35)/8 W = 18.75mW

2.2.4 Overall NAND Flash Power PREAD = (6.75 − 4.5)/8 W = 281.25mW
Considering the parameters in Table 2 for input, we have: PW RIT E = (6.05 + 5.8)/2 − 4.5)/8 W = 178.125mW
∗ ∗
Ptotal = PREAD × pREAD + PP∗ ROG × pP ROG Meanwhile, we got 12.9mW, 229 mW and 187.6 mW re-
∗
+ PERASE × pERASE spectively from the DRAM model. Fig. 4 shows the com-
parison of two data sets, indicating that the accuracy of
Now we can estimate the total power of NAND Flash with DRAM model could reach 95%.
only the knowledge of operation percentages.
What is more, with these two key component models, we
3.2 NAND Flash Model
could estimate the power of whole memory subsystem, re-
quiring only the hierarchy and system-level information.
In order to verify the NAND Flash power model, we
also developed benchmarks in NIOS II IDE. We used the
3 Experimental Results C APIs provided by Altera’s flash driver to access the flash,
then collected the current data in Table 4, and calculated its
For evaluation, we use Xilinx’s Vertex-II Pro Develop- powers below:
ment Board for DRAM model and Altera’s Cyclone Devel-
∗
opment Board for NAND Flash model. PREAD = (3.78 − 3.69) W = 90mW

373
 Table 4. Measured Power data of NAND Flash
Operations Current(A) Power(W)
Only Bootloop 0.37 3.33
No Memroy Access 0.41 3.69
Read 0.42 3.78
Erase 0.44 3.96
Program 0.44 3.96

a The Working Voltage of Development Board is 9 V

Figure 4. Comparison of DRAM Power

for providing the Development Board and Mr. Wang Heng-
cai for providing measure devices.
∗
PW RIT E = (3.96 − 3.69) W = 270mW
∗
PERASE = (3.96 − 3.69) W = 270mW
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ACKNOWLEDGEMENTS

This article was supported by 863 Research and Devel- Figure 5. Model Screenshot
opment Program. And we would like to thank Xilinx Inc.

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