a 16-Bit, 1 MSPS CMOS ADC

AD7671*
FEATURES FUNCTIONAL BLOCK DIAGRAM
Throughput
AVDD AGND REF REFGND DVDD DGND
1 MSPS (Warp Mode)
800 kSPS (Normal Mode) 4R
INL:
2.5 LSB Max (
0.0038% of Full Scale) IND(4R)
4R
AD7671 OVDD
16-Bit Resolution with No Missing Codes INC(4R)
OGND
2R SERIAL
S/(N+D): 90 dB Typ @ 250 kHz INB(2R)
PORT
R
THD: –100 dB Typ @ 250 kHz INA(R)
SWITCHED
SER/PAR
Analog Input Voltage Ranges INGND
CAP DAC
BUSY
Bipolar:
10 V,
5 V,
2.5 V PARALLEL 16
INTERFACE D[15:0]
Unipolar: 0 V to 10 V, 0 V to 5 V, 0 V to 2.5 V
PD CLOCK CS
Both AC and DC Specifications
No Pipeline Delay RESET RD
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
Parallel (8/16 Bits) and Serial 5 V/3 V Interface OB/2C

SPI®/QSPI™/MICROWIRE™/DSP Compatible BYTESWAP

Single 5 V Supply Operation
WARP IMPULSE CNVST
Power Dissipation
112 mW Typical
15 W @ 100 SPS PulSAR Selection
Power-Down Mode: 7 W Max
Type/kSPS 100–250 500–570 800–1000
Package: 48-Lead Quad Flatpack (LQFP)
Package: 48-Lead Chip Scale (LFCSP) Pseudo AD7660 AD7650
Pin-to-Pin Compatible Upgrade of the AD7665/AD7664 Differential AD7664
APPLICATIONS True Bipolar AD7663 AD7665 AD7671
Data Acquisition True Differential AD7675 AD7676 AD7677
Communication
Instrumentation 18-Bit AD7678 AD7679 AD7674
Spectrum Analysis Simultaneous/ AD7654 AD7655
Medical Instruments Multichannel
Process Control

GENERAL DESCRIPTION It is fabricated using Analog Devices’ high performance, 0.6 micron
The AD7671 is a 16-bit, 1 MSPS, charge redistribution SAR, CMOS process and is available in a 48-lead LQFP and a tiny
analog-to-digital converter that operates from a single 5 V power 48-lead LFCSP, with operation specified from –40∞C to +85∞C.
supply. It contains a high speed 16-bit sampling ADC, a resistor
input scaler that allows various input ranges, an internal PRODUCT HIGHLIGHTS
conversion clock, error correction circuits, and both serial 1. Fast Throughput
and parallel system interface ports. The AD7671 is a very high speed (1 MSPS in Warp Mode
and 800 kSPS in Normal Mode), charge redistribution, 16-bit
The AD7671 is hardware factory-calibrated and is comprehen- SAR ADC.
sively tested to ensure such ac parameters as signal-to-noise ratio 2. Single-Supply Operation
(SNR) and total harmonic distortion (THD), in addition to the The AD7671 operates from a single 5 V supply, dissipates
more traditional dc parameters of gain, offset, and linearity. only 112 mW typical, even lower when a reduced throughput
It features a very high sampling rate mode (Warp), a fast mode is used with the reduced power mode (Impulse) and a power-
(Normal) for asynchronous conversion rate applications, and, for down mode.
low power applications, a reduced power mode (Impulse) where 3. Superior INL
the power is scaled with the throughput. The AD7671 has a maximum integral nonlinearity of 2.5 LSB
with no missing 16-bit code.
*Patent pending 4. Serial or Parallel Interface
Versatile parallel (8 bits or 16 bits) or 2-wire serial interface
REV. B arrangement compatible with both 3 V or 5 V logic.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
under any patent or patent rights of Analog Devices. Trademarks and Tel: 781/329-4700 [Link]
registered trademarks are the property of their respective companies. Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
AD7671–SPECIFICATIONS (–40C to +85C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Parameter Conditions Min Typ Max Unit
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range VIND – VINGND ± 4 REF, 0 V to 4 REF, ± 2 REF (See Table I)
Common-Mode Input Voltage VINGND –0.1 +0.5 V
Analog Input CMRR fIN = 100 kHz 74 dB
Input Impedance See Table I
THROUGHPUT SPEED
Complete Cycle In Warp Mode 1 ms
Throughput Rate In Warp Mode 1 1000 kSPS
Time between Conversions In Warp Mode 1 ms
Complete Cycle In Normal Mode 1.25 ms
Throughput Rate In Normal Mode 0 800 kSPS
Complete Cycle In Impulse Mode 1.5 ms
Throughput Rate In Impulse Mode 0 666 kSPS
DC ACCURACY
Integral Linearity Error –2.5 +2.5 LSB1
No Missing Codes 16 Bits
Transition Noise 0.7 LSB
Bipolar Zero Error2, TMIN to TMAX ± 5 V Range, Normal or –45 +45 LSB
Impulse Modes
Other Range or Mode –0.1 +0.1 % of FSR
Bipolar Full-Scale Error2, TMIN to TMAX –0.38 +0.38 % of FSR
Unipolar Zero Error2, TMIN to TMAX –0.18 +0.18 % of FSR
Unipolar Full-Scale Error 2, TMIN to TMAX –0.76 +0.76 % of FSR
Power Supply Sensitivity AVDD = 5 V ± 5% ± 9.5 LSB
AC ACCURACY
Signal-to-Noise fIN = 20 kHz 89 90 dB3
fIN = 250 kHz 90 dB
Spurious-Free Dynamic Range fIN = 250 kHz 100 dB
Total Harmonic Distortion fIN = 20 kHz –100 –96 dB
fIN = 250 kHz –100 dB
Signal-to-(Noise+Distortion) fIN = 20 kHz 88.5 90 dB
fIN = 250 kHz, –60 dB Input 30 dB
–3 dB Input Bandwidth 9.6 MHz
SAMPLING DYNAMICS
Aperture Delay 2 ns
Aperture Jitter 5 ps rms
Transient Response Full-Scale Step 250 ns
REFERENCE
External Reference Voltage Range 2.3 2.5 AVDD – 1.85 V
External Reference Current Drain 1 MSPS Throughput 200 mA
DIGITAL INPUTS
Logic Levels
VIL –0.3 +0.8 V
VIH +2.0 DVDD + 0.3 V
IIL –1 +1 mA
IIH –1 +1 mA
DIGITAL OUTPUTS
Data Format Parallel or Serial 16-Bit
Pipeline Delay Conversion Results Available Immediately
after Completed Conversion
VOL ISINK = 1.6 mA 0.4 V
VOH ISOURCE = –570 mA OVDD – 0.6 V

–2– REV. B
 AD7671
Parameter Conditions Min Typ Max Unit
POWER SUPPLIES
Specified Performance
AVDD 4.75 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 5.254 V
Operating Current5 1 MSPS Throughput
AVDD 15 mA
DVDD6 7.2 mA
OVDD6 37 mA
Power Dissipation6, 7 666 kSPS Throughput8 84 95 mW
100 SPS Throughput8 15 mW
1 MSPS Throughput5 112 125 mW
In Power-Down Mode 9 7 mW
TEMPERATURE RANGE 10
Specified Performance TMIN to TMAX –40 +85 ∞C
NOTES
1
LSB means least significant bit. With the ± 5 V input range, one LSB is 152.588 mV.
2
See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
3
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
4
The max should be the minimum of 5.25 V and DVDD + 0.3 V.
5
In Warp Mode.
6
Tested in Parallel Reading Mode.
7
Tested with the 0 V to 5 V range and V IN – VINGND = 0 V. See Power Dissipation section.
8
In Impulse Mode.
9
With OVDD below DVDD + 0.3 V and all digital inputs forced to DVDD or DGND, respectively.
10
Contact factory for extended temperature range.
Specifications subject to change without notice.

Table I. Analog Input Configuration

Input Voltage Input

Range IND(4R) INC(4R) INB(2R) INA(R) Impedance1
± 4 REF2 VIN INGND INGND REF 1.63 kW
± 2 REF VIN VIN INGND REF 948 W
± REF VIN VIN VIN REF 711 W
0 V to 4 REF VIN VIN INGND INGND 948 W
0 V to 2 REF VIN VIN VIN INGND 711 W
0 V to REF VIN VIN VIN VIN Note 3
NOTES
1
Typical analog input impedance.
2
With REF = 3 V, in this range, the input should be limited to –11 V to +12 V.
3
For this range the input is high impedance.

TIMING SPECIFICATIONS (–40C to +85C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Parameter Symbol Min Typ Max Unit
Refer to Figures 11 and 12
Convert Pulsewidth t1 5 ns
Time between Conversions t2 1/1.25/1.5 Note 1 ms
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to BUSY HIGH Delay t3 30 ns
BUSY HIGH All Modes Except in Master Serial Read after t4 0.75/1/1.25 ms
Convert Mode (Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay t5 2 ns
End of Conversion to BUSY LOW Delay t6 10 ns
Conversion Time (Warp Mode/Normal Mode/Impulse Mode) t7 0.75/1/1.25 ms
Acquisition Time t8 250 ns
RESET Pulsewidth t9 10 ns

REV. B –3–
AD7671
TIMING SPECIFICATIONS (continued)
Parameter Symbol Min Typ Max Unit
Refer to Figures 13, 14, 15, and 16 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay t10 0.75/1/1.25 ms
(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY LOW Delay t11 20 ns
Bus Access Request to DATA Valid t12 40 ns
Bus Relinquish Time t13 5 15 ns
2
Refer to Figures 17 and 18 (Master Serial Interface Modes)
CS LOW to SYNC Valid Delay t14 10 ns
CS LOW to Internal SCLK Valid Delay t15 10 ns
CS LOW to SDOUT Delay t16 10 ns
CNVST LOW to SYNC Delay (Read during Convert) t17 25/275/525 ns
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay3 t18 4 ns
Internal SCLK Period3 t19 25 40 ns
Internal SCLK HIGH3 t20 15 ns
Internal SCLK LOW3 t21 9.5 ns
SDOUT Valid Setup Time3 t22 4.5 ns
SDOUT Valid Hold Time3 t23 2 ns
SCLK Last Edge to SYNC Delay3 t24 3
CS HIGH to SYNC HI-Z t25 10 ns
CS HIGH to Internal SCLK HI-Z t26 10 ns
CS HIGH to SDOUT HI-Z t27 10 ns
BUSY HIGH in Master Serial Read after Convert3 t28 See Table II ms
CNVST LOW to SYNC Asserted Delay t29 0.75/1/1.25 ms
(Warp Mode/Normal Mode/Impulse Mode)
Master Serial Read after Convert
SYNC Deasserted to BUSY LOW Delay t30 25 ns
Refer to Figures 19 and 21 (Slave Serial Interface Modes)
External SCLK Setup Time t31 5 ns
External SCLK Active Edge to SDOUT Delay t32 3 16 ns
SDIN Setup Time t33 5 ns
SDIN Hold Time t34 5 ns
External SCLK Period t35 25 ns
External SCLK HIGH t36 10 ns
External SCLK LOW t37 10 ns
NOTES
1
In Warp Mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C L of 10 pF; otherwise, the load is 60 pF maximum.
3
In Serial Master Read during Convert Mode. See Table II for Master Read after Convert Mode.
Specifications subject to change without notice.

Table II. Serial Clock Timings in Master Read after Convert

DIVSCLK[1] 0 0 1 1
DIVSCLK[0] 0 1 0 1 Unit
SYNC to SCLK First Edge Delay Minimum t18 4 20 20 20 ns
Internal SCLK Period Minimum t19 25 50 100 200 ns
Internal SCLK Period Maximum t19 40 70 140 280 ns
Internal SCLK HIGH Minimum t20 15 25 50 100 ns
Internal SCLK LOW Minimum t21 9 24 49 99 ns
SDOUT Valid Setup Time Minimum t22 4.5 22 22 22 ns
SDOUT Valid Hold Time Minimum t23 2 4 30 89 ns
SCLK Last Edge to SYNC Delay Minimum t24 3 60 140 300 ns
BUSY HIGH Width Maximum (Warp) t28 1.5 2 3 5.25 ms
BUSY HIGH Width Maximum (Normal) t28 1.75 2.25 3.25 5.5 ms
BUSY HIGH Width Maximum (Impulse) t28 2 2.5 3.5 5.75 ms
Specifications subject to change without notice.

–4– REV. B
 AD7671
ABSOLUTE MAXIMUM RATINGS 1 PIN CONFIGURATION
Analog Inputs ST-48 and CP-48
IND2, INC2, INB2 . . . . . . . . . . . . . . . . . . . . –11 V to +30 V
INA, REF, INGND, REFGND, AGND

REFGND
IND(4R)
INC(4R)
INB(2R)
. . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to AVDD + 0.3 V

INGND
INA(R)

REF
Ground Voltage Differences

NC
NC
NC
NC
NC
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . . ± 0.3 V 48 47 46 45 44 43 42 41 40 39 38 37

Supply Voltages AGND 1 36 AGND

PIN 1
AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . . –0.3 V to +7 V AVDD 2 IDENTIFIER 35 CNVST
AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . . ± 7 V NC 3 34 PD
BYTESWAP 4
DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V 33 RESET
OB/2C 5 32 CS
Digital Inputs . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V WARP 6 AD7671
31 RD
Internal Power Dissipation3 . . . . . . . . . . . . . . . . . . . . 700 mW IMPULSE 7
TOP VIEW
30 DGND
(Not to Scale)
Internal Power Dissipation4 . . . . . . . . . . . . . . . . . . . . . . 2.5 W SER/PAR 8 29 BUSY
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150∞C D0 9 28 D15
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C D1 10 27 D14
D2/DIVSCLK[0] 11 26 D13
Lead Temperature Range D3/DIVSCLK[1] 12 25 D12
(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300∞C
13 14 15 16 17 18 19 20 21 22 23 24
NOTES NC = NO CONNECT

D4/EXT/INT
D5/INVSYNC
D6/INVSCLK
D7/RDC/SDIN
OGND
OVDD
DVDD
DGND
D8/SDOUT
D9/SCLK
D10/SYNC
D11/RDERROR
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
2
See Analog Inputs section.
3
Specification is for device in free air: 48-Lead LQFP: qJA = 91∞C/W, qJC = 30∞C/W.
4
Specification is for device in free air: 48-Lead LFCSP: qJA = 26∞C/W.

1.6mA IOL

TO OUTPUT 1.4V
PIN CL
60pF*
2V
500A IOH 0.8V
tDELAY tDELAY
*INSERIAL INTERFACE MODES, THE SYNC, SCLK, AND
2V 2V
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. 0.8V 0.8V

Figure 1. Load Circuit for Digital Interface Timing, Figure 2. Voltage Reference Levels for Timing
SDOUT, SYNC, SCLK Outputs, CL = 10 pF

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD7671AST –40∞C to +85∞C Quad Flatpack (LQFP) ST-48
AD7671ASTRL –40∞C to +85∞C Quad Flatpack (LQFP) ST-48
AD7671ACP –40∞C to +85∞C Chip Scale (LFCSP) CP-48
AD7671ACPRL –40∞C to +85∞C Chip Scale (LFCSP) CP-48
EVAL-AD7671CB1 Evaluation Board
EVAL-CONTROL BRD22 Controller Board
NOTES
1
This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.
2
This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7671 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. B –5–
AD7671
PIN FUNCTION DESCRIPTION

Pin
No. Mnemonic Type Description
1 AGND P Analog Power Ground Pin.
2 AVDD P Input Analog Power Pin. Nominally 5 V.
3, 44–48 NC No Connect.
4 BYTESWAP Parallel Mode Selection (8-/16-Bit). When LOW, the LSB is output on D[7:0] and the MSB is
output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].
5 OB/2C DI Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight
binary; when LOW, the MSB is inverted, resulting in a twos complement output from its internal
shift register.
6 WARP DI Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the maximum
throughput is achievable and a minimum conversion rate must be applied in order to guarantee
full specified accuracy. When LOW, full accuracy is maintained independent of the minimum
conversion rate.
7 IMPULSE DI Mode Selection. When HIGH and WARP LOW, this input selects a reduced Power Mode.
In this mode, the power dissipation is approximately proportional to the sampling rate.
8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH, the Serial
Interface Mode is selected and some bits of the data bus are used as a Serial Port.
9, 10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are
in high impedance.
11, 12 D[2:3] or DI/O When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data
Output Bus.
DIVSCLK[0:1] When SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the Serial Master
Read after Convert Mode. These inputs, part of the Serial Port, are used to slow down, if desired,
the internal serial clock that clocks the data output. In the other serial modes, these pins are high
impedance outputs.
13 D[4] DI/O When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus.
or EXT/INT When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital select input for
choosing the internal or an external data clock, called Master and Slave Modes, respectively. With
EXT/INT tied LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic
HIGH, output data is synchronized to an external clock signal connected to the SCLK input and
the external clock is gated by CS.
14 D[5] DI/O When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus.
or INVSYNC When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the active state of
the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
15 D[6] DI/O When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus.
or INVSCLK When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the SCLK signal. It is
active in both Master and Slave Mode.
16 D[7] DI/O When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus.
or RDC/SDIN When SER/PAR is HIGH, this input, part of the Serial Port, is used as either an external data input
or a read mode selection input, depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion
results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output
on DATA with a delay of 16 SCLK periods after the initiation of the read sequence.
When EXT/INT is LOW, RDC/SDIN is used to select the Read Mode. When RDC/SDIN is HIGH,
the previous data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can
be output on SDOUT only when the conversion is complete.
17 OGND P Input/Output Interface Digital Power Ground.
18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host
interface (5 V or 3 V).
19 DVDD P Digital Power. Nominally at 5 V.
20 DGND P Digital Power Ground.

–6– REV. B
 AD7671
PIN FUNCTION DESCRIPTION (continued)

Pin
No. Mnemonic Type Description
21 D[8] DO When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.
or SDOUT When SER/PAR is HIGH, this output, part of the Serial Port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7671 provides
the conversion result, MSB first, from its internal shift register. The data format is determined
by the logic level of OB/2C. In Serial Mode, when EXT/INT is LOW, SDOUT is valid on both
edges of SCLK.
In Serial Mode, when EXT/INT is HIGH:
If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the next falling edge.
If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising edge.
22 D[9] DI/O When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus.
or SCLK When SER/PAR is HIGH, this pin, part of the Serial Port, is used as a serial data clock input or
output, dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT
is updated depends upon the logic state of the INVSCLK pin.
23 D[10] DO When SER/PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus.
or SYNC When SER/PAR is HIGH, this output, part of the Serial Port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence
is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while SDOUT
output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW
and remains LOW while SDOUT output is valid.
24 D[11] DO When SER/PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus.
or RDERROR When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the Serial Port, is used as an
incomplete read error flag. In Slave Mode, when a data read is started and not complete when the
following conversion is complete, the current data is lost and RDERROR is pulsed HIGH.
25–28 D[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in
high impedance.
29 BUSY DO Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the conversion
is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could
be used as a data-ready clock signal.
30 DGND P Must Be Tied to Digital Ground.
31 RD DI Read Data. When CS and RD are both LOW, the Interface Parallel or Serial Output Bus is enabled.
32 CS DI Chip Select. When CS and RD are both LOW, the Interface Parallel or Serial Output Bus is enabled.
CS is also used to gate the external serial clock.
33 RESET DI Reset Input. When set to a logic HIGH, reset the AD7671. Current conversion, if any, is aborted.
If not used, this pin could be tied to DGND.
34 PD DI Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are
inhibited after the current one is completed.
35 CNVST DI Start Conversion. A falling edge on CNVST puts the internal sample-and-hold into the hold state
and initiates a conversion. In Impulse Mode (IMPULSE HIGH and WARP LOW), if CNVST is
held LOW when the acquisition phase (t8) is complete, the internal sample-and-hold is put into the
hold state and a conversion is immediately started.
36 AGND P Must Be Tied to Analog Ground.
37 REF AI Reference Input Voltage.
38 REFGND AI Reference Input Analog Ground.
39 INGND P Analog Input Ground.
40, 41, INA, INB, AI Analog Inputs. Refer to Table I for input range configuration.
42, 43 INC, IND
NOTES
AI = Analog Input
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power

REV. B –7–
AD7671
DEFINITION OF SPECIFICATIONS Effective Number of Bits (ENOB)
Integral Nonlinearity Error (INL) A measurement of the resolution with a sine wave input. It is
Linearity error refers to the deviation of each individual code related to S/(N+D) by the following formula:
from a line drawn from “negative full scale” through “positive ENOB = (S/[N + D]dB – 1.76)/6.02)
full scale.” The point used as negative full scale occurs 1/2 LSB
before the first code transition. Positive full scale is defined as a and is expressed in bits.
level 1 1/2 LSB beyond the last code transition. The deviation is Total Harmonic Distortion (THD)
measured from the middle of each code to the true straight line. The rms sum of the first five harmonic components to the rms
Differential Nonlinearity Error (DNL) value of a full-scale input signal, expressed in decibels.
In an ideal ADC, code transitions are 1 LSB apart. Differential Signal-to-Noise Ratio (SNR)
nonlinearity is the maximum deviation from this ideal value. It is The ratio of the rms value of the actual input signal to the rms
often specified in terms of resolution for which no missing codes sum of all other spectral components below the Nyquist fre-
are guaranteed. quency, excluding harmonics and dc. The value for SNR is
Full-Scale Error expressed in decibels.
The last transition (from 011 . . . 10 to 011 . . . 11 in twos Signal-to-(Noise + Distortion) Ratio (S/[N+D])
complement coding) should occur for an analog voltage 1 1/2 LSB The ratio of the rms value of the actual input signal to the rms
below the nominal full scale (2.499886 V for the ± 2.5 V range). sum of all other spectral components below the Nyquist fre-
The full-scale error is the deviation of the actual level of the last quency, including harmonics but excluding dc. The value for
transition from the ideal level. S/(N+D) is expressed in decibels.
Bipolar Zero Error Aperture Delay
The difference between the ideal midscale input voltage (0 V) and A measure of the acquisition performance measured from the
the actual voltage producing the midscale output code. falling edge of the CNVST input to when the input signal is
Unipolar Zero Error held for a conversion.
In Unipolar Mode, the first transition should occur at a level Transient Response
1/2 LSB above analog ground. The unipolar zero error is the The time required for the AD7671 to achieve its rated accuracy
deviation of the actual transition from that point. after a full-scale step function is applied to its input.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.

–8– REV. B
 Typical Performance Characteristics–AD7671
2.5 60

2.0
50
1.5

1.0

NUMBER OF UNITS
40
0.5
INL – LSB

0 30

–0.5
20
–1.0

–1.5
10
–2.0

–2.5 0
0 16384 32768 49152 65536 –3.0 –2.7 –2.4 –2.1 –1.8 –1.5 –1.2 –0.9 –0.6 –0.3
CODE NEGATIVE INL – LSB

TPC 1. Integral Nonlinearity vs. Code TPC 4. Typical Negative INL Distribution (314 Units)

1.75 8000

1.50 7029 7039

7000
1.25
6000
1.00

0.75 5000
DNL – LSB

0.50 COUNTS
4000
0.25

0 3000

–0.25 2000
–0.50 1297
986
1000
–0.75
0 0 17 25 0 0
–1.00 0
0 16384 32768 49152 65536 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8005
CODE CODE IN HEXA

TPC 2. Differential Nonlinearity vs. Code TPC 5. Histogram of 16,384 Conversions of a DC Input at
the Code Transition

60 10000
9503
9000
50
8000

7000
NUMBER OF UNITS

40
6000
COUNTS

30 5000

4000
3296 3344
20
3000

2000
10
1000
0 0 2 132 106 1 0 0
0 0
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006
POSITIVE INL – LSB CODE IN HEXA

TPC 3. Typical Positive INL Distribution (314 Units) TPC 6. Histogram of 16,384 Conversions of a DC Input at
the Code Center

REV. B –9–
AD7671
0 96 –98
FS = 1MSPS
–20 fIN = 45.5322kHz
SNR = 89.45dB
THD = –100.05dB
AMPLITUDE – dB of Full Scale

–40 SFDR = 100.49dB 93

SINAD = 89.1dB
–60 –100
THD

SNR – dB

THD – dB
–80
90
–100
SNR
–120 –102
87
–140

–160

–180 84 –104
0 100 200 300 400 500 –55 –35 –15 5 25 45 65 85 105 125
FREQUENCY – kHz TEMPERATURE – C

TPC 7. FFT Plot TPC 10. SNR, THD vs. Temperature

100 16.0 –60 110

–65 105
SFDR
95 15.5
–70 100
SNR –75
THD, HARMONICS – dB
SNR AND S/[N+D] – dB

95
90 15.0
SINAD –80
ENOB – Bits

90

SFDR – dB
–85
85 14.5 85
–90
ENOB 80
–95 SECOND HARMONIC
80 14.0
THD 75
–100

–105 70
75 13.5
–110 THIRD HARMONIC 65

70 13.0 –115 60
1 10 100 1000 1 10 100 1000
FREQUENCY – kHz
FREQUENCY – kHz

TPC 8. SNR, S/(N + D), and ENOB vs. Frequency TPC 11. THD, Harmonics, and SFDR vs. Frequency

92 –60

–70
SNR (REFERRED TO FULL SCALE) – dB

–80
THD, HARMONICS – dB

90 –90

–100
SECOND HARMONIC
–110
THD

88 –120

–130
THIRD HARMONIC
–140

86 –150
–80 –70 –60 –50 –40 –30 –20 –10 0 –60 –50 –40 –30 –20 –10 0
INPUT LEVEL – dB INPUT LEVEL – dB

TPC 9. SNR vs. Input Level TPC 12. THD, Harmonics vs. Input Level

–10– REV. B
 AD7671
50 1000

POWER-DOWN OPERATING CURRENTS – nA

900

40 800

700
DVDD
t12 DELAY – ns

30 600

500

20 400

300

10 200 OVDD

100 AVDD

0 0
0 50 100 150 200 –55 –35 –15 5 25 45 65 85 105
CL – pF TEMPERATURE – C

TPC 13. Typical Delay vs. Load Capacitance CL TPC 15. Power-Down Operating Currents vs. Temperature

100000 10
AVDD, WARP/NORMAL
8
10000
DVDD, WARP/NORMAL 6
OPERATING CURRENTS – A

1000
4
–FS
100 OFFSET
2
LSB
10 AVDD, IMPULSE 0 +FS

–2
0
DVDD, IMPULSE
–4
0.1
–6
OVDD, ALL MODES
0.01
–8

0.001 –10
1 10 100 1000 10000 100000 1000000 –55 –35 –15 5 25 45 65 85 105 125
SAMPLING RATE – SPS TEMPERATURE – C

TPC 14. Operating Currents vs. Sample Rate TPC 16. +FS, Offset, and –FS vs. Temperature

CIRCUIT INFORMATION It is specified to operate with both bipolar and unipolar input
The AD7671 is a fast, low power, single-supply, precise 16-bit ranges by changing the connection of its input resistive scaler.
analog-to-digital converter (ADC). The AD7671 features different The AD7671 can be operated from a single 5 V supply and be
modes to optimize performances according to the applications. interfaced to either 5 V or 3 V digital logic. It is housed in a
In Warp Mode, the AD7671 is capable of converting 1,000,000 48-lead LQFP package or a 48-lead LFCSP package that com-
samples per second (1 MSPS). bines space savings and flexible configurations as either serial
The AD7671 provides the user with an on-chip track-and-hold, or parallel interface. The AD7671 is a pin-to-pin compatible
successive approximation ADC that does not exhibit any pipeline upgrade of the AD7665 and AD7664.
or latency, making it ideal for multiple multiplexed channel
applications.

REV. B –11–
AD7671
4R
IND
REF
4R REFGND
INC SWITCHES
CONTROL
2R MSB LSB SWA
INB
32,768C 16,384C 4C 2C C C
R BUSY
INA
CONTROL
COMP LOGIC
INGND 65,536C OUTPUT
SWB CODE

CNVST

Figure 3. ADC Simplified Schematic

CONVERTER OPERATION Modes of Operation

The AD7671 is a successive approximation analog-to-digital The AD7671 features three modes of operation, Warp, Normal,
converter based on a charge redistribution DAC. Figure 3 shows and Impulse. Each of these modes is more suitable for specific
the simplified schematic of the ADC. The input analog signal is applications.
first scaled down and level shifted by the internal input resistive The Warp Mode allows the fastest conversion rate up to 1 MSPS.
scaler, which allows both unipolar ranges (0 V to 2.5 V, 0 V to 5 V, However, in this mode, and this mode only, the full specified accu-
and 0 V to 10 V) and bipolar ranges (± 2.5 V, ± 5 V, and ± 10 V). racy is guaranteed only when the time between conversion does
The output voltage range of the resistive scaler is always 0 V to not exceed 1 ms. If the time between two consecutive conversions
2.5 V. The capacitive DAC consists of an array of 16 binary is longer than 1 ms, for instance, after power-up, the first conver-
weighted capacitors and an additional “LSB” capacitor. The sion result should be ignored. This mode makes the AD7671 ideal
comparator’s negative input is connected to a “dummy” capacitor for applications where both high accuracy and fast sample rate
of the same value as the capacitive DAC array. are required.
During the acquisition phase, the common terminal of the array The Normal Mode is the fastest mode (800 kSPS) without any limi-
tied to the comparator’s positive input is connected to AGND via tation about the time between conversions. This mode makes the
SWA. All independent switches are connected to the output of the AD7671 ideal for asynchronous applications such as data acquisi-
resistive scaler. Thus, the capacitor array is used as a sampling tion systems, where both high accuracy and fast sample rate are
capacitor and acquires the analog signal. Similarly, the dummy required.
capacitor acquires the analog signal on INGND input.
The Impulse Mode, the lowest power dissipation mode, allows
When the acquisition phase is complete and the CNVST input goes power saving between conversions. The maximum throughput in
or is LOW, a conversion phase is initiated. When the conversion this mode is 666 kSPS. When operating at 100 SPS, for example,
phase begins, SWA and SWB are opened first. The capacitor array it typically consumes only 15 mW. This feature makes the AD7671
and the dummy capacitor are then disconnected from the inputs and ideal for battery-powered applications.
connected to the REFGND input. Therefore, the differential
voltage between the output of the resistive scaler and INGND Transfer Functions
captured at the end of the acquisition phase is applied to the Using the OB/2C digital input, the AD7671 offers two output
comparator inputs, causing the comparator to become unbalanced. codings: straight binary and twos complement. The ideal transfer
characteristic for the AD7671 is shown in Figure 4 and Table III.
By switching each element of the capacitor array between REFGND
or REF, the comparator input varies by binary weighted voltage
steps (VREF/2, VREF/4 . . . VREF/65,536). The control logic toggles
these switches, starting with the MSB first, in order to bring the
111...111
comparator back into a balanced condition. After the completion
ADC CODE – Straight Binary

111...110
of this process, the control logic generates the ADC output code 111...101
and brings BUSY output LOW.

000...010
000...001
000...000
–FS –FS + 1 LSB +FS – 1 LSB
–FS + 0.5 LSB +FS – 1.5 LSB
ANALOG INPUT

Figure 4. ADC Ideal Transfer Function

–12– REV. B
 AD7671
Table III. Output Codes and Ideal Input Voltages

Digital Output
Code (Hexa)
Straight Twos
Description Analog Input Binary Complement
Full-Scale Range 1
± 10 V ±5 V ± 2.5 V 0 V to 10 V 0 V to 5 V 0 V to 2.5 V
Least Significant Bit 305.2 mV 152.6 mV 76.3 mV 152.6 mV 76.3 mV 38.15 mV
FSR – 1 LSB 9.999695 V 4.999847 V 2.499924 V 9.999847 V 4.999924 V 2.499962 V FFFF2 7FFF2
Midscale + 1 LSB 305.2 mV 152.6 mV 76.3 mV 5.000153 V 2.570076 V 1.257038 V 8001 0001
Midscale 0V 0V 0V 5V 2.5 V 1.25 V 8000 0000
Midscale – 1 LSB –305.2 mV –152.6 mV –76.3 mV 4.999847 V 2.499924 V 1.249962 V 7FFF FFFF
–FSR + 1 LSB –9.999695 V –4.999847 V –2.499924 V 152.6 mV 76.3 mV 38.15 mV 0001 8001
–FSR –10 V –5 V –2.5 V 0V 0V 0V 00003 80003
NOTES
1
Values with REF = 2.5 V. With REF = 3 V, all values will scale linearly.
2
This is also the code for an overrange analog input.
3
This is also the code for an underrange analog input.

TYPICAL CONNECTION DIAGRAM

Figure 5 shows a typical connection diagram for the AD7671. Different circuitry shown on this diagram is optional and is discussed below.

DVDD
ANALOG 20 DIGITAL SUPPLY
SUPPLY (3.3V OR 5V)
(5V) + NOTE 7 + +
10F 100nF 10F 100nF 100nF 10F

ADR421
AVDD AGND DGND DVDD OVDD OGND
SERIAL
REF PORT
2.5V REF SCLK
NOTE 1 1M +
50k CREF
SDOUT
100nF NOTE 2
REFGND
NOTE 3 BUSY

50
C/P/DSP
CNVST D

U2 INA
+
AD7671 NOTE 8
+ 10F 100nF
AD8031
OB/2C
NOTE 4
SER/PAR DVDD
50
WARP

15 CLOCK
ANALOG NOTE 5 U1 IND IMPULSE
INPUT + 2.7nF CS
(
10V)
AD8021 NOTE 6 RD
CC
BYTESWAP
INGND
RESET
INB
PD
INC

NOTES
1. SEE VOLTAGE REFERENCE INPUT SECTION.
2. WITH THE RECOMMENDED VOLTAGE REFERENCES, CREF IS 47F. SEE VOLTAGE REFERENCE INPUT SECTION.
3. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION.
4. FOR BIPOLAR RANGE ONLY. SEE SCALER REFERENCE INPUT SECTION.
5. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.
6. WITH 0V TO 2.5V RANGE ONLY. SEE ANALOG INPUTS SECTION.
7. OPTION. SEE POWER SUPPLY SECTION.
8. OPTIONAL LOW JITTER CNVST. SEE CONVERSION CONTROL SECTION.

Figure 5. Typical Connection Diagram (± 10 V Range Shown)

REV. B –13–
AD7671
Analog Inputs 75
The AD7671 is specified to operate with six full-scale analog input
70
ranges. Connections required for each of the four analog inputs,
IND, INC, INB, and INA, and the resulting full-scale ranges 65
are shown in Table I. The typical input impedance for each
analog input range is also shown. 60

CMRR – dB
Figure 6 shows a simplified analog input section of the AD7671. 55

The four resistors connected to the four analog inputs form a 50

resistive scaler that scales down and shifts the analog input range
to a common input range of 0 V to 2.5 V at the input of the 45

switched capacitive ADC. 40

AVDD 35
1 10 100 1000 10000
FREQUENCY – kHz
4R
IND
4R
Figure 7. Analog Input CMRR vs. Frequency
INC
2R R1
Except when using the 0 V to 2.5 V analog input voltage range,
INB the AD7671 has to be driven by a very low impedance source to
R CS
INA avoid gain errors. That can be done by using a driver amplifier
whose choice is eased by the primarily resistive analog input
R = 1.28k circuitry of the AD7671.
When using the 0 V to 2.5 V analog input voltage range, the input
AGND impedance of the AD7671 is very high so the AD7671 can be
driven directly by a low impedance source without gain error.
Figure 6. Simplified Analog Input That allows, as shown in Figure 5, putting an external one-pole
By connecting the four inputs INA, INB, INC, and IND to the RC filter between the output of the amplifier output and the
input signal itself, the ground, or a 2.5 V reference, other analog ADC analog inputs to even further improve the noise filtering
input ranges can be obtained. done by the AD7671 analog input circuit. However, the source
The diodes shown in Figure 6 provide ESD protection for the impedance has to be kept low because it affects the ac perfor-
four analog inputs. The inputs INB, INC, and IND have a high mances, especially the total harmonic distortion (THD). The
voltage protection (–11 V to +30 V) to allow a wide input voltage maximum source impedance depends on the amount of total THD
range. Care must be taken to ensure that the analog input signal that can be tolerated. The THD degradation is a function of the
never exceeds the absolute ratings on these inputs, including source impedance and the maximum input frequency as shown
INA (0 V to 5 V). This will cause these diodes to become forward- in Figure 8.
biased and start conducting current. These diodes can handle –70
a forward-biased current of 120 mA maximum. For instance,
when using the 0 V to 2.5 V input range, these conditions could
eventually occur on the input INA when the input buffer’s (U1)
–80
supplies are different from AVDD. In such cases, an input buffer R = 100
with a short-circuit current limitation can be used to protect the part.
THD – dB

R = 50
This analog input structure allows the sampling of the differen-
–90
tial signal between the output of the resistive scaler and INGND.
Unlike other converters, the INGND input is sampled at the
same time as the inputs. By using this differential input, small R = 11
signals common to both inputs are rejected as shown in Figure 7, –100

which represents the typical CMRR over frequency. For instance,

by using INGND to sense a remote signal ground, the difference of
ground potentials between the sensor and the local ADC ground –110
0 100 1000
is eliminated. During the acquisition phase for ac signals, the FREQUENCY – kHz
AD7671 behaves like a one-pole RC filter consisting of the
Figure 8. THD vs. Analog Input Frequency and Input
equivalent resistance of the resistive scaler R/2 in series with R1
Resistance (0 V to 2.5 V Only)
and CS. The resistor R1 is typically 100 W and is a lumped
component made up of some serial resistors and the on resis-
tance of the switches.
The capacitor CS is typically 60 pF and is mainly the ADC
sampling capacitor. This one-pole filter with a typical –3 dB
cutoff frequency of 9.6 MHz reduces undesirable aliasing effects
and limits the noise coming from the inputs.

–14– REV. B
 AD7671
Driver Amplifier Choice Voltage Reference Input
Although the AD7671 is easy to drive, the driver amplifier needs The AD7671 uses an external 2.5 V voltage reference.
to meet at least the following requirements: The voltage reference input REF of the AD7671 has a dynamic
∑ The driver amplifier and the AD7671 analog input circuit input impedance; it should therefore be driven by a low impedance
must be able, together, to settle for a full-scale step the capaci- source with an efficient decoupling between REF and REFGND
tor array at a 16-bit level (0.0015%). In the amplifier’s data inputs. This decoupling depends on the choice of the voltage
sheet, the settling at 0.1% to 0.01% is more commonly speci- reference but usually consists of a 1 mF ceramic capacitor and a
fied. It could significantly differ from the settling time at low ESR tantalum capacitor connected to the REF and REFGND
16-bit level and it should therefore be verified prior to the inputs with minimum parasitic inductance. 47 mF is an appropriate
driver selection. The tiny op amp AD8021, which combines value for the tantalum capacitor when used with one of the
ultralow noise and a high gain bandwidth, meets this settling recommended reference voltages:
time requirement even when used with a high gain up to 13. ∑ The low noise, low temperature drift ADR421 and AD780
∑ The noise generated by the driver amplifier needs to be kept voltage references
as low as possible in order to preserve the SNR and transi- ∑ The low power ADR291 voltage reference
tion noise performance of the AD7671. The noise coming
from the driver is first scaled down by the resistive scaler ∑ The low cost AD1582 voltage reference
according to the analog input voltage range used and is then For applications using multiple AD7671s, it is more effective to
filtered by the AD7671 analog input circuit one-pole, low- buffer the reference voltage with a low noise, very stable op amp
pass filter made by (R/2 + R1) and CS. The SNR degradation like the AD8031.
due to the amplifier is
Care should also be taken with the reference temperature coeffi-
cient of the voltage reference that directly affects the full-scale
Ê ˆ accuracy if this parameter matters. For instance, a ± 15 ppm/∞C
Á ˜ temperature coefficient of the reference changes the full scale
Á 28 ˜ by ± 1 LSB/∞C.
SNRLOSS = 20 LOG Á ˜
2
Á p Ê 2.5 N eN ˆ ˜ Note that VREF , as mentioned in the Specifications table, could
Á + ˜
2 –3dB ÁË FSR ˜¯
784 f be increased to AVDD – 1.85 V. The benefit here is the increased
Ë ¯
SNR obtained as a result of this increase. Since the input range
is defined in terms of VREF, this would essentially increase the
where: ± REF range from ± 2.5 V to ± 3 V and so on with an AVDD
f–3 dB is the –3 dB input bandwidth in MHz of the AD7671 above 4.85 V. The theoretical improvement as a result of this
(9.6 MHz) or the cutoff frequency of the input filter if increase in reference is 1.58 dB (20 log [3/2.5]). Due to the
any used (0 V to 2.5 V range). theoretical quantization noise, however, the observed improve-
ment is approximately 1 dB. The AD780 can be selected with a
N is the noise factor of the amplifier (1 if in buffer
3 V reference voltage.
configuration).
Scaler Reference Input (Bipolar Input Ranges)
eN is the equivalent input noise voltage of the op amp When using the AD7671 with bipolar input ranges, the connec-
in nV/冪Hz. tion diagram in Figure 5 shows a reference buffer amplifier. This
FSR is the full-scale span (i.e., 5 V for ± 2.5 V range). buffer amplifier is required to isolate the REF pin from the signal
dependent current in the INx pin. A high speed op amp, such as the
For instance, when using the 0 V to 5 V range, a driver like
AD8031, can be used with a single 5 V power supply without
the AD8021, with an equivalent input noise of 2 nV/冪Hz and
degrading the performance of the AD7671. The buffer must have
configured as a buffer, thus with a noise gain of 1, the SNR
good settling characteristics and provide low total noise within
degrades by only 0.08 dB. the input bandwidth of the AD7671.
∑ The driver needs to have a THD performance suitable to that Power Supply
of the AD7671. TPC 11 gives the THD versus frequency The AD7671 uses three sets of power supply pins: an analog 5 V
that the driver should preferably exceed. supply AVDD, a digital 5 V core supply DVDD, and a digital
The AD8021 meets these requirements and is usually appropriate input/output interface supply OVDD. The OVDD supply allows
for almost all applications. The AD8021 needs an external com- direct interface with any logic working between 2.7 V and DVDD
pensation capacitor of 10 pF. This capacitor should have good + 0.3 V. To reduce the number of supplies needed, the digital core
linearity as an NPO ceramic or mica type. (DVDD) can be supplied through a simple RC filter from the
The AD8022 could also be used where a dual version is needed analog supply as shown in Figure 5. The AD7671 is independent
and a gain of 1 is used. of power supply sequencing, once OVDD does not exceed DVDD
by more than 0.3 V, and thus free from supply voltage induced
The AD829 is another alternative where high frequency (above latch-up. Additionally, it is very insensitive to power supply varia-
100 kHz) performance is not required. In a gain of 1, it requires tions over a wide frequency range as shown in Figure 9.
an 82 pF compensation capacitor.
The AD8610 is another option where low bias current is needed
in low frequency applications.

REV. B –15–
AD7671
75 CONVERSION CONTROL
Figure 11 shows the detailed timing diagrams of the conversion
70
process. The AD7671 is controlled by the signal CNVST, which
65 initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conversion
60
is complete. The CNVST signal operates independently of CS
PSRR – dB

55
and RD signals.

50 t2
t1
45
CNVST
40

35
1 10 100 1000 10000
BUSY
FREQUENCY – kHz t4
t3
Figure 9. PSRR vs. Frequency t6
t5

POWER DISSIPATION MODE ACQUIRE CONVERT ACQUIRE CONVERT

In Impulse Mode, the AD7671 automatically reduces its power t7 t8
consumption at the end of each conversion phase. During the
acquisition phase, the operating currents are very low, which allows a Figure 11. Basic Conversion Timing
significant power savings when the conversion rate is reduced,
as shown in Figure 10. This feature makes the AD7671 ideal for In Impulse Mode, conversions can be automatically initiated. If
very low power battery applications. CNVST is held LOW when BUSY is LOW, the AD7671 controls
the acquisition phase and then automatically initiates a new conver-
This does not take into account the power, if any, dissipated by sion. By keeping CNVST LOW, the AD7671 keeps the conversion
the input resistive scaler, which depends on the input voltage process running by itself. It should be noted that the analog input
range used and the analog input voltage even in Power-Down has to be settled when BUSY goes LOW. Also, at power-up,
Mode. There is no power dissipated when the 0 V to 2.5 V is used CNVST should be brought LOW once to initiate the conversion
or when both the analog input voltage is 0 V and a unipolar range, process. In this mode, the AD7671 could sometimes run slightly
0 V to 5 V or 0 V to 10 V, is used. faster than the guaranteed limits in the Impulse Mode of
It should be noted that the digital interface remains active even 666 kSPS. This feature does not exist in Warp or Normal Modes.
during the acquisition phase. To reduce the operating digital Although CNVST is a digital signal, it should be designed with
supply currents even further, the digital inputs need to be driven special care with fast, clean edges, and levels with minimum over-
close to the power rails (i.e., DVDD and DGND) and OVDD shoot and undershoot or ringing. It is a good thing to shield the
should not exceed DVDD by more than 0.3 V. CNVST trace with ground and also to add a low value serial
100000
resistor (i.e., 50 W) termination close to the output of the
WARP/NORMAL component that drives this line.
10000 For applications where the SNR is critical, the CNVST signal
should have a very low jitter. To achieve this, some use a dedicated
POWER DISSIPATION – W

1000
oscillator for CNVST generation, or at least to clock it with a
high frequency low jitter clock as shown in Figure 5.
100
t9
RESET
10

IMPULSE
1
BUSY

0.1
1 10 100 1000 10000 100000 1000000
SAMPLING RATE – SPS

DATA BUS
Figure 10. Power Dissipation vs. Sample Rate

t8

CNVST

Figure 12. RESET Timing

–16– REV. B
 AD7671
DIGITAL INTERFACE CS = 0
The AD7671 has a versatile digital interface; it can be interfaced t1
CNVST,
with the host system by using either a serial or parallel interface. RD
The serial interface is multiplexed on the parallel data bus. The
AD7671 digital interface also accommodates both 3 V or 5 V logic
by simply connecting the OVDD supply pin of the AD7671 to the BUSY t4
host system interface digital supply. Finally, by using the OB/2C
t3
input pin, straight binary and twos complement coding can be used.
The two signals CS and RD control the interface. When at least
DATA BUS PREVIOUS
one of these signals is HIGH, the interface outputs are in high CONVERSION
impedance. Usually, CS allows the selection of each AD7671 in t 12 t 13
multicircuit applications and is held LOW in a single AD7671
design. RD is generally used to enable the conversion result on Figure 15. Slave Parallel Data Timing for Reading (Read
the data bus. during Convert)
CS = RD = 0 The BYTESWAP pin allows a glueless interface to an 8-bit bus.
t1 As shown in Figure 16, the LSB is output on D[7:0] and the
MSB is output on D[15:8] when BYTESWAP is LOW. When
CNVST
BYTESWAP is HIGH, the LSB and MSB bytes are swapped and
t 10 the LSB is output on D[15:8] and the MSB is output on D[7:0].
By connecting BYTESWAP to an address line, the 16 data bits
BUSY
t4 can be read in two bytes on either D[15:8] or D[7:0].
t3
t 11

DATA BUS PREVIOUS CONVERSION DATA NEW DATA CS

Figure 13. Master Parallel Data Timing for Reading RD

(Continuous Read)
BYTE
PARALLEL INTERFACE
The AD7671 is configured to use the parallel interface when the
HI-Z HI-Z
SER/PAR is held LOW. The data can be read either after each PINS D[15:8] HIGH BYTE LOW BYTE
conversion, which is during the next acquisition phase, or during t12 t12 t13
the following conversion as shown, respectively, in Figures 14 and PINS D[7:0] HI-Z HI-Z
LOW BYTE HIGH BYTE
15. When the data is read during the conversion, however, it is
recommended that it be read-only during the first half of the con-
version phase. That avoids any potential feedthrough between Figure 16. 8-Bit Parallel Interface
voltage transients on the digital interface and the most critical
analog conversion circuitry. SERIAL INTERFACE
The AD7671 is configured to use the serial interface when the
SER/PAR is held HIGH. The AD7671 outputs 16 bits of data,
CS
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin. The output data
RD
is valid on both the rising and falling edge of the data clock.

SLAVE SERIAL INTERFACE

BUSY External Clock
The AD7671 is configured to accept an externally supplied
DATA BUS CURRENT serial data clock on the SCLK pin when the EXT/INT pin is
CONVERSION
held HIGH. In this mode, several methods can be used to read
t 12 t 13
the data. The external serial clock is gated by CS and the data
are output when both CS and RD are LOW. Thus, depending on
Figure 14. Slave Parallel Data Timing for Reading (Read
CS, the data can be read after each conversion or during the follow-
after Convert)
ing conversion. The external clock can be either a continuous or
discontinuous clock. A discontinuous clock can be either normally
HIGH or normally LOW when inactive. Figures 19 and 21
show the detailed timing diagrams of these methods.

REV. B –17–
AD7671
MASTER SERIAL INTERFACE In Read-during-Conversion Mode, the serial clock and data toggle
Internal Clock at appropriate instants, which minimizes potential feedthrough
The AD7671 is configured to generate and provide the serial data between digital activity and the critical conversion decisions.
clock SCLK when the EXT/INT pin is held LOW. It also gener- In Read-after-Conversion Mode, it should be noted that unlike
ates a SYNC signal to indicate to the host when the serial data is in other modes, the signal BUSY returns LOW after the 16 data
valid. The serial clock SCLK and the SYNC signal can be inverted bits are pulsed out and not at the end of the conversion phase,
if desired. Depending on RDC/SDIN input, the data can be read which results in a longer BUSY width.
after each conversion or during conversion. Figures 17 and 18
show the detailed timing diagrams of these two modes. While the AD7671 is performing a bit decision, it is important that
voltage transients not occur on digital input/output pins or degra-
Usually, because the AD7671 is used with a fast throughput, the dation of the conversion result could occur. This is particularly
mode master, read during conversion, is the most recommended important during the second half of the conversion phase because
Serial Mode when it can be used.

EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0

CS, RD

t3

CNVST

BUSY t 28
t 30
t 29
t 25
SYNC

t 14 t 18
t 19
t 20 t 21 t 24
t 26
SCLK 1 2 3 14 15 16

t 15
t 27
SDOUT X D15 D14 D2 D1 D0

t 16 t 23
t 22

Figure 17. Master Serial Data Timing for Reading (Read after Convert)

EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0

CS, RD

t1
CNVST

t3

BUSY

t 17
t 25
SYNC

t 14 t 19
t 20 t 21
t 24
t 26
t 15
SCLK 1 2 3 14 15 16
t 18
t 27

SDOUT X D15 D14 D2 D1 D0

t 16 t 23
t 22

Figure 18. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
–18– REV. B
 AD7671
EXT/INT = 1 INVSCLK = 0 RD = 0

CS, RD

BUSY

t35
t36 t37

SCLK 1 2 3 14 15 16 17 18

t31 t32

SDOUT X D15 D14 D13 D1 D0 X15 X14

t16
t34

SDIN X15 X14 X13 X1 X0 Y15 Y14

t33

Figure 19. Slave Serial Data Timing for Reading (Read after Convert)

the AD7671 provides error correction circuitry that can correct BUSY
for an improper bit decision made during the first half of the OUT

conversion phase. For this reason, it is recommended that when BUSY BUSY
an external clock is being provided, it is a discontinuous clock
that is toggling only when BUSY is LOW or, more importantly, AD7671 AD7671
#2 #1
that does not transition during the latter half of BUSY HIGH. (UPSTREAM) (DOWNSTREAM)

External Discontinuous Clock Data Read after Conversion RDC/SDIN SDOUT DATA
RDC/SDIN SDOUT
OUT
Though the maximum throughput cannot be achieved using this
CNVST CNVST
mode, it is the most recommended of the serial slave modes.
CS CS
Figure 19 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning LOW, SCLK SCLK
the result of this conversion can be read while both CS and RD
are LOW. The data is shifted out, MSB first, with 16 clock SCLK IN
pulses and is valid on both the rising and falling edge of the clock. CS IN
CNVST IN
Among the advantages of this method, the conversion perfor-
mance is not degraded because there are no voltage transients Figure 20. Two AD7671s in a Daisy-Chain Configuration
on the digital interface during the conversion process.
External Clock Data Read during Conversion
Another advantage is to be able to read the data at any speed up to Figure 21 shows the detailed timing diagrams of this method.
40 MHz, which accommodates both slow digital host interface During a conversion, while both CS and RD are LOW, the result
and the fastest serial reading. of the previous conversion can be read. The data is shifted out,
Finally, in this mode only, the AD7671 provides a “daisy-chain” MSB first, with 16 clock pulses and is valid on both the rising and
feature using the RDC/SDIN input pin for cascading multiple the falling edge of the clock. The 16 bits have to be read before the
converters together. This feature is useful for reducing component current conversion is complete. If that is not done, RDERROR
count and wiring connections when desired as, for instance, in is pulsed HIGH and can be used to interrupt the host interface
isolated multiconverter applications. to prevent incomplete data reading. There is no daisy-chain feature
in this mode, and RDC/SDIN input should always be tied either
An example of the concatenation of two devices is shown in Fig-
HIGH or LOW.
ure 20. Simultaneous sampling is possible by using a common
CNVST signal. It should be noted that the RDC/SDIN input is
latched on the opposite edge of SCLK of the one used to shift out
the data on SDOUT. Therefore, the MSB of the “upstream”
converter just follows the LSB of the “downstream” converter
on the next SCLK cycle.

REV. B –19–
AD7671
EXT/INT = 1 INVSCLK = 0 RD = 0

CS

CNVST

BUSY

t3 t 35
t 36 t 37

SCLK 1 2 3 14 15 16
t 31
t 32

SDOUT X D15 D14 D13 D1 D0

t 16

Figure 21. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)

DVDD
To reduce performance degradation due to digital activity, a fast
AD7671* MC68HC11*
discontinuous clock of at least 25 MHz when Impulse Mode is
SER/PAR
used, 32 MHz when Normal or 40 MHz when Warp Mode is
EXT/INT
used, is recommended to ensure that all the bits are read during
CS
the first half of the conversion phase. It is also possible to begin
RD BUSY IRQ
to read the data after conversion and continue to read the last bits
SDOUT MISO/SDI
even after a new conversion has been initiated. That allows the use
SCLK SCK
of a slower clock speed like 18 MHz in Impulse Mode, 21 MHz INVSCLK CNVST I/O PORT
in Normal Mode, and 26 MHz in Warp Mode.
*ADDITIONAL PINS OMITTED FOR CLARITY

MICROPROCESSOR INTERFACING
Figure 22. Interfacing the AD7671 to SPI Interface
The AD7671 is ideally suited for traditional dc measurement
applications supporting a microprocessor and ac signal processing ADSP-21065L in Master Serial Interface
applications interfacing to a digital signal processor. The AD7671 As shown in Figure 23, the AD7671 can be interfaced to the
is designed to interface either with a parallel 8-bit or 16-bit wide ADSP-21065L using the serial interface in Master Mode without
interface or with a general-purpose Serial Port or I/O Ports on a any glue logic required. This mode combines the advantages
microcontroller. A variety of external buffers can be used with of reducing the wire connections and the ability to read the
the AD7671 to prevent digital noise from coupling into the ADC. data during or after conversion at maximum speed transfer
The following sections illustrate the use of the AD7671 with an (DIVSCLK[0:1] both low).
SPI equipped microcontroller, the ADSP-21065L and ADSP-218x
The AD7671 is configured for the Internal Clock Mode (EXT/INT
signal processors.
LOW) and acts therefore as the master device. The convert
SPI Interface (MC68HC11) command can be generated by either an external low jitter oscil-
Figure 22 shows an interface diagram between the AD7671 and an lator or, as shown, by a FLAG output of the ADSP-21065L or by
SPI-equipped microcontroller, such as the MC68HC11. To accom- a frame output TFS of one Serial Port of the ADSP-21065L, which
modate the slower speed of the microcontroller, the AD7671 acts as can be used like a timer. The Serial Port on the ADSP-21065L
a slave device and data must be read after conversion. This mode is configured for external clock (IRFS = 0), rising edge active
also allows the daisy-chain feature. The convert command could be (CKRE = 1), external late framed sync signals (IRFS = 0,
initiated in response to an internal timer interrupt. The reading of LAFS = 1, RFSR = 1), and active HIGH (LRFS = 0). The Serial
output data, one byte at a time if necessary, could be initiated in Port of the ADSP-21065L is configured by writing to its receive
response to the end-of-conversion signal (BUSY going low) using control register (SRCTL)—see ADSP-2106x SHARC User’s
an interrupt line of the microcontroller. The serial peripheral Manual. Because the Serial Port within the ADSP-21065L will
interface (SPI) on the MC68HC11 is configured for Master Mode be seeing a discontinuous clock, an initial word reading has to
(MSTR) = 1, Clock Polarity Bit (CPOL) = 0, Clock Phase Bit be done after the ADSP-21065L has been reset to ensure that
(CPHA) = 1, and SPI interrupt enable (SPIE) = 1 by writing to the Serial Port is properly synchronized to this clock during each
the SPI Control Register (SPCR). The IRQ is configured for edge- following data read operation.
sensitive-only operation (IRQE = 1 in the OPTION register).

–20– REV. B
 AD7671
DVDD The power supply lines to the AD7671 should use as large a trace
AD7671* ADSP-21065L* as possible to provide low impedance paths and reduce the effect of
SHARC ®
SER/PAR glitches on the power supply lines. Good decoupling is also impor-
RDC/SDIN tant to lower the supplies impedance presented to the AD7671
RD and to reduce the magnitude of the supply spikes. Decoupling
EXT/INT SYNC RFS ceramic capacitors, typically 100 nF, should be placed on all of
CS SDOUT DR the power supply pins power supplies pins AVDD, DVDD, and
INVSYNC SCLK RCLK OVDD close to, and ideally right up against, these pins and
INVSCLK CNVST FLAG OR TFS their corresponding ground pins. Additionally, low ESR 10 mF
*ADDITIONAL PINS OMITTED FOR CLARITY
capacitors should be located in the vicinity of the ADC to further
reduce low frequency ripple.
Figure 23. Interfacing to the ADSP-21065L Using The DVDD supply of the AD7671 can be either a separate sup-
the Serial Master Mode ply or come from the analog supply, AVDD, or from the digital
interface supply, OVDD. When the system digital supply is noisy,
APPLICATION HINTS or fast switching digital signals are present, it is recommended,
Layout if no separate supply is available, to connect the DVDD digital
The AD7671 has very good immunity to noise on the power supply to the analog supply AVDD through an RC filter as shown
supplies as can be seen in Figure 9. However, care should still in Figure 5 and to connect the system supply to the interface
be taken with regard to grounding layout. digital supply OVDD and the remaining digital circuitry. When
The printed circuit board that houses the AD7671 should be DVDD is powered from the system supply, it is useful to insert
designed so the analog and digital sections are separated and con- a bead to further reduce high frequency spikes.
fined to certain areas of the board. This facilitates the use of ground The AD7671 has five different ground pins: INGND, REFGND,
planes that can be easily separated. Digital and analog ground AGND, DGND, and OGND. INGND is used to sense the
planes should be joined in only one place, preferably underneath analog input signal. REFGND senses the reference voltage and
the AD7671, or, at least, as close as possible to the AD7671. If should be a low impedance return to the reference because it carries
the AD7671 is in a system where multiple devices require analog- pulsed currents. AGND is the ground to which most internal ADC
to-digital ground connections, the connection should still be made at analog signals are referenced. This ground must be connected
one point only, a star ground point, which should be established with the least resistance to the analog ground plane. DGND must
as close as possible to the AD7671. be tied to the analog or digital ground plane depending on the
It is recommended to avoid running digital lines under the device configuration. OGND is connected to the digital system ground.
as these will couple noise onto the die. The analog ground plane The layout of the decoupling of the reference voltage is important.
should be allowed to run under the AD7671 to avoid noise The decoupling capacitor should be close to the ADC and con-
coupling. Fast switching signals like CNVST or clocks should nected with short and large traces to minimize parasitic inductances.
be shielded with digital ground to avoid radiating noise to other
sections of the board and should never run near analog signal Evaluating the AD7671 Performance
paths. Crossover of digital and analog signals should be avoided. A recommended layout for the AD7671 is outlined in the evalua-
Traces on different but close layers of the board should run at right tion board for the AD7671. The evaluation board package includes
angles to each other. This will reduce the effect of feedthrough a fully assembled and tested evaluation board, documentation,
through the board. and software for controlling the board from a PC via the Eval-
Control Board.

REV. B –21–
AD7671
OUTLINE DIMENSIONS

48-Lead Low Profile Quad Flat Package [LQFP]

(ST-48)
Dimensions shown in millimeters

0.75 9.00 BSC

1.60
0.60 MAX SQ
0.45 48 37
1 36

SEATING PIN 1
10
PLANE
1.45 6
TOP VIEW 7.00
0.20 (PINS DOWN) BSC SQ
1.40 2

0.09
1.35 VIEW A
7

3.5

12 25
0.15 0
13 24
0.05 SEATING 0.10 MAX
PLANE 0.50 0.27
COPLANARITY
BSC 0.22
VIEW A 0.17
ROTATED 90
CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC

48-Lead Lead Frame Chip Scale Package [LFCSP]

(CP-48)
Dimensions shown in millimeters

0.30
7.00 0.60 MAX 0.23
BSC SQ 0.18
0.60 MAX PIN 1
INDICATOR
37 48
36 1
PIN 1
INDICATOR

6.75 5.25
TOP BSC SQ BOTTOM 5.10 SQ
VIEW VIEW
4.95

0.50
0.40 25 12
24 13
0.30

5.50
0.80 MAX REF
1.00 12
MAX PADDLE CONNECTED TO AGND.
0.65 NOM
0.90 THIS CONNECTION IS NOT
0.80 0.05 MAX REQUIRED TO MEET THE
0.02 NOM ELECTRICAL PERFORMANCES
0.20 0.50 BSC
REF COPLANARITY
SEATING 0.08
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2

–22– REV. B
 AD7671
Revision History
Location Page
4/03—Data Sheet changed from REV. A to REV. B.
Changes to PulSAR Selection table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Changes to Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5/02—Data Sheet changed from REV. 0 to REV. A.
Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Chart added to PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Edits to Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edits to TPC 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
New TPC 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Addition of TPC 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Edits to Table III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Edits to Driver Amplifier Choice section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
New Voltage Reference Input section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
New ST-48 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

REV. B –23–
–24–
C02567–0–5/03(B)