0% found this document useful (0 votes)

20 views115 pages

STM32L021 Ultra-Low-Power MCU Datasheet

Uploaded by

korev67897

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

0% found this document useful (0 votes)

20 views115 pages

STM32L021 Ultra-Low-Power MCU Datasheet

Uploaded by

korev67897

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

STM32L021D4 STM32L021F4

STM32L021G4 STM32L021K4
Access line ultra-low-power 32-bit MCU Arm®-based
Cortex®-M0+, 16KB Flash, 2KB SRAM, 512B EEPROM, ADC, AES
Datasheet - production data

Features
• Ultra-low-power platform
– 1.65 V to 3.6 V power supply
– -40 to 125 °C temperature range TSSOP14/20 UFQFPN20 3x3 mm LQFP32
– 0.23 µA Standby mode (2 wakeup pins) 169 mils UFQFPN28 4x4 mm 7x7 mm
UFQFPN32 5x5 mm
– 0.29 µA Stop mode (16 wakeup lines)
– 0.54 µA Stop mode + RTC + 2 KB RAM • Rich Analog peripherals
retention – 12-bit ADC 1.14 Msps up to 10 channels (down
– Down to 76 µA/MHz in Run mode to 1.65 V)
– 5 µs wakeup time (from Flash memory) – 2x ultra-low-power comparators (window mode
– 41 µA 12-bit ADC conversion at 10 ksps and wake up capability, down to 1.65 V)
• Core: Arm® 32-bit Cortex®-M0+ • 5-channel DMA controller, supporting ADC, SPI,
– From 32 kHz to 32 MHz max. I2C, USART, Timers, AES
– 0.95 DMIPS/MHz • 4x peripherals communication interface
• Reset and supply management • 1x USART (ISO 7816, IrDA), 1x UART (low power)
– Ultra-safe, low-power BOR (brownout reset) • 1x SPI 16 Mbits/s
with 5 selectable thresholds
– Ultralow power POR/PDR • 1x I2C (SMBus/PMBus)
– Programmable voltage detector (PVD) • 7x timers: 1x 16-bit with up to 4 channels, 1x 16-bit
• Clock sources with up to 2 channels, 1x 16-bit ultra-low-power
– 0 to 32 MHz external clock timer, 1x SysTick, 1x RTC and 2x watchdogs
(independent/window)
– 32 kHz oscillator for RTC with calibration
– High speed internal 16 MHz factory-trimmed RC • CRC calculation unit, 96-bit unique ID
(+/- 1%) • Hardware Encryption Engine AES 128-bit
– Internal low-power 37 kHz RC
• All packages are ECOPACK®2
– Internal multispeed low-power 65 kHz to
4.2 MHz RC
– PLL for CPU clock
• Pre-programmed bootloader
– USART, SPI supported
• Development support
– Serial wire debug supported
• Up to 28 fast I/Os (23 I/Os 5V tolerant)
• Memories
– 16 KB Flash memory with ECC
– 2 KB RAM
– 512 B of data EEPROM with ECC
– 20-byte backup register
– Sector protection against R/W operation
–

September 2017 DocID027982 Rev 5 1/114

This is information on a product in full production. [Link]
Contents STM32L021x4

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2 Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3 Arm® Cortex®-M0+ core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.6 Low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 24
3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.8 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.9 Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.11 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.11.1 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.12 Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 27
3.13 System configuration controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.14 AES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.15 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.15.1 General-purpose timers (TIM2, TIM21) . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.15.2 Low-power Timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.15.3 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.15.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.15.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2/114 DocID027982 Rev 5

STM32L021x4 Contents

3.16 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.16.1 I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.16.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 31
3.16.3 Low-power universal asynchronous receiver transmitter (LPUART) . . . 31
3.16.4 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.17 Cyclic redundancy check (CRC) calculation unit . . . . . . . . . . . . . . . . . . . 32
3.18 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 49
6.3.3 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.3.5 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

DocID027982 Rev 5 3/114

4
Contents STM32L021x4

6.3.15 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6.3.16 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.3.17 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.18 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.1 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
7.2 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.3 UFQFPN28 4 x 4 mm package information . . . . . . . . . . . . . . . . . . . . . . . 99
7.4 UFQFPN20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.5 TSSOP20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
7.6 TSSOP14 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
7.7 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.7.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

4/114 DocID027982 Rev 5

STM32L021x4 List of tables

List of tables

Table 1. Ultra-low-power STM32L021x4 device features and peripheral counts . . . . . . . . . . . . . . . 11

Table 2. Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 16
Table 3. CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Functionalities depending on the working mode
(from Run/active down to standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. STM32L021x4 peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 7. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 8. STM32L021x4 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 9. USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 10. SPI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 11. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 12. Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 13. Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 14. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 15. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 16. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 17. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 18. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 19. Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 20. Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 21. Current consumption in Run mode, code with data processing running from Flash. . . . . . 53
Table 22. Current consumption in Run mode vs code type,
code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 23. Current consumption in Run mode, code with data processing running from RAM . . . . . . 55
Table 24. Current consumption in Run mode vs code type,
code with data processing running from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 25. Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 26. Current consumption in Low-power Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 27. Current consumption in Low-power Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 28. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 29. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 60
Table 30. Average current consumption during wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 31. Peripheral current consumption in run or Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 32. Peripheral current consumption in Stop and Standby mode . . . . . . . . . . . . . . . . . . . . . . . 62
Table 33. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 34. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 35. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 36. LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 37. 16 MHz HSI16 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 38. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 39. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 40. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 41. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 42. Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 43. Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 71
Table 44. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 45. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

DocID027982 Rev 5 5/114

6
List of tables STM32L021x4

Table 46. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 47. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 48. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 49. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 50. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 51. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 52. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 53. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 54. RAIN max for fADC = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 55. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 56. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 57. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 58. Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 59. Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 60. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 61. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 62. I2C frequency in all I2C modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 63. SPI characteristics in voltage Range 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 64. SPI characteristics in voltage Range 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 65. SPI characteristics in voltage Range 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 66. LQFP32 - 32-pin, 7 x 7 mm, 32-pin low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 67. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 68. WLCSP25 - 25-ball, 2.133 x 2.070 mm, 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 69. UFQFPN28 - 28-lead, 4x4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 70. UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 71. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 72. TSSOP14 – 14-lead thin shrink small outline, 5 x 4.4 mm, 0.65 mm pitch,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 73. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 74. STM32L021x4 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 75. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

6/114 DocID027982 Rev 5

STM32L021x4 List of figures

List of figures

Figure 1. STM32L021x4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 3. STM32L021x4 LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 4. STM32L021x4 UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 5. STM32L021x4 UFQFPN28 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 6. STM32L021x4 UFQFPN20 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 7. STM32L021x4 TSSOP20 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 8. STM32L021x4 TSSOP14 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 9. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 11. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 12. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 13. IDD vs VDD, at TA= 25 °C, Run mode, code running from
Flash memory, Range 2, 16 MHz HSE, 1WS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 14. IDD vs VDD, at TA= 25 °C, Run mode, code running from
Flash memory, Range 2, HSI16, 1WS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 15. IDD vs VDD, at TA= -40/25/55/ 85/105/125 °C, Low-power run mode,
code running from RAM, Range 3, MSI (Range 0) at 64 KHz, 0 WS . . . . . . . . . . . . . . . . . 58
Figure 16. IDD vs VDD, at TA= -40/25/55/ 85/105/125 °C, Stop mode with RTC enabled
and running on LSE Low drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 17. IDD vs VDD, at TA= -40/25/55/85/105/125 °C, Stop mode with RTC disabled,
all clocks OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 18. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 19. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 20. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 21. HSI16 minimum and maximum value versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 22. VIH/VIL versus VDD (CMOS I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 23. VIH/VIL versus VDD (TTL I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 24. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 25. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 26. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 27. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 28. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 29. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 30. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 31. LQFP32 - 32-pin, 7 x 7 mm, 32-pin low-profile quad flat package outline . . . . . . . . . . . . . 94
Figure 32. LQFP32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 33. Example of LQFP32 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 34. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 35. UFQFPN32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 36. UFQFPN28 - 28-lead, 4x4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 37. UFQFPN28 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 38. Example of UFQFPN28 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 39. UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 40. UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat

DocID027982 Rev 5 7/114

8
List of figures STM32L021x4

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 41. Example of UFQFPN20 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 42. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 43. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 44. TSSOP14 – 14-lead thin shrink small outline, 5.0 x 4.4 mm, 0.65 mm pitch,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 45. Example of TSSOP14 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 46. Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

8/114 DocID027982 Rev 5

STM32L021x4 Introduction

1 Introduction

The ultra-low-power STM32L021x4 family includes devices in 6 different package types

from 14 to 32 pins. The description below gives an overview of the complete range of
peripherals proposed in this family.
These features make the ultra-low-power STM32L021x4 microcontrollers suitable for a wide
range of applications:
• Gas/water meters and industrial sensors
• Healthcare and fitness equipment
• Remote control and user interface
• PC peripherals, gaming, GPS equipment
• Alarm system, wired and wireless sensors, video intercom
This STM32L021x4 datasheet should be read in conjunction with the STM32L0x1 reference
manual (RM0377).
For information on the Arm® Cortex®-M0+ core please refer to the Cortex®-M0+ Technical
Reference Manual, available from the [Link] website.
Figure 1 shows the general block diagram of the device family.

DocID027982 Rev 5 9/114

32
Description STM32L021x4

2 Description

The access line ultra-low-power STM32L021x4 family incorporates the high-performance

Arm® Cortex®-M0+ 32-bit RISC core operating at a 32 MHz frequency, high-speed
embedded memories (16 Kbytes of Flash program memory, 512 bytes of data EEPROM and
2 Kbytes of RAM) plus an extensive range of enhanced I/Os and peripherals.
The STM32L021x4 devices provide high power efficiency for a wide range of performance.
It is achieved with a large choice of internal and external clock sources, an internal voltage
adaptation and several low-power modes.
The STM32L021x4 devices offer several analog features, one 12-bit ADC with hardware
oversampling, two ultra-low-power comparators, AES, several timers, one low-power timer
(LPTIM), three general-purpose 16-bit timers, one RTC and one SysTick which can be used
as timebases. They also feature two watchdogs, one watchdog with independent clock and
window capability and one window watchdog based on bus clock.
Moreover, the STM32L021x4 devices embed standard and advanced communication
interfaces: one I2C, one SPI, one USART, and a low-power UART (LPUART).
The STM32L021x4 also include a real-time clock and a set of backup registers that remain
powered in Standby mode.
The ultra-low-power STM32L021x4 devices operate from a 1.8 to 3.6 V power supply (down
to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without BOR
option. They are available in the -40 to +125 °C temperature range. A comprehensive set of
power-saving modes allows the design of low-power applications.

10/114 DocID027982 Rev 5

STM32L021x4 Description

2.1 Device overview

Table 1. Ultra-low-power STM32L021x4 device features and peripheral counts
Peripheral STM32 L021D4 STM32 L021F4 STM32 L021G4 STM32L021K4

Flash (Kbytes) 16

Data EEPROM (bytes) 512

RAM (Kbytes) 2

AES 1

General-
2
purpose
Timers
LPTIM 1

RTC/SYSTICK/IWDG/
1/1/1/1
WWDG

SPI 1

I2C 1
Communication
interfaces USART 1

LPUART 1

GPIOs 11 16 24 26/28(1)

Clocks: HSE(2)/LSE/HSI/MSI/LSI 1/1/1/1/1

12-bit synchronized ADC 1 1 1

Number of channels 4 7/9(3) 10

Comparators 2

Max. CPU frequency 32 MHz

1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option

Operating voltage
1.65 V to 3.6 V without BOR option
Ambient temperature: –40 to +125 °C
Operating temperatures
Junction temperature: –40 to +130 °C
TSSOP20, LQFP32,
Packages TSSOP14 UFQFPN28
UFQFPN20 UFQFPN32
1. The devices feature 26 and 28 GPIOs on LQFP32 and UFQFPN32, respectively.
2. HSE available only as external clock input (HSE bypass).
3. The devices feature 7 and 9 ADC channels on UFQFPN20 and TSSOP20, respectively.

DocID027982 Rev 5 11/114

32
Description STM32L021x4

Figure 1. STM32L021x4 block diagram

7HPS
6:' 6:' VHQVRU

)/$6+
((3520
%227 $'& $,1[

0,62026,
63, 6&.166
&257(;0&38
)PD[0+] 5$0

'%* $
3
'0$ 7,0 FK
19,& %

(;7,

%5,'*(
&203 ,13,10287

&203 ,13,10287

&5&

%5,'*(

$(6 ,1,1
3$>@ *3,23257$ /37,0 (75287
$+%)PD[0+]

3%>@ *3,23257%

6&/6'$
::'* ,&
60%$
3&>@ *3,23257&

$
3
% 5;7;576
86$57
&76&.

3+>@ *3,23257+ 5;7;576

/38$57 &76

&.B,1 +6( +6,0

/6, ,:'*
7,0 FK
3//

06, 57&

%&.35(*
:.83[ 5(6(7 &/.

26&B,1 /6(
26&B287
39'B,1
95()B287
308
1567

9''$

9'' 5(*8/$725

06Y9

12/114 DocID027982 Rev 5

STM32L021x4 Description

2.2 Ultra-low-power device continuum

The ultra-low-power family offers a large choice of core and features, from 8-bit proprietary
core up to Arm® Cortex®-M4, including Arm® Cortex®-M3 and Arm® Cortex®-M0+. The
STM32Lx series are the best choice to answer your needs in terms of ultra-low-power
features. The STM32 Ultra-low-power series are the best solution for applications such as
gas/water meter, keyboard/mouse or fitness and healthcare application. Several built-in
features like LCD drivers, dual-bank memory, low-power Run mode, operational amplifiers,
128-bit AES, DAC, crystal-less USB and many other definitely help you building a highly
cost optimized application by reducing BOM cost. STMicroelectronics, as a reliable and
long-term manufacturer, ensures as much as possible pin-to-pin compatibility between all
STM8Lx and STM32Lx on one hand, and between all STM32Lx and STM32Fx on the other
hand. Thanks to this unprecedented scalability, your legacy application can be upgraded to
respond to the latest market feature and efficiency requirements.

DocID027982 Rev 5 13/114

32
Functional overview STM32L021x4

Range 1
32 kHz to 16 MHz (0ws)
8 MHz to 16 MHz (1ws)
Range 2
32 kHz to 8 MHz (0ws)

32 kHz to 4.2 MHz (0ws) Range 3

16/114 DocID027982 Rev 5

STM32L021x4 Functional overview

Table 4. Functionalities depending on the working mode

(from Run/active down to standby) (1)(2)
Stop Standby
Low- Low-
IPs Run/Active Sleep power power
Wakeup Wakeup
run sleep
capability capability

CPU Y - Y - - - - -
Flash memory O O O O - - - -
RAM Y Y Y Y Y - - -
Backup registers Y Y Y Y Y - Y -
EEPROM O O O O - - - -
Brown-out reset
O O O O O O O O
(BOR)
DMA O O O O - - - -
Programmable
Voltage Detector O O O O O O - -
(PVD)
Power-on/down
Y Y Y Y Y Y Y Y
reset (POR/PDR)
High Speed (3)
O O - - - - -
Internal (HSI)
High Speed
O O O O - - - -
External (HSE)
Low Speed Internal
O O O O O - O -
(LSI)
Low Speed
O O O O O - O -
External (LSE)
Multi-Speed
O O Y Y - - - -
Internal (MSI)
Inter-Connect
Y Y Y Y Y - - -
Controller
RTC O O O O O O O -
RTC Tamper O O O O O O O O
Auto WakeUp
O O O O O - O O
(AWU)
USART O O O O O(4) O - -
(4)
LPUART O O O O O O - -
SPI O O O O - - -
I2C O O O O O(5) O - -
ADC O O - - - - - -
Temperature
O O O O O - - -
sensor

DocID027982 Rev 5 17/114

32
Functional overview STM32L021x4

Table 4. Functionalities depending on the working mode

(from Run/active down to standby) (continued)(1)(2)
Stop Standby
Low- Low-
IPs Run/Active Sleep power power
Wakeup Wakeup
run sleep
capability capability

Comparators O O O O O O - -
16-bit timers O O O O - - - -
LPTIM O O O O O O - -
IWDG O O O O O O O O
WWDG O O O O - - - -
SysTick Timer O O O O - - - -
GPIOs O O O O O O - 2 pins
Wakeup time to 7 CPU
0 µs 6 CPU cycles 3 µs 5 µs 65 µs
Run mode cycles
0.29 µA (No 0.18 µA (No
RTC) VDD=1.8 V RTC) VDD=1.8 V
0.54 µA (with 0.41 µA (with
Consumption Down to Down to RTC) V =1.8 V RTC) VDD=1.8 V
Down to Down to DD
VDD=1.8 to 3.6 V 128 µA/MHz 31 µA/MHz
7 µA 3.8 µA 0.34 µA (No 0.23 µA (No
(Typ) (from Flash) (from Flash)
RTC) VDD=3.0 V RTC) VDD=3.0 V
0.67 µA (with 0.53 µA (with
RTC) VDD=3.0 V RTC) VDD=3.0 V
1. Legend:
“Y” = Yes (enable).
“O” = Optional, can be enabled/disabled by software)
“-” = Not available
2. The consumption values given in this table are preliminary data given for indication. They are subject to slight changes.
3. Some peripherals with wakeup from Stop capability can request HSI to be enabled. In this case, HSI is woken up by the
peripheral, and only feeds the peripheral which requested it. HSI is automatically put off when the peripheral does not need
it anymore.
4. UART and LPUART reception is functional in Stop mode. It generates a wakeup interrupt on [Link] generate a wakeup on
address match or received frame event, the LPUART can run on LSE clock while the UART has to wake up or keep running
the HSI clock.
5. I2C address detection is functional in Stop mode. It generates a wakeup interrupt in case of address match. It will wake up
the HSI during reception.

3.2 Interconnect matrix

Several peripherals are directly interconnected. This allows autonomous communication
between peripherals, thus saving CPU resources and power consumption. In addition,
these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power

run, Low-power sleep and Stop modes.

18/114 DocID027982 Rev 5

STM32L021x4 Functional overview

Table 5. STM32L021x4 peripherals interconnect matrix

Low- Low-
Interconnect Interconnect
Interconnect action Run Sleep power power Stop
source destination
run sleep

3.3 Arm® Cortex®-M0+ core

The Cortex-M0+ processor is an entry-level 32-bit Arm Cortex processor designed for a
broad range of embedded applications. It offers significant benefits to developers, including:
• a simple architecture that is easy to learn and program
• ultra-low power, energy-efficient operation
• excellent code density
• deterministic, high-performance interrupt handling
• upward compatibility with Cortex-M processor family
• platform security robustness.
The Cortex-M0+ processor is built on a highly area and power optimized 32-bit processor
core, with a 2-stage pipeline von Neumann architecture. The processor delivers exceptional
energy efficiency through a small but powerful instruction set and extensively optimized
design, providing high-end processing hardware including a single-cycle multiplier.
The Cortex-M0+ processor provides the exceptional performance expected of a modern 32-
bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.
Owing to its embedded Arm core, the STM32L021x4 are compatible with all Arm tools and
software.

DocID027982 Rev 5 19/114

32
Functional overview STM32L021x4

Nested vectored interrupt controller (NVIC)

The ultra-low-power STM32L021x4 embed a nested vectored interrupt controller able to
handle up to 32 maskable interrupt channels and 4 priority levels.
The Cortex-M0+ processor closely integrates a configurable Nested Vectored Interrupt
Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC:
• includes a Non-Maskable Interrupt (NMI)
• provides zero jitter interrupt option
• provides four interrupt priority levels
The tight integration of the processor core and NVIC provides fast execution of Interrupt
Service Routines (ISRs), dramatically reducing the interrupt latency. This is achieved
through the hardware stacking of registers, and the ability to abandon and restart load-
multiple and store-multiple operations. Interrupt handlers do not require any assembler
wrapper code, removing any code overhead from the ISRs. Tail-chaining optimization also
significantly reduces the overhead when switching from one ISR to another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a
deep sleep function that enables the entire device to enter rapidly stop or standby mode.
This hardware block provides flexible interrupt management features with minimal interrupt
latency.

3.4 Reset and supply management

3.4.1 Power supply schemes

• VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
externally through VDD pins.
• VSSA, VDDA = 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. On
TSSOP14 package, VDDA is internally connected to VDD.

3.4.2 Power supply supervisor

The devices feature an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
Two versions are available:
• The version with BOR activated at power-on operates between 1.8 V and 3.6 V.
• The other version without BOR operates between 1.65 V and 3.6 V.
After the VDD threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or
not at power-on), the option byte loading process starts, either to confirm or modify default
thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes
1.65 V (whatever the version, BOR active or not, at power-on).
When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever
the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the
power ramp-up should guarantee that 1.65 V is reached on VDD at least 1 ms after it exits
the POR area.

20/114 DocID027982 Rev 5

STM32L021x4 Functional overview

Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Stop mode, it is possible to automatically switch off the
internal reference voltage (VREFINT) in Stop mode. The device remains in reset mode when
VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external
reset circuit.
Note: The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the start-
up time at power-on can be decreased down to 1 ms typically for devices with BOR inactive
at power-up.
The devices feature an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when
VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

3.4.3 Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.
• MR is used in Run mode (nominal regulation)
• LPR is used in the Low-power run, Low-power sleep and Stop modes
• Power down is used in Standby mode. The regulator output is high impedance, the
kernel circuitry is powered down, inducing zero consumption but the contents of the
registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,
LSI, LSE crystal 32 KHz oscillator, RCC_CSR).

3.4.4 Boot modes

At startup, BOOT0 pin and nBOOT0, nBOOT1 and nBOOT_SEL option bits are used to
select one of three boot options:
• Boot from Flash memory
• Boot from System memory
• Boot from embedded RAM
The bootloader is located in System memory. It is used to reprogram the Flash memory by
using SPI1 (PA4, PA7, PA13 and PA14 on TSSOP14 package or PA4, PA5, PA6 and PA7
on other packages) or USART2 (PA2, PA3 and PA9, PA10).
If the bootloader is activated (the bootloader is active on all empty devices due to the empty
check mechanism), then the above mentioned bits are configured depending on whether
SPI1 or USART2 functionality is used.
See STM32™ microcontroller system memory boot mode AN2606 for details.

DocID027982 Rev 5 21/114

32
Functional overview STM32L021x4

3.5 Clock management

The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:
• Clock prescaler
To get the best trade-off between speed and current consumption, the clock frequency
to the CPU and peripherals can be adjusted by a programmable prescaler.
• Safe clock switching
Clock sources can be changed safely on the fly in Run mode through a configuration
register.
• Clock management
To reduce power consumption, the clock controller can stop the clock to the core,
individual peripherals or memory.
• System clock source
Three different clock sources can be used to drive the master clock SYSCLK:
– 0-32 MHz high-speed external (HSE bypass), that can supply a PLL
– 16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can
supply a PLL
– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7
frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz).
When a 32.768 kHz clock source is available in the system (LSE), the MSI
frequency can be trimmed by software down to a ±0.5% accuracy.
• Auxiliary clock source
Two ultra-low-power clock sources that can be used to drive the real-time clock:
– 32.768 kHz low-speed external crystal (LSE)
– 37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock can be measured using the high-speed internal RC oscillator for
greater precision.
• RTC clock sources
The LSI, LSE or HSE sources can be chosen to clock the RTC, whatever the system
clock.
• Startup clock
After reset, the microcontroller restarts by default with an internal 2 MHz clock (MSI).
The prescaler ratio and clock source can be changed by the application program as
soon as the code execution starts.
• Clock security system (CSS)
This feature can be enabled by software. If an LSE clock failure occurs, it provides an
interrupt or wakeup event which is generated assuming it has been previously enabled.
This feature is not available on the HSE clock.
• Clock-out capability (MCO: microcontroller clock output)
It outputs one of the internal clocks for external use by the application.
Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and
APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See
Figure 2 for details on the clock tree.

22/114 DocID027982 Rev 5

STM32L021x4 Functional overview

Figure 2. Clock tree

#9 (QDEOH:DWFKGRJ
:DWFKGRJ/6 /HJHQG
/6,5& /6,WHPSR +6( +LJKVSHHGH[WHUQDOFORFNVLJQDO
57&6(/ +6, +LJKVSHHGLQWHUQDOFORFNVLJQDO
/6, /RZVSHHGLQWHUQDOFORFNVLJQDO
57&HQDEOH /6( /RZVSHHGH[WHUQDOFORFNVLJQDO
06, 0XOWLVSHHGLQWHUQDOFORFNVLJQDO
57&
/6(26& /6(WHPSR

/68 /6' /6'

#9
0+]

#9 0&26(/ $'&HQDEOH

/6,
06,5& $'&&/.
06, /6(
/HYHOVKLIWHUV
#9 0&2
QRWGHHSVOHHS

#9 &.B3:5
QRWGHHSVOHHS
+6,5&
FNBUFKV +6,
/HYHOVKLIWHUV QRW VOHHSRU )&/.
#9 GHHSVOHHS
6\VWHP
&ORFN QRW VOHHSRU +&/.
GHHSVOHHS

#9 06, 7,0[&/.
+6( +6, $+%
%<3$66 +6( 35(6& 3&/.WR$3%
/HYHOVKLIWHUV 3//65& « SHULSKHUDOV
#9 #9
3//&/. $3%
35(6&
FNBSOOLQ 3//
; 3HULSKHUDO
FORFNHQDEOH
WR7,0
,I $3%SUHVF [

HOVH[
/HYHOVKLIWHUV
3HULSKHUDO
#9''&25(
&ORFN FORFNHQDEOH
3&/.WR$3%
6RXUFH 0+] SHULSKHUDOV
$3% PD[
&RQWURO 35(6&

3HULSKHUDO
FORFNHQDEOH
WR7,0
,I $3%SUHVF [
HOVH[

3HULSKHUDOV
/6, HQDEOH

/37,0&/.
/6( 3HULSKHUDOV
HQDEOH
+6,
6<6&/.
3&/. 3HULSKHUDOV /38$57
HQDEOH 8$57&/.

,&&/.

06Y9

DocID027982 Rev 5 23/114

32
Functional overview STM32L021x4

3.6 Low-power real-time clock and backup registers

The real time clock (RTC) and the 5 backup registers are supplied in all modes including
standby mode. The backup registers are five 32-bit registers used to store 20 bytes of user
application data. They are not reset by a system reset, or when the device wakes up from
Standby mode.
The RTC is an independent BCD timer/counter. Its main features are the following:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format
• Automatically correction for 28, 29 (leap year), 30, and 31 day of the month
• Two programmable alarms with wake up from Stop and Standby mode capability
• Periodic wakeup from Stop and Standby with programmable resolution and period
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
• Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy
• 2 anti-tamper detection pins with programmable filter. The MCU can be woken up from
Stop and Standby modes on tamper event detection.
• Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.
The RTC clock sources can be:
• A 32.768 kHz external crystal
• A resonator or oscillator
• The internal low-power RC oscillator (typical frequency of 37 kHz)
• The high-speed external clock

3.7 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions, and can be individually
remapped using dedicated alternate function registers. All GPIOs are high current capable.
Each GPIO output, speed can be slowed (40 MHz, 10 MHz, 2 MHz, 400 kHz). The alternate
function configuration of I/Os can be locked if needed following a specific sequence in order
to avoid spurious writing to the I/O registers. The I/O controller is connected to a dedicated
IO bus with a toggling speed of up to 32 MHz.
The BOOT0 pin is shared with PB9 GPIO pin. This pin is an input-only pin. If nBOOT_SEL
option bit is reset, sampling this pin on NRST rising edge gives the internal BOOT0 state.
This pin then works as PB9 pin. The input voltage characteristics of this pin are specific for
BOOT0 pin type (see Table 49: I/O static characteristics).

Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 26 edge detector lines used to generate
interrupt/event requests. Each line can be individually configured to select the trigger event

24/114 DocID027982 Rev 5

STM32L021x4 Functional overview

(rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 38 GPIOs can be connected
to the 16 configurable interrupt/event lines. The 10 other lines are connected to PVD, RTC,
USART, I2C, LPUART, LPTIM or comparator events.

3.8 Memories
The STM32L021x4 devices have the following features:
• 2 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states. With the enhanced bus matrix, operating the RAM does not lead to any
performance penalty during accesses to the system bus (AHB and APB buses).
• The non-volatile memory is divided into three arrays:
– 16 Kbytes of embedded Flash program memory
– 512 bytes of data EEPROM
– Information block containing 32 user and factory options bytes plus 4 Kbytes of
system memory
The user options bytes are used to write-protect or read-out protect the memory (with
4 Kbyte granularity) and/or readout-protect the whole memory with the following options:
• Level 0: no protection
• Level 1: memory readout protected.
The Flash memory cannot be read from or written to if either debug features are
connected or boot in RAM is selected
• Level 2: chip readout protected, debug features (Cortex-M0+ serial wire) and boot in
RAM selection disabled (debugline fuse)
The whole non-volatile memory embeds the error correction code (ECC) feature.

3.9 Direct memory access (DMA)

The flexible 5-channel, general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management, avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with software trigger
support for each channel. Configuration is done by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: AES, SPI, I2C, USART, LPUART,
general-purpose timers, and ADC.

DocID027982 Rev 5 25/114

32
Functional overview STM32L021x4

3.10 Analog-to-digital converter (ADC)

A native 12-bit, extended to 16-bit through hardware oversampling, analog-to-digital
converter is embedded into STM32L021x4 devices. It has up to 10 external channels and 2
internal channels (temperature sensor, voltage reference). Three channels, PA0, PA4 and
PA5, are fast channels, while the others are standard channels.
The ADC performs conversions in single-shot or scan mode. In scan mode, automatic
conversion is performed on a selected group of analog inputs.
The ADC frequency is independent from the CPU frequency, allowing maximum sampling
rate of 1.14 MSPS even with a low CPU speed. The ADC consumption is low at all
frequencies (~25 µA at 10 kSPS, ~200 µA at 1MSPS). An auto-shutdown function
guarantees that the ADC is powered off except during the active conversion phase.
The ADC can be served by the DMA controller. It can operate from a supply voltage down to
1.65 V.
The ADC features a hardware oversampler up to 256 samples, this improves the resolution
to 16 bits (see AN2668).
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all scanned channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start triggers, to allow the application to synchronize A/D conversions and timers.

3.11 Temperature sensor

The temperature sensor (TSENSE) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC_IN18 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode (see Table 56:
Temperature sensor calibration values).

3.11.1 Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and Comparators. VREFINT is internally connected to the ADC_IN17 input channel. It
enables accurate monitoring of the VDD value (since no external voltage, VREF+, is available
for ADC). The precise voltage of VREFINT is individually measured for each part by ST during
production test and stored in the system memory area (see Table 19: Embedded internal
reference voltage calibration values). It is accessible in read-only mode.

26/114 DocID027982 Rev 5

STM32L021x4 Functional overview

3.12 Ultra-low-power comparators and reference voltage

The STM32L021x4 embed two comparators sharing the same current bias and reference
voltage. The reference voltage can be internal or external (coming from an I/O).
• One comparator with ultra low consumption
• One comparator with rail-to-rail inputs, fast or slow mode.
• The threshold can be one of the following:
– External I/O pins
– Internal reference voltage (VREFINT)
– submultiple of Internal reference voltage(1/4, 1/2, 3/4) for the rail to rail
comparator.
Both comparators can wake up the devices from Stop mode, and be combined into a
window comparator.
The internal reference voltage is available externally via a low-power / low-current output
buffer (driving current capability of 1 µA typical).

3.13 System configuration controller

The system configuration controller provides the capability to remap some alternate
functions on different I/O ports.
The highly flexible routing interface allows the application firmware to control the routing of
different I/Os to the TIM2, TIM21 and LPTIM1 timer input captures. It also controls the
routing of internal analog signals to the ADC, COMP1 and COMP2 and the internal
reference voltage VREFINT.

3.14 AES
The AES Hardware Accelerator can be used to encrypt and decrypt data using the AES
algorithm (compatible with FIPS PUB 197, 2001 Nov 26):
• Key scheduler
• Key derivation for decryption
• 128-bit data block processed
• 128-bit key length
• 213 clock cycles to encrypt/decrypt one 128-bit block
• Electronic codebook (ECB), cypher block chaining (CBC), and counter mode (CTR)
supported by hardware.
The AES can be served by the DMA controller.

DocID027982 Rev 5 27/114

32
Functional overview STM32L021x4

3.15 Timers and watchdogs

The ultra-low-power STM32L021x4 devices include two general-purpose timers, one low-
power timer (LPTIM1), two watchdog timers and the SysTick timer.
Table 6 compares the features of the general-purpose and basic timers.

Table 6. Timer feature comparison

DMA
Counter Capture/compare Complementary
Timer Counter type Prescaler factor request
resolution channels outputs
generation

Up, down, Any integer between

TIM2 16-bit Yes 4 No
up/down 1 and 65536
Up, down, Any integer between
TIM21 16-bit No 2 No
up/down 1 and 65536

3.15.1 General-purpose timers (TIM2, TIM21)

There are three synchronizable general-purpose timers embedded in the STM32L021x4
devices (see Table 6 for differences).

TIM2
TIM2 is based on 16-bit auto-reload up/down counter. It includes a 16-bit prescaler. It
features four independent channels each for input capture/output compare, PWM or one-
pulse mode output.
The TIM2 general-purpose timers can work together or with the TIM21 general-purpose
timer via the Timer Link feature for synchronization or event chaining. Its counter can be
frozen in debug mode. Any of the general-purpose timers can be used to generate PWM
outputs.
TIM2 has independent DMA request generation.
This timer is capable of handling quadrature (incremental) encoder signals and the digital
outputs from 1 to 3 hall-effect sensors.

TIM21
TIM21 is based on a 16-bit auto-reload up/down counter. It includes a 16-bit prescaler. It has
two independent channels for input capture/output compare, PWM or one-pulse mode
output. It can work together and be synchronized with TIM2 full-featured general-purpose
timer.
It can also be used as simple timebase and be clocked by the LSE clock source
(32.768 kHz) to provide independent timebase from the main CPU clock.

28/114 DocID027982 Rev 5

STM32L021x4 Functional overview

3.15.2 Low-power Timer (LPTIM)

The low-power timer has an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
• 16-bit up counter with 16-bit autoreload register
• 16-bit compare register
• Configurable output: pulse, PWM
• Continuous / one shot mode
• Selectable software / hardware input trigger
• Selectable clock source
– Internal clock source: LSE, LSI, HSI or APB clock
– External clock source over LPTIM1 input (working even with no internal clock
source running, used by the Pulse Counter Application)
• Programmable digital glitch filter
• Encoder mode

3.15.3 SysTick timer

This timer is dedicated to the OS, but could also be used as a standard downcounter. It is
based on a 24-bit downcounter with autoreload capability and a programmable clock
source. It features a maskable system interrupt generation when the counter reaches ‘0’.

3.15.4 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 37 kHz internal RC and, as it operates independently of the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes. The counter
can be frozen in debug mode.

3.15.5 Window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.

DocID027982 Rev 5 29/114

32
Functional overview STM32L021x4

3.16 Communication interfaces

3.16.1 I2C bus

One I2C interface (I2C1) can operate in multimaster or slave modes. The I2C interface can
support Standard mode (Sm, up to 100 kbit/s), Fast mode (Fm, up to 400 kbit/s) and Fast
Mode Plus (Fm+, up to 1 Mbit/s) with 20 mA output drive on some I/Os.
The I2C interface supports 7-bit and 10-bit addressing modes, multiple 7-bit slave
addresses (2 addresses, 1 with configurable mask). They also include programmable
analog and digital noise filters.

Table 7. Comparison of I2C analog and digital filters

Analog filter Digital filter

Pulse width of Programmable length from 1 to 15

≥ 50 ns
suppressed spikes I2C peripheral clocks
1. Extra filtering capability vs.
Benefits Available in Stop mode standard requirements.
2. Stable length
Wakeup from Stop on address
Variations depending on
Drawbacks match is not available when digital
temperature, voltage, process
filter is enabled.

In addition, I2C1 provides hardware support for SMBus 2.0 and PMBus 1.1: ARP capability,
Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and
ALERT protocol management. I2C1 also has a clock domain independent from the CPU
clock, allowing the I2C1 to wake up the MCU from Stop mode on address match.
The I2C interface can be served by the DMA controller.
Refer to Table 8 for the supported modes and features of I2C interface.

Table 8. STM32L021x4 I2C implementation

I2C features(1) I2C1

7-bit addressing mode X

10-bit addressing mode X
Standard mode (up to 100 kbit/s) X
Fast mode (up to 400 kbit/s) X
Fast Mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X(2)
Independent clock X
SMBus X
Wakeup from STOP X
1. X = supported.
2. See Table 12: Pin definitions on page 36 for the list of I/Os that feature Fast Mode Plus capability

30/114 DocID027982 Rev 5

STM32L021x4 Functional overview

3.16.2 Universal synchronous/asynchronous receiver transmitter (USART)

The USART interface (USART2) is able to communicate at speeds of up to 4 Mbit/s.
It provides hardware management of the CTS, RTS and RS485 driver enable (DE) signals,
multiprocessor communication mode and single-wire half-duplex communication mode.
USART2 also supports Smartcard communication (ISO 7816, T=0 protocol) and IrDA SIR
ENDEC.
USART2 interface can be served by the DMA controller.
Table 9 for the supported modes and features of USART interface.

Table 9. USART implementation

USART modes/features(1) USART2

Hardware flow control for modem X

Continuous communication using DMA X
Multiprocessor communication X
Synchronous mode -
Smartcard mode X
Single-wire half-duplex communication X
IrDA SIR ENDEC block X
LIN mode -
Dual clock domain and wakeup from Stop mode -
Receiver timeout interrupt -
Modbus communication -
Auto baud rate detection (4 modes) -
Driver Enable X
1. X = supported.

3.16.3 Low-power universal asynchronous receiver transmitter (LPUART)

The devices embed one Low-power UART. The LPUART supports asynchronous serial
communication with minimum power consumption. It supports half duplex single wire
communication and modem operations (CTS/RTS). It allows multiprocessor
communication.
The LPUART has a clock domain independent from the CPU clock, and can wake up the
system from Stop mode, using baudrates up to 46 Kbaud. The Wakeup events from Stop
mode are programmable and can be:
• Start bit detection
• Or any received data frame
• Or a specific programmed data frame
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600
baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while
having an extremely low energy consumption. Higher speed clock can be used to reach
higher baudrates.
LPUART interface can be served by the DMA controller.

DocID027982 Rev 5 31/114

32
Functional overview STM32L021x4

3.16.4 Serial peripheral interface (SPI)

The SPI is able to communicate at up to 16 Mbits/s in slave and master modes in full-duplex
and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
The SPI can be served by the DMA controller.
Refer to Table 10 for the supported modes and features of SPI interface.

Table 10. SPI implementation

SPI features(1) SPI1

Hardware CRC calculation X

I2S mode -
TI mode X
1. X = supported.

3.17 Cyclic redundancy check (CRC) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at
linktime and stored at a given memory location.

3.18 Serial wire debug port (SW-DP)

An Arm SW-DP interface is provided to allow a serial wire debugging tool to be connected to
the MCU.

32/114 DocID027982 Rev 5

STM32L021x4 Pin descriptions

4 Pin descriptions

Figure 3. STM32L021x4 LQFP32 pinout

3%%227

3$
966

3%
3%
3%
3%
3%

9'' 3$
3&26&B,1 3$
3&26&B287 3$
1567 /4)3 3$
9''$ 3$
3$&.B,1 3$
3$ 3$
3$ 9''

3%
3%
966
3$
3$
3$
3$
3$

06Y9

1. The above figure shows the package top view.

Figure 4. STM32L021x4 UFQFPN32 pinout

3%%227

3$
3%
3%

3%
3%
3%
3%

9'' 3$
3&26&B,1 3$
3&26&B287 3$
1567 966 3$
9''$ 3$
3$&.B,1 3$
3$ 3$
3$ 9''
3%
3%
3%
3$
3$
3$
3$
3$

06Y9

1. The above figure shows the package top view.

DocID027982 Rev 5 33/114

42
Pin descriptions STM32L021x4

Figure 5. STM32L021x4 UFQFPN28 pinout

3$
3%
3%

3%

3%%227 3$
3&26&B,1 3$
3&26&B287 3$
1567 3$
9''$ 9''
3$&.B,1 966
3$ 3%

3%
3$

3$
06Y9

1. The above figure shows the package top view.

Figure 6. STM32L021x4 UFQFPN20 pinout

3%%227

3$
3%

3&26&B,1 3$

3&26&B287 3$

1567 9''

9''$ 966

3$&.B,1 3%

3$

06Y9

1. The above figure shows the package top view.

34/114 DocID027982 Rev 5

STM32L021x4 Pin descriptions

Figure 7. STM32L021x4 TSSOP20 pinout

3%%227 3$
3&26&B,1 3$
3&26&B287 3$
1567 3$
9''$ 9''
3$&.B,1 966
3$ 3%
3$ 3$
3$ 3$
3$ 3$

06Y9

1. The above figure shows the package top view.

Figure 8. STM32L021x4 TSSOP14 pinout

3%%227 3$
3&26&B,1 3$
3&26&B287 3$
1567 3$
3$&.B,1 9''
3$ 966
3$ 3$

06Y9

1. The above figure shows the package top view.

Table 11. Legend/abbreviations used in the pinout table

Name Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during
Pin name
and after reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input / output pin
FT 5 V tolerant I/O
FTf 5 V tolerant I/O, FM+ capable
TTa 3.3 V tolerant I/O directly connected to the ADC
I/O structure
TC Standard 3.3V I/O
B Dedicated BOOT0 pin
RST Bidirectional reset pin with embedded weak pull-up resistor

DocID027982 Rev 5 35/114

42
Pin descriptions STM32L021x4

Table 11. Legend/abbreviations used in the pinout table (continued)

Name Abbreviation Definition

Unless otherwise specified by a note, all I/Os are set as floating inputs during and
Notes
after reset.
Alternate
Functions selected through GPIOx_AFR registers
functions
Pin functions
Additional
Functions directly selected/enabled through peripheral registers
functions

Table 12. Pin definitions

Pin number Pin functions

I/O structure
Pin type
UFQFPN32(1)

PA0 USART2_RX LPTIM1_IN1 TIM2_CH1 - USART2_CTS TIM2_ETR LPUART1_RX COMP1_OUT

USART2_RTS_
PA1 EVENTOUT LPTIM1_IN2 TIM2_CH2 I2C1_SMBA TIM21_ETR LPUART1_TX -
DE
PA2 TIM21_CH1 - TIM2_CH3 - USART2_TX - LPUART1_TX COMP2_OUT
PA3 TIM21_CH2 - TIM2_CH4 - USART2_RX - LPUART1_RX -
DocID027982 Rev 5

PA4 SPI1_NSS LPTIM1_IN1 LPTIM1_ETR I2C1_SCL USART2_CK TIM2_ETR LPUART1_TX COMP2_OUT

PA5 SPI1_SCK LPTIM1_IN2 TIM2_ETR - - TIM2_CH1 - -
PA6 SPI1_MISO LPTIM1_ETR - - LPUART1_CTS - EVENTOUT COMP1_OUT
PA7 SPI1_MOSI LPTIM1_OUT - - USART2_CTS TIM21_ETR EVENTOUT COMP2_OUT
Port A
PA8 MCO - LPTIM1_IN1 EVENTOUT USART2_CK TIM2_CH1 - -
PA9 MCO I2C1_SCL LPTIM1_OUT - USART2_TX TIM21_CH2 - COMP1_OUT
PA10 TIM21_CH1 I2C1_SDA RTC_REFIN - USART2_RX TIM2_CH3 - COMP1_OUT
PA11 SPI1_MISO LPTIM1_OUT EVENTOUT - USART2_CTS TIM21_CH2 - COMP1_OUT
USART2_RTS_
PA12 SPI1_MOSI - EVENTOUT - - - COMP2_OUT
DE
PA13 SWDIO LPTIM1_ETR - I2C1_SDA - SPI1_SCK LPUART1_RX COMP1_OUT
PA14 SWCLK LPTIM1_OUT - I2C1_SMBA USART2_TX SPI1_MISO LPUART1_TX COMP2_OUT

Pin descriptions
PA15 SPI1_NSS - TIM2_ETR EVENTOUT USART2_RX TIM2_CH1 - -
41/114
Table 13. Alternate functions (continued)
42/114

Pin descriptions
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7

SPI1/USART2/ LPUART1/
Ports I2C1/USART2/L
TIM21/ SPI1/I2C1/ LPTIM/TIM2/ I2C1/LPTIM/ LPUART1/EVE
PUART1/ SPI1/TIM2/21 COMP1/2
EVENTOUT/ LPTIM EVENTOUT/ EVENTOUT VENTOUT
EVENTOUT
SYS_AF SYS_AF

USART2_RTS_
PB0 EVENTOUT SPI1_MISO TIM2_CH2 - TIM2_CH3 - -
DE
LPUART1_RTS_
PB1 USART2_CK SPI1_MOSI LPTIM1_IN1 - TIM2_CH4 - -
DE
PB2 - - LPTIM1_OUT - - - - -
PB3 SPI1_SCK - TIM2_CH2 - EVENTOUT - - -
Port B PB4 SPI1_MISO - EVENTOUT - - - - -
DocID027982 Rev 5

PB5 SPI1_MOSI - LPTIM1_IN1 I2C1_SMBA - TIM21_CH1 - -

PB6 USART2_TX I2C1_SCL LPTIM1_ETR - - TIM2_CH3 LPUART1_TX -
PB7 USART2_RX I2C1_SDA LPTIM1_IN2 - - TIM2_CH4 LPUART1_RX -
PB8 USART2_TX - EVENTOUT - I2C1_SCL SPI1_NSS - -
PB9 - - - - - - - -
PC14 - - - - - - - -
Port C
PC15 - - - - - - - -

STM32L021x4
STM32L021x4 Memory mapping

5 Memory mapping
Refer to the product line reference manual for details on the memory mapping as well as the
boundary addresses for all peripherals.

DocID027982 Rev 5 43/114

43
Electrical characteristics STM32L021x4

6 Electrical characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).

6.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.6 V (for the
1.65 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 9.

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 10.

Figure 9. Pin loading conditions Figure 10. Pin input voltage

0&8SLQ 0&8SLQ
& S)
9,1

DLF DLF

44/114 DocID027982 Rev 5

STM32L021x4 Electrical characteristics

6.1.6 Power supply scheme

Figure 11. Power supply scheme

6WDQGE\SRZHUFLUFXLWU\
26&57&:DNHXS
ORJLF57&EDFNXS
UHJLVWHUV

/HYHOVKLIWHU
287
,2
*3,2V /RJLF .HUQHOORJLF
,1
&38
'LJLWDO
9'' 0HPRULHV

9''
5HJXODWRU
1îQ)
î)
966
9''$
9''$

Q) $QDORJ
) 5&3//&203
$'&
«

966$

06Y9

1. On TSSOP14 package, VDDA is internally connected to VDD.

2. VSSA is internally connected to VSS on all packages.

6.1.7 Current consumption measurement

Figure 12. Current consumption measurement scheme

9''$
,''

1[9''

1îQ)
î)
1[966

06Y9

DocID027982 Rev 5 45/114

93
Electrical characteristics STM32L021x4

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 14: Voltage characteristics,
Table 15: Current characteristics, and Table 16: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability. Device mission profile (application conditions)
is compliant with JEDEC JESD47 Qualification Standard. Extended mission profiles are
available on demand.

Table 14. Voltage characteristics

Symbol Ratings Min Max Unit

External main supply voltage

VDD–VSS –0.3 4.0
(including VDDA, VDD)(1)
Input voltage on FT and FTf pins VSS −0.3 VDD+4.0
V
Input voltage on TC pins VSS −0.3 4.0
VIN(2)
Input voltage on BOOT0 VSS VDD + 4.0
Input voltage on any other pin VSS − 0.3 4.0
|ΔVDD| Variations between different VDDx power pins - 50
Variations between any VDDx and VDDA power mV
|VDDA-VDDx| - 300
pins(3)
|ΔVSS| Variations between all different ground pins - 50
Electrostatic discharge voltage
VESD(HBM) see Section 6.3.11
(human body model)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 15 for maximum allowed injected current values.
3. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV
between VDD and VDDA can be tolerated during power-up and device operation. its value does not need to
respect this rule.

46/114 DocID027982 Rev 5

STM32L021x4 Electrical characteristics

Table 15. Current characteristics

Symbol Ratings Max. Unit

ΣIVDD(2) Total current into sum of all VDD power lines (source)(1) 105
ΣIVSS(2) Total current out of sum of all VSS ground lines (sink) (1)
105
(1)
IVDD(PIN) Maximum current into each VDD power pin (source) 100
IVSS(PIN) Maximum current out of each VSS ground pin (sink)(1) 100
Output current sunk by any I/O and control pin except FTf
16
pins
IIO
Output current sunk by FTf pins 22
Output current sourced by any I/O and control pin -16
Total output current sunk by sum of all IOs and control
45 mA
pins(4)
ΣIIO(PIN)(3)
Total output current sourced by sum of all IOs and control
-45
pins
Total output current sunk by sum of all IOs and control
90
pins(2)
ΣIIO(PIN)
Total output current sourced by sum of all IOs and control
-90
pins(2)
Injected current on FT, FFf, RST and B pins -5/+0(5)
IINJ(PIN)
Injected current on TC pin ± 5(6)
ΣIINJ(PIN) Total injected current (sum of all I/O and control pins)(7) ± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
LQFP packages.
3. These values apply only to STM32L021GxUx part number (UFQFPN28 package).
4. This current consumption must be correctly distributed over all I/Os and control pins. In particular, it must
be located the closest possible to the couple of supply and ground, and distributed on both sides.
5. Positive current injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN)
must never be exceeded. Refer to Table 14 for maximum allowed input voltage values.
6. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. IINJ(PIN)
must never be exceeded. Refer to Table 14: Voltage characteristics for the maximum allowed input voltage
values.
7. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).

Table 16. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range –65 to +150 °C

TJ Maximum junction temperature 150 °C

DocID027982 Rev 5 47/114

93
Electrical characteristics STM32L021x4

6.3 Operating conditions

6.3.1 General operating conditions

Table 17. General operating conditions

Symbol Parameter Conditions Min Max Unit

fHCLK Internal AHB clock frequency - 0 32

fPCLK1 Internal APB1 clock frequency - 0 32 MHz
fPCLK2 Internal APB2 clock frequency - 0 32
BOR detector disabled 1.65 3.6
BOR detector enabled,
1.8 3.6
VDD Standard operating voltage at power on V
BOR detector disabled,
1.65 3.6
after power on
Analog operating voltage Must be the same voltage
VDDA 1.65 3.6 V
(all features) as VDD(1)
2.0 V ≤ VDD ≤3.6 V -0.3 5.5
Input voltage on FT, FTf and RST pins(2)
1.65 V ≤ VDD ≤2.0 V -0.3 5.2
VIN V
Input voltage on BOOT0 pin - 0 5.5
Input voltage on TC pin - -0.3 VDD+0.3
LQFP32 package - 333
UFQFPN32 package - 513

Power dissipation at TA = 85 °C (range 6) UFQFPN28 package - 206

or TA =105 °C (rage 7) (3) TSSOP20 package - 270
UFQFPN20 package - 196
TSSOP14 package - 210
PD mW
LQFP32 package - 83
UFQFPN32 package - 128

Power dissipation at TA = 125 °C (range UFQFPN28 package - 52

3) (3) TSSOP20 package - 67
UFQFPN20 package - 49
TSSOP14 package - 53

48/114 DocID027982 Rev 5

STM32L021x4 Electrical characteristics

Table 17. General operating conditions (continued)

Symbol Parameter Conditions Min Max Unit

Maximum power
–40 85
dissipation (range 6)
Maximum power
TA Temperature range –40 105
dissipation (range 7)
Maximum power °C
–40 125
dissipation (range 3)
Junction temperature range (range 6) -40 °C ≤ TA ≤ 85 ° –40 105
TJ Junction temperature range (range 7) -40 °C ≤ TA ≤ 105 °C –40 125
Junction temperature range (range 3) -40 °C ≤ TA ≤ 125 °C –40 130
1. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
VDDA can be tolerated during power-up and normal operation.
2. To sustain a voltage higher than VDD+0.3V, the internal pull-up/pull-down resistors must be disabled.
3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 16: Thermal characteristics
on page 47).

6.3.2 Embedded reset and power control block characteristics

The parameters given in the following table are derived from the tests performed under the
ambient temperature condition summarized in Table 17.

Table 18. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit

BOR detector enabled 0 - ∞

VDD rise time rate
BOR detector disabled 0 - 1000
tVDD(1) µs/V
BOR detector enabled 20 - ∞
VDD fall time rate
BOR detector disabled 0 - 1000
VDD rising, BOR enabled - 2 3.3
TRSTTEMPO(1) Reset temporization ms
VDD rising, BOR disabled(2) 0.4 0.7 1.6

Power on/power down reset Falling edge 1 1.5 1.65

VPOR/PDR
threshold Rising edge 1.3 1.5 1.65
Falling edge 1.67 1.7 1.74
VBOR0 Brown-out reset threshold 0
Rising edge 1.69 1.76 1.8
V
Falling edge 1.87 1.93 1.97
VBOR1 Brown-out reset threshold 1
Rising edge 1.96 2.03 2.07
Falling edge 2.22 2.30 2.35
VBOR2 Brown-out reset threshold 2
Rising edge 2.31 2.41 2.44

DocID027982 Rev 5 49/114

93
Electrical characteristics STM32L021x4

Table 18. Embedded reset and power control block characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit

Falling edge 2.45 2.55 2.6

VBOR3 Brown-out reset threshold 3
Rising edge 2.54 2.66 2.7
Falling edge 2.68 2.8 2.85
VBOR4 Brown-out reset threshold 4
Rising edge 2.78 2.9 2.95

Programmable voltage detector Falling edge 1.8 1.85 1.88

VPVD0
threshold 0 Rising edge 1.88 1.94 1.99
Falling edge 1.98 2.04 2.09
VPVD1 PVD threshold 1
Rising edge 2.08 2.14 2.18
Falling edge 2.20 2.24 2.28
VPVD2 PVD threshold 2 V
Rising edge 2.28 2.34 2.38
Falling edge 2.39 2.44 2.48
VPVD3 PVD threshold 3
Rising edge 2.47 2.54 2.58
Falling edge 2.57 2.64 2.69
VPVD4 PVD threshold 4
Rising edge 2.68 2.74 2.79
Falling edge 2.77 2.83 2.88
VPVD5 PVD threshold 5
Rising edge 2.87 2.94 2.99
Falling edge 2.97 3.05 3.09
VPVD6 PVD threshold 6
Rising edge 3.08 3.15 3.20
BOR0 threshold - 40 -
Vhyst Hysteresis voltage All BOR and PVD thresholds mV
- 100 -
excepting BOR0
1. Guaranteed by characterization results, not tested in production.
2. Valid for device version without BOR at power up. Please see option "D" in Ordering information scheme for more details.

50/114 DocID027982 Rev 5

STM32L021x4 Electrical characteristics

6.3.3 Embedded internal reference voltage

The parameters given in Table 20 are based on characterization results, unless otherwise
specified.

Table 19. Embedded internal reference voltage calibration values

Calibration value name Description Memory address

Raw data acquired at

VREFINT_CAL temperature of 25°C 0x1FF8 0078 - 0x1FF8 0079
VDDA= 3 V

Table 20. Embedded internal reference voltage(1)

Symbol Parameter Conditions Min Typ Max Unit

VREFINT out (2)

Internal reference voltage – 40 °C < TJ < +125 °C 1.202 1.224 1.242 V
TVREFINT Internal reference startup time - - 2 3 ms
VDDA voltage during VREFINT
VVREF_MEAS - 2.99 3 3.01 V
factory measure
Including uncertainties
Accuracy of factory-measured
AVREF_MEAS due to ADC and VDDA - - ±5 mV
VREFINT value(3)
values
–40 °C < TJ < +125 °C - 25 100
TCoeff(4) Temperature coefficient ppm/°C
0 °C < TJ < +50 °C - - 20
ACoeff(4) Long-term stability 1000 hours, T= 25 °C - - 1000 ppm
VDDCoeff(4) Voltage coefficient 3.0 V < VDDA < 3.6 V - - 2000 ppm/V
ADC sampling time when
TS_vrefint(4)(5) reading the internal reference - 5 10 - µs
voltage
Startup time of reference
TADC_BUF(4) - - - 10 µs
voltage buffer for ADC
Consumption of reference
IBUF_ADC(4) - - 13.5 25 µA
voltage buffer for ADC
IVREF_OUT(4) VREF_OUT output current(6) - - - 1 µA
CVREF_OUT(4) VREF_OUT output load - - - 50 pF
Consumption of reference
ILPBUF(4) voltage buffer for VREF_OUT - - 730 1200 nA
and COMP
VREFINT_DIV1(4) 1/4 reference voltage - 24 25 26
%
VREFINT_DIV2(4) 1/2 reference voltage - 49 50 51
VREFINT
VREFINT_DIV3(4) 3/4 reference voltage - 74 75 76
1. Refer to Table 32: Peripheral current consumption in Stop and Standby mode for the value of the internal reference current
consumption (IREFINT).
2. Guaranteed by test in production.
3. The internal VREF value is individually measured in production and stored in dedicated EEPROM bytes.

DocID027982 Rev 5 51/114

93
Electrical characteristics STM32L021x4

4. Guaranteed by design, not tested in production.

5. Shortest sampling time can be determined in the application by multiple iterations.
6. To guarantee less than 1% VREF_OUT deviation.

6.3.4 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, temperature, I/O pin loading, device software configuration, operating
frequencies, I/O pin switching rate, program location in memory and executed binary code.
The current consumption is measured as described in Figure 12: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code if not specified
otherwise.
The current consumption values are derived from the tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 17: General operating
conditions unless otherwise specified.
The MCU is placed under the following conditions:
• All I/O pins are configured in analog input mode
• All peripherals are disabled except when explicitly mentioned
• The Flash memory access time and prefetch is adjusted depending on fHCLK frequency
and voltage range to provide the best CPU performance unless otherwise specified.
• When the peripherals are enabled fAPB1 = fAPB2 = fAPB
• When PLL is ON, the PLL inputs are equal to HSI = 16 MHz (if internal clock is used) or
HSE = 16 MHz (if HSE bypass mode is used)
• The HSE user clock is applied to CK_IN. It follows the characteristic specified in
Table 34: High-speed external user clock characteristics
• For maximum current consumption VDD = VDDA = 3.6 V is applied to all supply pins
• For typical current consumption VDD = VDDA = 3.0 V is applied to all supply pins if not
specified otherwise

52/114 DocID027982 Rev 5

STM32L021x4 Electrical characteristics

Table 21. Current consumption in Run mode, code with data processing running from Flash
Symbol Parameter Conditions fHCLK Typ Max(1) Unit

1 MHz 140 180

Range 3, VCORE=1.2 V
2 MHz 245 290 µA
VOS[1:0]=11
4 MHz 460 540
fHSE = fHCLK up to 4 MHz 0.56 0.65
16 MHz included, Range 2, VCORE=1.5 V,
8 MHz 1.1 1.3
fHSE = fHCLK/2 above VOS[1:0]=10,
16 MHz (PLL ON)(2) 16 MHz 2.1 2.4
Supply mA
IDD current in 8 MHz 1.3 1.6
(Run Run mode, Range 1, VCORE=1.8 V,
16 MHz 2.6 3
from code VOS[1:0]=01
Flash) executed 32 MHz 5.3 6.5
from Flash 65 kHz 34.5 54
Range 3, VCORE=1.2 V,
MSI clock 524 kHz 86 120 µA
VOS[1:0]=11
4.2 MHz 505 560
Range 2, VCORE=1.5 V,
16 MHz 2.2 2.6
VOS[1:0]=10,
HSI clock mA
Range 1, VCORE=1.8 V,
32 MHz 5.4 5.9
VOS[1:0]=01
1. Guaranteed by characterization results at 125 °C, not tested in production, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

Table 22. Current consumption in Run mode vs code type,

code with data processing running from Flash
Symbol Parameter Conditions fHCLK Typ Unit

Dhrystone 460
CoreMark 440
Range 3,
Fibonacci 330
VCORE=1.2 V, 4 MHz µA
VOS[1:0]=11 while(1) 305
Supply
IDD current in fHSE = fHCLK up to while(1), prefetch
320
(Run Run mode, 16 MHz included, OFF
from code fHSE = fHCLK/2 above Dhrystone 5.4
Flash) executed 16 MHz (PLL ON)(1)
from Flash CoreMark 4.9
Range 1,
Fibonacci 5
VOS[1:0]=01, 32 MHz mA
VCORE=1.8 V while(1) 4.35
while(1), prefetch
3.7
OFF
1. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

DocID027982 Rev 5 53/114

93
Electrical characteristics STM32L021x4

Figure 13. IDD vs VDD, at TA= 25 °C, Run mode, code running from
Flash memory, Range 2, 16 MHz HSE, 1WS

/;ŵͿ

Ϯ͘ϱ

ϭ͘ϱ

Ϭ͘ϱ

Ϭ s;sͿ
ϭ͘ϲ ϭ͘ϴ Ϯ Ϯ͘Ϯ Ϯ͘ϰ Ϯ͘ϲ Ϯ͘ϴ ϯ ϯ͘Ϯ ϯ͘ϰ ϯ͘ϲ
ŚƌǇƐƚŽŶĞϮ͘ϭ͕ϭt^͕dсϮϱΣ

06Y9

Figure 14. IDD vs VDD, at TA= 25 °C, Run mode, code running from
Flash memory, Range 2, HSI16, 1WS
/;ŵͿ

Ϯ͘ϱ

ϭ͘ϱ

Ϭ͘ϱ

Ϭ s;sͿ
ϭ͘ϲ ϭ͘ϴ Ϯ Ϯ͘Ϯ Ϯ͘ϰ Ϯ͘ϲ Ϯ͘ϴ ϯ ϯ͘Ϯ ϯ͘ϰ ϯ͘ϲ

ŚƌǇƐƚŽŶĞϮ͘ϭ͕ϭt^͕dсϮϱΣ
06Y9

54/114 DocID027982 Rev 5

STM32L021x4 Electrical characteristics

Table 23. Current consumption in Run mode, code with data processing running from RAM
Symbol Parameter Conditions fHCLK Typ Max(1) Unit

1 MHz 115 140

Range 3,
VCORE=1.2 V, 2 MHz 205 240 µA
VOS[1:0]=11
4 MHz 385 420
fHSE = fHCLK up to 16
4 MHz 0.48 0.55
MHz, included Range 2,
fHSE = fHCLK/2 above VCORE=1.5 ,V, 8 MHz 0.935 1.1
16 MHz VOS[1:0]=10
16 MHz 1.8 2
(PLL ON)(2) mA
8 MHz 1.1 1.4
Supply current in Range 1,
IDD (Run Run mode, code VCORE=1.8 V, 16 MHz 2.1 2.5
from executed from VOS[1:0]=01
32 MHz 4.5 4.9
RAM) RAM, Flash
switched OFF 65 kHz 22 38
Range 3,
MSI clock VCORE=1.2 V, 524 kHz 67 91 µA
VOS[1:0]=11
4.2 MHz 415 450
Range 2,
VCORE=1.5 V, 16 MHz 1.95 2.2
HSI16 clock source VOS[1:0]=10
mA
(16 MHz) Range 1,
VCORE=1.8 V, 32 MHz 4.7 5.2
VOS[1:0]=01
1. Guaranteed by characterization results at 125 °C, not tested in production, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

Table 24. Current consumption in Run mode vs code type,

code with data processing running from RAM(1)
Symbol Parameter Conditions fHCLK Typ Unit

Dhrystone 385
Range 3, CoreMark -(3)
VCORE=1.2 V, 4 MHz µA
Supply current in VOS[1:0]=11 Fibonacci 350
fHSE = fHCLK up to 16
IDD (Run Run mode, code while(1) 340
MHz, included,
from executed from
fHSE = fHCLK/2 above Dhrystone 4.5
RAM) RAM, Flash
16 MHz (PLL ON)(2)
switched OFF Range 1, CoreMark -(3)
VCORE=1.8 V, 32 MHz mA
VOS[1:0]=01 Fibonacci 4.2
while(1) 3
1. Guaranteed by characterization results, not tested in production, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
3. CoreMark code is unable to run from RAM since the RAM size is only 2 Kbytes.

DocID027982 Rev 5 55/114

93
Electrical characteristics STM32L021x4

Table 25. Current consumption in Sleep mode

Symbol Parameter Conditions fHCLK Typ Max(1) Unit

1 MHz 36.5 70
Range 3,
VCORE=1.2 V, 2 MHz 58 95
VOS[1:0]=11
4 MHz 100 150
fHSE = fHCLK up to
4 MHz 125 170
16 MHz included, Range 2,
fHSE = fHCLK/2 VCORE=1.5 V, 8 MHz 230 300
above 16 MHz VOS[1:0]=10
16 MHz 450 540
(PLL ON)(2)
8 MHz 275 350
Range 1,
Supply current VCORE=1.8 V, 16 MHz 555 650
in Sleep VOS[1:0]=01
mode, Flash 32 MHz 1350 1600
OFF 65 kHz 15.5 32
Range 3,
MSI clock VCORE=1.2 V, 524 kHz 26.5 55
VOS[1:0]=11
4.2 MHz 115 160
Range 2,
VCORE=1.5 V, 16 MHz 585 670
HSI16 clock source VOS[1:0]=10
(16 MHz) Range 1,
VCORE=1.8 V, 32 MHz 1500 1700
VOS[1:0]=01
IDD (Sleep) µA
1 MHz 49 88
Range 3,
VCORE=1.2 V, 2 MHz 69 120
VOS[1:0]=11
4 MHz 115 190
fHSE = fHCLK up to
4 MHz 135 200
16 MHz included, Range 2,
fHSE = fHCLK/2 CORE=1.5 V, 8 MHz 240 340
above 16 MHz (PLL VOS[1:0]=10
16 MHz 460 650
ON)(2)
8 MHz 290 400
Range 1,
Supply current VCORE=1.8 V, 16 MHz 565 750
in Sleep VOS[1:0]=01
mode, Flash 32 MHz 1350 1900
ON 65 kHz 26.5 46
Range 3,
MSI clock VCORE=1.2 V, 524 kHz 38.5 70
VOS[1:0]=11
4.2 MHz 125 190
Range 2,
VCORE=1.5 V, 16 MHz 600 760
HSI16 clock source VOS[1:0]=10
(16 MHz) Range 1,
VCORE=1.8 V, 32 MHz 1500 1850
VOS[1:0]=01
1. Guaranteed by characterization results at 125 °C, not tested in production, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

56/114 DocID027982 Rev 5

STM32L021x4 Electrical characteristics

Table 26. Current consumption in Low-power Run mode

Symbol Parameter Conditions Typ Max(1) Unit

TA = -40 °C to 25 °C 5.7 8.1

MSI clock, 65 kHz TA = 85 °C 6.5 9

fHCLK = 32 kHz TA = 105 °C 8 13

All TA = 125 °C 11.5 22

peripherals TA =-40 °C to 25 °C 8.7 11
OFF, code
executed MSI clock, 65 kHz TA = 85 °C 9.5 12
from RAM, fHCLK = 65 kHz TA = 105 °C 11 15
Flash
switched TA = 125 °C 15 24
OFF, VDD
from 1.65 V TA = -40 °C to 25 °C 17 19
to 3.6 V TA = 55 °C 17 19.5
MSI clock, 131 kHz
TA = 85 °C 17.5 20
fHCLK = 131 kHz
TA = 105 °C 19 22
Supply
IDD current in TA = 125 °C 22.5 31
µA
(LP Run) Low-power TA = -40 °C to 25 °C 18 22
run mode
MSI clock, 65 kHz TA = 85 °C 20 24
fHCLK = 32 kHz TA = 105 °C 22 27
TA = 125 °C 26.5 37
All TA = -40 °C to 25 °C 22 25
peripherals
OFF, code MSI clock, 65 kHz TA = 85 °C 24 27
executed fHCLK = 65 kHz TA = 105 °C 26 30
from Flash,
VDD from TA = 125 °C 30.5 39
1.65 V to
TA = -40 °C to 25 °C 32 34
3.6 V
TA = 55 °C 32.5 35
MSI clock, 131 kHz
TA = 85 °C 34 37
fHCLK = 131 kHz
TA = 105 °C 36 39
TA = 125 °C 40 47
1. Guaranteed by characterization results at 125 °C, not tested in production, unless otherwise specified.

DocID027982 Rev 5 57/114

93
Electrical characteristics STM32L021x4

Figure 15. IDD vs VDD, at TA= -40/25/55/ 85/105/125 °C, Low-power run mode,
code running from RAM, Range 3, MSI (Range 0) at 64 KHz, 0 WS

06Y9

Table 27. Current consumption in Low-power Sleep mode

Symbol Parameter Conditions Typ Max(1) Unit

MSI clock, 65 kHz

fHCLK = 32 kHz TA = -40 °C to 25 °C 2.5(2) -
Flash OFF
TA = -40 °C to 25 °C 13 19
MSI clock, 65 kHz TA = 85 °C 15.5 20
fHCLK = 32 kHz
Flash ON TA = 105 °C 17.5 22
TA = 125 °C 21 29
Supply TA = -40 °C to 25 °C 13.5 19
All peripherals
IDD current in
OFF, VDD from MSI clock, 65 kHz TA = 85 °C 16 20 µA
(LP Sleep) Low-power
1.65 V to 3.6 V fHCLK = 65 kHz,
sleep mode TA = 105 °C 18 22
Flash ON
TA = 125 °C 21.5 29
TA = -40 °C to 25 °C 15.5 21
T = 55 °C 17 22
MSI clock, 131 kHz A
fHCLK = 131 kHz, TA = 85 °C 18 23
Flash ON
TA = 105 °C 19.5 24
TA = 125 °C 23.5 31
1. Guaranteed by characterization results at 125 °C, not tested in production, unless otherwise specified.
2. As the CPU is in Sleep mode, the difference between the current consumption with Flash memory ON and OFF (nearly
12 µA) is the same whatever the clock frequency.

58/114 DocID027982 Rev 5

STM32L021x4 Electrical characteristics

Table 28. Typical and maximum current consumptions in Stop mode

Symbol Parameter Conditions Typ Max(1) Unit

TA = -40°C to 25°C 0.34 0.99

TA = 55°C 0.43 1.9
IDD (Stop) Supply current in Stop mode TA= 85°C 0.94 4.2 µA
TA = 105°C 2.0 9
TA = 125°C 4.9 19
1. Guaranteed by characterization results at 125 °C, not tested in production, unless otherwise specified.

Figure 16. IDD vs VDD, at TA= -40/25/55/ 85/105/125 °C, Stop mode with RTC enabled
and running on LSE Low drive

ϲ
ͲϰϬΣ
ϱ
ϮϱΣ
ϰ ϱϱΣ

ϯ ϴϱΣ
ϭϬϱΣ
Ϯ
ϭϮϱΣ
ϭ

Ϭ s;sͿ
ϭ͘ϲ ϭ͘ϴ Ϯ Ϯ͘Ϯ Ϯ͘ϰ Ϯ͘ϲ Ϯ͘ϴ ϯ ϯ͘Ϯ ϯ͘ϰ ϯ͘ϲ

06Y9

Figure 17. IDD vs VDD, at TA= -40/25/55/85/105/125 °C, Stop mode with RTC disabled,
all clocks OFF

ϱ
ͲϰϬΣ
ϰ
ϮϱΣ

ϯ ϱϱΣ
ϴϱΣ
Ϯ
ϭϬϱΣ

ϭ ϭϮϱΣ

Ϭ s;sͿ
ϭ͘ϲ ϭ͘ϴ Ϯ Ϯ͘Ϯ Ϯ͘ϰ Ϯ͘ϲ Ϯ͘ϴ ϯ ϯ͘Ϯ ϯ͘ϰ ϯ͘ϲ

06Y9

DocID027982 Rev 5 59/114

93
Electrical characteristics STM32L021x4

Table 29. Typical and maximum current consumptions in Standby mode

Symbol Parameter Conditions Typ Max(1) Unit

TA = -40 °C to 25 °C 0.8 1.6

TA = 55 °C 0.9 1.8
Independent watchdog
TA= 85 °C 1 2
and LSI enabled
TA = 105 °C 1.25 3

IDD Supply current in Standby TA = 125 °C 2 7

µA
(Standby) mode TA = -40 °C to 25 °C 0.23 0.6
TA = 55 °C 0.25 0.7
Independent watchdog
TA = 85 °C 0.36 1
and LSI OFF
TA = 105 °C 0.62 1.7
TA = 125 °C 1.35 5
1. Guaranteed by characterization results at 125 °C, not tested in production, unless otherwise specified

Table 30. Average current consumption during wakeup

Current
Symbol parameter System frequency consumption Unit
during wakeup

HSI 1
HSI/4 0,7
IDD (WU from Supply current during wakeup from
MSI 4,2 MHz 0,7
Stop) Stop mode
MSI 1,05 MHz 0,4
MSI 65 KHz 0,1
mA
IDD (Reset) Reset pin pulled down - 0,21

IDD (Power Up) BOR ON - 0,23

IDD (WU from With Fast wakeup set MSI 2,1 MHz 0,5
StandBy) With Fast wakeup disabled MSI 2,1 MHz 0,12

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in the following tables. The
MCU is placed under the following conditions:
• all I/O pins are in input mode with a static value at VDD or VSS (no load)
• all peripherals are disabled unless otherwise mentioned
• the given value is calculated by measuring the current consumption
– with all peripherals clocked OFF
– with only one peripheral clocked ON

60/114 DocID027982 Rev 5

STM32L021x4 Electrical characteristics

Table 31. Peripheral current consumption in run or Sleep mode(1)

Typical consumption, VDD = 3.0 V, TA = 25 °C

Peripheral Range 1, Range 2, Range 3, Low-power Unit

VCORE=1.8 V VCORE=1.5 V VCORE=1.2 V sleep and
VOS[1:0] = 01 VOS[1:0] = 10 VOS[1:0] = 11 run

WWDG 2.5 2 1.6 2

LPUART1 8.3 7.2 5.4 7.2
I2C1 11 8.2 6.8 8.9 µA/MHz
APB1
LPTIM1 14 11 8.7 11 (fHCLK)

TIM2 10.5 8.5 6.4 8.5

USART2 8.5 6.8 5.4 7.1
ADC1(2) 5.0 3.9 3.3 4
SPI1 4.5 3.5 2.9 3.6
TIM21 6.8 6.1 4.5 5.6 µA/MHz
APB2
(fHCLK)
DBGMCU 1.7 1.7 1.1 1.4
SYSCFG/
2.5 2.4 1.6 2.3
COMP
GPIOA 7.6 6.3 4.9 6.5
Cortex-
µA/MHz
M0+ core GPIOB 5.1 4.1 3.2 4
(fHCLK)
I/O port
GPIOC 1.1 0.7 0.6 0.8
CRC 1.5 1.1 1 1.2
FLASH(3) 10 8.5 7 8.5
AHB µA/MHz
AES 3.6 3.0 2.4 2.8
(fHCLK)
DMA1 5.3 4.2 3.5 4.8
All enabled 96 80 62 88
µA/MHz
PWR 2.1 1.9 1.4 1.8
(fHCLK)
1. Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock
enabled, in the following conditions: fHCLK = 32 MHz (range 1), fHCLK = 16 MHz (range 2), fHCLK = 4 MHz
(range 3), fHCLK = 64kHz (Low-power run/sleep), fAPB1 = fHCLK, fAPB2 = fHCLK, default prescaler value for
each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling. Not tested in production.
2. HSI oscillator is OFF for this measure.
3. These values correspond to the Flash memory dynamic current consumption. The Flash memory static
consumption (Flash memory ON) equals 12 µA and does not depend on the frequency.
The Flash memory consumption is already taken into account in all the supply current consumption tables
(Flash memory ON cases).

DocID027982 Rev 5 61/114

93
Electrical characteristics STM32L021x4

Table 32. Peripheral current consumption in Stop and Standby mode

Typical consumption, TA = 25 °C
Symbol Peripheral Unit
VDD=1.8 V VDD=3.0 V

IDD(PVD / BOR) - 0.6 1

IREFINT - 1.25 1.3
- LSE Low drive 0.11 0.16

- LPTIM1, Input 100 Hz 0.01 0.02

µA

- LPTIM1, Input 1 MHz 8 9

- LPUART1 0.025 0.027

- RTC 0.1 0.19

6.3.5 Wakeup time from low-power mode

The wakeup times given in the following table are measured with the MSI or HSI16 RC
oscillator. The clock source used to wake up the device depends on the current operating
mode:
• Sleep mode: the clock source is the clock that was set before entering Sleep mode
• Stop mode: the clock source is either the MSI oscillator in the range configured before
entering Stop mode, the HSI16 or HSI16/4.
• Standby mode: the clock source is the MSI oscillator running at 2.1 MHz
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 17.

Table 33. Low-power mode wakeup timings

Symbol Parameter Conditions Typ Max Unit

tWUSLEEP Wakeup from Sleep mode fHCLK = 32 MHz 7 8

fHCLK = 262 kHz
7 8 CPU
Wakeup from Low-power sleep mode, Flash enabled
tWUSLEEP_LP cycles
fHCLK = 262 kHz fHCLK = 262 kHz
9 10
Flash switched OFF

62/114 DocID027982 Rev 5

STM32L021x4 Electrical characteristics

Table 33. Low-power mode wakeup timings (continued)

Symbol Parameter Conditions Typ Max Unit

fHCLK = fMSI = 4.2 MHz 5.1 8

Wakeup from Stop mode, regulator in
fHCLK = fHSI = 16 MHz 5.1 7
Run mode
fHCLK = fHSI/4 = 4 MHz 8.1 11
fHCLK = fMSI = 4.2 MHz
5 8
Voltage range 1
fHCLK = fMSI = 4.2 MHz
5 8
Voltage range 2
fHCLK = fMSI = 4.2 MHz
5 8
Voltage range 3
fHCLK = fMSI = 2.1 MHz 7.4 13
Wakeup from Stop mode, regulator in
fHCLK = fMSI = 1.05 MHz 14 23
low-power mode
tWUSTOP fHCLK = fMSI = 524 kHz 28 38
fHCLK = fMSI = 262 kHz 51 65 µs
fHCLK = fMSI = 131 kHz 99 120
fHCLK = fMSI = 65 kHz 196 260
fHCLK = fHSI = 16 MHz 5.1 7
fHCLK = fHSI/4 = 4 MHz 8.2 11
Wakeup from Stop mode, regulator in
low-power mode, HSI kept running in fHCLK = fHSI = 16 MHz 3.25 -
Stop mode
fHCLK = fHSI = 16 MHz 4.9 7
Wakeup from Stop mode, regulator in
low-power mode, code running from fHCLK = fHSI/4 = 4 MHz 7.9 10
RAM
fHCLK = fMSI = 4.2 MHz 4.8 8
Wakeup from Standby mode
fHCLK = fMSI = 2.1 MHz 65 130
FWU bit = 1
tWUSTDBY
Wakeup from Standby mode
fHCLK = fMSI = 2.1 MHz 2.2 3 ms
FWU bit = 0

DocID027982 Rev 5 63/114

93
Electrical characteristics STM32L021x4

6.3.6 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the input pin is a standard [Link] external clock signal has to respect
the I/O characteristics in Section 6.3.12. However, the recommended clock input waveform
is shown in Figure 18.

Table 34. High-speed external user clock characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

CSS is ON or
1 8 32 MHz
User external clock source PLL is used
fHSE_ext
frequency CSS is OFF,
0 8 32 MHz
PLL not used
VHSEH CK_IN input pin high level voltage 0.7VDD - VDD
V
VHSEL CK_IN input pin low level voltage VSS - 0.3VDD
tw(HSE)
CK_IN high or low time 12 - -
tw(HSE)
- ns
tr(HSE)
CK_IN rise or fall time - - 20
tf(HSE)
Cin(HSE) CK_IN input capacitance - 2.6 - pF
DuCy(HSE) Duty cycle 45 - 55 %
IL CK_IN Input leakage current VSS ≤ VIN ≤ VDD - - ±1 µA
1. Guaranteed by design, not tested in production.

Figure 18. High-speed external clock source AC timing diagram

9+6(+

9+6(/
WU +6( W: +6( W
WI +6( W: +6(
7+6(

(;7(51$/ I+6(BH[W
&.B,1 ,/
&/2&. 6285&(
670/[[

06Y9

64/114 DocID027982 Rev 5

STM32L021x4 Electrical characteristics

Low-speed external user clock generated from an external source

The characteristics given in the following table result from tests performed using a low-
speed external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 17.

Table 35. Low-speed external user clock characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

User external clock source

fLSE_ext - 32.768 1000 kHz
frequency
OSC32_IN input pin high level
VLSEH 0.7VDD - VDD
voltage
V
OSC32_IN input pin low level
VLSEL - VSS - 0.3VDD
voltage
tw(LSE)
OSC32_IN high or low time 465 - -
tw(LSE)
ns
tr(LSE)
OSC32_IN rise or fall time - - 10
tf(LSE)
CIN(LSE) OSC32_IN input capacitance - - 0.6 - pF
DuCy(LSE) Duty cycle - 45 - 55 %
IL OSC32_IN Input leakage current VSS ≤ VIN ≤ VDD - - ±1 µA
1. Guaranteed by design, not tested in production

Figure 19. Low-speed external clock source AC timing diagram

9/6(+

9/6(/

WU /6( W: /6( W
WI /6( W: /6(
7/6(

(;7(5 1$/ I/6(BH[W

26&B,1 ,/
&/2&. 6285& (
670/[[

DLF

Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 36. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization

DocID027982 Rev 5 65/114

93
Electrical characteristics STM32L021x4

time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).

Table 36. LSE oscillator characteristics(1)

Symbol Parameter Conditions(2) Min(2) Typ Max Unit

fLSE LSE oscillator frequency - 32.768 - kHz

LSEDRV[1:0]=00
- - 0.5
lower driving capability
LSEDRV[1:0]= 01
- - 0.75
Maximum critical crystal medium low driving capability
Gm µA/V
transconductance LSEDRV[1:0] = 10
- - 1.7
medium high driving capability
LSEDRV[1:0]=11
- - 2.7
higher driving capability
tSU(LSE)(3) Startup time VDD is stabilized - 2 - s
1. Guaranteed by design, not tested in production.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST
microcontrollers”.
3. Guaranteed by characterization results, not tested in production. tSU(LSE) is the startup time measured from the moment it is
enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal
resonator and it can vary significantly with the crystal manufacturer. To increase speed, address a lower-drive quartz with a
high- driver mode.

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website [Link]

Figure 20. Typical application with a 32.768 kHz crystal

5HVRQDWRUZLWKLQWHJUDWHG
FDSDFLWRUV
&/

26&B,1 I/6(

N+] 'ULYH
UHVRQDWRU SURJUDPPDEOH
DPSOLILHU

26&B287
&/

069

Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.

66/114 DocID027982 Rev 5

STM32L021x4 Electrical characteristics

6.3.7 Internal clock source characteristics

The parameters given in Table 37 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 17.

High-speed internal 16 MHz (HSI16) RC oscillator

Table 37. 16 MHz HSI16 oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

fHSI16 Frequency VDD = 3.0 V - 16 - MHz

HSI16 user- Trimming code is not a multiple of 16 - ± 0.4 0.7 %

(1)(2)
TRIM trimmed resolution Trimming code is a multiple of 16 - - ± 1.5 %
VDDA = 3.0 V, TA = 25 °C -1(3) - 1(3) %
VDDA = 3.0 V, TA = 0 to 55 °C -1.5 - 1.5 %

Accuracy of the VDDA = 3.0 V, TA = -10 to 70 °C -2 - 2 %

ACCHSI16
(2) factory-calibrated VDDA = 3.0 V, TA = -10 to 85 °C -2.5 - 2 %
HSI16 oscillator
VDDA = 3.0 V, TA = -10 to 105 °C -4 - 2 %
VDDA = 1.65 V to 3.6 V
-5.45 - 3.25 %
TA = -40 to 125 °C
HSI16 oscillator
tSU(HSI16)(2) - - 3.7 6 µs
startup time
HSI16 oscillator
IDD(HSI16)(2) - - 100 140 µA
power consumption
1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are
multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0).
2. Guaranteed by characterization results, not tested in production.
3. Guaranteed by test in production.

Figure 21. HSI16 minimum and maximum value versus temperature

9PLQ

9W\S

9PD[
9PD[

9PLQ

06Y9

DocID027982 Rev 5 67/114

93
Electrical characteristics STM32L021x4

Low-speed internal (LSI) RC oscillator

Table 38. LSI oscillator characteristics

Symbol Parameter Min Typ Max Unit

fLSI(1) LSI frequency 26 38 56 kHz

LSI oscillator frequency drift
DLSI(2) -10 - 4 %
0°C ≤ TA ≤ 85°C
tsu(LSI)(3) LSI oscillator startup time - - 200 µs
(3)
IDD(LSI) LSI oscillator power consumption - 400 510 nA
1. Guaranteed by test in production.
2. This is a deviation for an individual part, once the initial frequency has been measured.
3. Guaranteed by design, not tested in production.

Multi-speed internal (MSI) RC oscillator

Table 39. MSI oscillator characteristics

Symbol Parameter Condition Typ Max Unit

MSI range 0 65.5 -

MSI range 1 131 -
kHz
MSI range 2 262 -
Frequency after factory calibration, done at
fMSI MSI range 3 524 -
VDD= 3.3 V and TA = 25 °C
MSI range 4 1.05 -
MSI range 5 2.1 - MHz
MSI range 6 4.2 -
ACCMSI Frequency error after factory calibration - ± 0.5 - %
MSI oscillator frequency drift
DTEMP(MSI)(1) - ±3 - %
0 °C ≤ TA ≤ 85 °C
MSI oscillator frequency drift
DVOLT(MSI)(1) - - 2.5 %/V
1.65 V ≤ VDD ≤ 3.6 V, TA = 25 °C
MSI range 0 0.75 -
MSI range 1 1 -
MSI range 2 1.5 -
IDD(MSI)(2) MSI oscillator power consumption MSI range 3 2.5 - µA
MSI range 4 4.5 -
MSI range 5 8 -
MSI range 6 15 -

68/114 DocID027982 Rev 5

STM32L021x4 Electrical characteristics

Table 39. MSI oscillator characteristics (continued)

Symbol Parameter Condition Typ Max Unit

MSI range 0 30 -
MSI range 1 20 -
MSI range 2 15 -
MSI range 3 10 -
MSI range 4 6 -
tSU(MSI) MSI oscillator startup time µs
MSI range 5 5 -
MSI range 6,
Voltage range 1 3.5 -
and 2
MSI range 6,
5 -
Voltage range 3
MSI range 0 - 40
MSI range 1 - 20
MSI range 2 - 10
MSI range 3 - 4
MSI range 4 - 2.5
tSTAB(MSI)(2) MSI oscillator stabilization time µs
MSI range 5 - 2
MSI range 6,
Voltage range 1 - 2
and 2
MSI range 3,
- 3
Voltage range 3
Any range to
- 4
range 5
fOVER(MSI) MSI oscillator frequency overshoot MHz
Any range to
- 6
range 6
1. This is a deviation for an individual part, once the initial frequency has been measured.
2. Guaranteed by characterization results, not tested in production.

6.3.8 PLL characteristics

The parameters given in Table 40 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 17.

Table 40. PLL characteristics

Value
Symbol Parameter Unit
Min Typ Max(1)

PLL input clock(2) 2 - 24 MHz

fPLL_IN
PLL input clock duty cycle 45 - 55 %

DocID027982 Rev 5 69/114

93
Electrical characteristics STM32L021x4

Table 40. PLL characteristics (continued)

Value
Symbol Parameter Unit
Min Typ Max(1)

fPLL_OUT PLL output clock 2 - 32 MHz

PLL input = 16 MHz
tLOCK - 115 160 µs
PLL VCO = 96 MHz
Jitter Cycle-to-cycle jitter - ± 600 ps
IDDA(PLL) Current consumption on VDDA - 220 450
µA
IDD(PLL) Current consumption on VDD - 120 150
1. Guaranteed by characterization results, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.

6.3.9 Memory characteristics

RAM memory

Table 41. RAM and hardware registers

Symbol Parameter Conditions Min Typ Max Unit

VRM Data retention mode(1) STOP mode (or RESET) 1.65 - - V

1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware
registers (only in Stop mode).

70/114 DocID027982 Rev 5

STM32L021x4 Electrical characteristics

Flash memory and data EEPROM

Table 42. Flash memory and data EEPROM characteristics

Symbol Parameter Conditions Min Typ Max(1) Unit

Operating voltage
VDD - 1.65 - 3.6 V
Read / Write / Erase

Programming time for Erasing - 3.28 3.94

tprog ms
word or half-page Programming - 3.28 3.94
Average current during
the whole programming / - 500 700 µA
erase operation
IDD Maximum current (peak) TA = 25 °C, VDD = 3.6 V
during the whole
- 1.5 2.5 mA
programming / erase
operation
1. Guaranteed by design, not tested in production.

Table 43. Flash memory and data EEPROM endurance and retention
Value
Symbol Parameter Conditions Unit
Min(1)

Cycling (erase / write)

10
Program memory
TA = -40°C to 105 °C
Cycling (erase / write)
100
EEPROM data memory
NCYC(2) kcycles
Cycling (erase / write)
0.2
Program memory
TA = -40°C to 125 °C
Cycling (erase / write)
2
EEPROM data memory
Data retention (program memory) after
30
10 kcycles at TA = 85 °C
TRET = +85 °C
Data retention (EEPROM data memory)
30
after 100 kcycles at TA = 85 °C
Data retention (program memory) after
10 kcycles at TA = 105 °C
tRET(2) TRET = +105 °C years
Data retention (EEPROM data memory)
after 100 kcycles at TA = 105 °C
10
Data retention (program memory) after
200 cycles at TA = 125 °C
TRET = +125 °C
Data retention (EEPROM data memory)
after 2 kcycles at TA = 125 °C
1. Guaranteed by characterization results, not tested in production.
2. Characterization is done according to JEDEC JESD22-A117.

DocID027982 Rev 5 71/114

93
Electrical characteristics STM32L021x4

6.3.10 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 44. They are based on the EMS levels and classes
defined in application note AN1709.

Table 44. EMS characteristics

Level/
Symbol Parameter Conditions
Class

VDD = 3.3 V, LQFP32, TA = +25 °C,

Voltage limits to be applied on any I/O pin to
VFESD fHCLK = 32 MHz 3B
induce a functional disturbance
conforms to IEC 61000-4-2
Fast transient voltage burst limits to be VDD = 3.3 V, LQFP32, TA = +25 °C,
VEFTB applied through 100 pF on VDD and VSS fHCLK = 32 MHz 4A
pins to induce a functional disturbance conforms to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1
second.

72/114 DocID027982 Rev 5

STM32L021x4 Electrical characteristics

To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.

Table 45. EMI characteristics

Monitored Max vs. frequency range
Symbol Parameter Conditions Unit
frequency band (32 MHz voltage Range 1)

VDD = 3.3 V, 0.1 to 30 MHz -22

TA = 25 °C, 30 to 130 MHz -7 dBµV
SEMI Peak level LQFP32 package
compliant with IEC 130 MHz to 1GHz -12
61967-2 SAE EMI Level 1 -

6.3.11 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.

Table 46. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Class Unit
value(1)

TA = +25 °C,
Electrostatic discharge
VESD(HBM) conforming to 2 2000
voltage (human body model)
ANSI/JEDEC JS-001
V
Electrostatic discharge TA = +25 °C,
VESD(CDM) voltage (charge device conforming to C4 500
model) ANSI/ESD STM5.3.1.
1. Guaranteed by characterization results, not tested in production.

Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.

DocID027982 Rev 5 73/114

93
Electrical characteristics STM32L021x4

Table 47. Electrical sensitivities

Symbol Parameter Conditions Class

LU Static latch-up class TA = +125 °C conforming to JESD78A II level A

6.3.12 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard pins) should be avoided during normal product operation.
However, in order to give an indication of the robustness of the microcontroller in cases
when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset occurrence oscillator
frequency deviation).
The test results are given in the Table 48.

Table 48. I/O current injection susceptibility

Functional susceptibility
Symbol Description Unit
Negative Positive
injection injection

Injected current on BOOT0 -0 NA(1)

IINJ Injected current on all FT pins -5 (2) NA(1) mA
(2)
Injected current on any other pin -5 +5
1. Current injection is not possible.
2. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject
negative currents.

74/114 DocID027982 Rev 5

STM32L021x4 Electrical characteristics

6.3.13 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 49 are derived from tests
performed under the conditions summarized in Table 17. All I/Os are CMOS and TTL
compliant.
Table 49. I/O static characteristics
Symbol Parameter Conditions Min Typ Max Unit

TC, FT, FTf, RST

- - 0.3VDD
VIL Input low level voltage I/Os
BOOT0 pin - - 0.14VDD(1)
All I/Os except
0.7 VDD - -
BOOT0 pin V
VIH Input high level voltage
0.15
BOOT0 pin - -
VDD+0.56(1)

I/O Schmitt trigger voltage hysteresis Standard I/Os - 10% VDD(3) -

Vhys (2)
BOOT0 pin - 0.01 -
VSS ≤ VIN ≤ VDD
All I/Os except
- - ±50 nA
BOOT0 and FTf
I/Os
BOOT0(5)
- +2 -
VIN = VDD
µA
BOOT0
Ilkg Input leakage current (4) - 0 -
VIN = VSS
VDD ≤ VIN ≤ 5 V
- - 200
FT I/Os
nA
VDD ≤ VIN ≤ 5 V
- - 500
FTf I/Os
VDD ≤ VIN ≤ 5 V
- - 10 µA
BOOT0
RPU Weak pull-up equivalent resistor(6) VIN = VSS 25 45 65 kΩ
RPD Weak pull-down equivalent resistor(6) VIN = VDD 25 45 65 kΩ
CIO I/O pin capacitance - - 5 - pF
1. Guaranteed by characterization, not tested in production
2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results, not tested in production.
3. With a minimum of 200 mV. Guaranteed by characterization results, not tested in production.
4. The max. value may be exceeded if negative current is injected on adjacent pins.
5. BOOT0/PB9 pin limitation: typical input leakage current = 2 µA and input frequency limited to 10 kHz (1.65 V < VDD < 2.7 V)
and 5 MHz (2.7 V < VDD < 3.6 V).
6. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).

DocID027982 Rev 5 75/114

93
Electrical characteristics STM32L021x4

Figure 22. VIH/VIL versus VDD (CMOS I/Os)

9,/9,+ 9 LQV
9 '
'
DOOS

WV9 ,+PLQ
9 '' 3+
LUHPHQ 3&
UHTX 9 ,+PLQ W%227 IRU
DUG S
6V WDQG H[FH 9 '' +
&02 3
9,+PLQ 9 ,+PLQ 3&
7
%22

9 '
'

9 ,/PD[
,QSXWUDQJHQRW
JXDUDQWHHG
&026VWDQGDUGUHTXLUHPHQWV9,/PD[ 9''
9,/PD[

9'' 9

06Y9

Figure 23. VIH/VIL versus VDD (TTL I/Os)

9,/9,+ 9 SLQV

DOO
9 ' 3+

'
3&
9 ,+PLQ W%227 IRU
S
77/VWDQGDUGUHTXLUHPHQWV9,+PLQ 9 H[FH 9 '' 3+

9,+PLQ 9 ,+P 3&
LQ
7
%22

9 '
'

9 ,/PD[
,QSXWUDQJHQRW
JXDUDQWHHG

9,/PD[
77/VWDQGDUGUHTXLUHPHQWV9,/PD[ 9
9'' 9

06Y9

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±15 mA with the non-standard VOL/VOH specifications given in Table 50.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD(Σ) (see Table 15).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS(Σ) (see Table 15).

76/114 DocID027982 Rev 5

STM32L021x4 Electrical characteristics

Output voltage levels

Unless otherwise specified, the parameters given in Table 50 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 17. All I/Os are CMOS and TTL compliant.

Table 50. Output voltage characteristics

Symbol Parameter Conditions Min Max Unit

Output low level voltage for an I/O

VOL(1) CMOS port(2), - 0.4
pin
IIO = +8 mA
Output high level voltage for an I/O 2.7 V ≤ VDD ≤ 3.6 V
VOH(3) VDD-0.4 -
pin
TTL port(2),
(1) Output low level voltage for an I/O
VOL IIO =+ 8 mA - 0.4
pin
2.7 V ≤ VDD ≤ 3.6 V
TTL port(2),
(3)(4) Output high level voltage for an I/O
VOH IIO = -6 mA 2.4 -
pin
2.7 V ≤ VDD ≤ 3.6 V
Output low level voltage for an I/O IIO = +15 mA
VOL(1)(4) - 1.3 V
pin 2.7 V ≤ VDD ≤ 3.6 V
Output high level voltage for an I/O IIO = -15 mA
VOH(3)(4) VDD-1.3 -
pin 2.7 V ≤ VDD ≤ 3.6 V
Output low level voltage for an I/O IIO = +4 mA
VOL(1)(4) - 0.45
pin 1.65 V ≤ VDD < 3.6 V
Output high level voltage for an I/O IIO = -4 mA
VOH(3)(4) V -0.45 -
pin 1.65 V ≤ VDD ≤ 3.6 V DD
IIO = 20 mA
- 0.4
Output low level voltage for an FTf 2.7 V ≤ VDD ≤ 3.6 V
VOLFM+(1)(4)
I/O pin in Fm+ mode IIO = 10 mA
- 0.4
1.65 V ≤ VDD ≤ 3.6 V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 15.
The sum of the currents sunk by all the I/Os (I/O ports and control pins) must always be respected and
must not exceed ΣIIO(PIN).
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 15. The sum of the currents sourced by all the I/Os (I/O ports and control pins) must always be
respected and must not exceed ΣIIO(PIN).
4. Guaranteed by characterization results, not tested in production.

DocID027982 Rev 5 77/114

93
Electrical characteristics STM32L021x4

Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 24 and
Table 51, respectively.
Unless otherwise specified, the parameters given in Table 51 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 17.

Table 51. I/O AC characteristics(1)(2)

OSPEEDRx
[1:0] bit Symbol Parameter Conditions Min Max(3) Unit
value(1)

CL = 50 pF, VDD = 2.7 V to 3.6 V - 400

fmax(IO)out Maximum frequency(4) kHz
CL = 50 pF, VDD = 1.65 V to 2.7 V - 100
00
tf(IO)out CL = 50 pF, VDD = 2.7 V to 3.6 V - 125
Output rise and fall time ns
tr(IO)out CL = 50 pF, VDD = 1.65 V to 2.7 V - 320
CL = 50 pF, VDD = 2.7 V to 3.6 V - 2
fmax(IO)out Maximum frequency(4) MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V - 0.6
01
tf(IO)out CL = 50 pF, VDD = 2.7 V to 3.6 V - 30
Output rise and fall time ns
tr(IO)out CL = 50 pF, VDD = 1.65 V to 2.7 V - 65
CL = 50 pF, VDD = 2.7 V to 3.6 V - 10
Fmax(IO)out Maximum frequency(4) MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V - 2
10
tf(IO)out CL = 50 pF, VDD = 2.7 V to 3.6 V - 13
Output rise and fall time ns
tr(IO)out CL = 50 pF, VDD = 1.65 V to 2.7 V - 28
CL = 30 pF, VDD = 2.7 V to 3.6 V - 35
Fmax(IO)out Maximum frequency(4) MHz
CL = 50 pF, VDD = 1.65 V to 2.7 V - 10
11
tf(IO)out CL = 30 pF, VDD = 2.7 V to 3.6 V - 6
Output rise and fall time ns
tr(IO)out CL = 50 pF, VDD = 1.65 V to 2.7 V - 17
Pulse width of external
- tEXTIpw signals detected by the - 8 - ns
EXTI controller
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the line reference manual for a description of GPIO
Port configuration register.
2. BOOT0/PB9 maximum input frequency is 10 kHz (1.65 V < VDD < 2.7 V) and 5 MHz (2.7 V < VDD < 3.6 V).
3. Guaranteed by design. Not tested in production.
4. The maximum frequency is defined in Figure 24.

78/114 DocID027982 Rev 5

STM32L021x4 Electrical characteristics

Figure 24. I/O AC characteristics definition

(;7(51$/ WU ,2 RXW WI ,2 RXW

287387
21&/ 7

0D[LPXPIUHTXHQF\LVDFKLHYHGLI WUWI 7DQGLIWKHGXW\F\FOHLV

ZKHQORDGHGE\&/VSHFLILHGLQWKHWDEOH³,2$&FKDUDFWHULVWLFV´

DLG

6.3.14 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU , except when it is internally driven low (see Table 52).
Unless otherwise specified, the parameters given in Table 52 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 17.

Table 52. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIL(NRST)(1) NRST input low level voltage - - - 0.3VDD

0.39VDD+
VIH(NRST)(1) NRST input high level voltage - - -
0.59
IOL = 2 mA V
- -
2.7 V < VDD < 3.6 V
VOL(NRST)(1) NRST output low level voltage 0.4
IOL = 1.5 mA
- -
1.65 V < VDD < 2.7 V
NRST Schmitt trigger voltage
Vhys(NRST)(1) - - 10%VDD(2) - mV
hysteresis
Weak pull-up equivalent
RPU VIN = VSS 25 45 65 kΩ
resistor(3)
VF(NRST)(1) NRST input filtered pulse - - - 50 ns
VNF(NRST)(1) NRST input not filtered pulse - 350 - - ns
1. Guaranteed by design, not tested in production.
2. 200 mV minimum value
3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is around 10%.

DocID027982 Rev 5 79/114

93
Electrical characteristics STM32L021x4

Figure 25. Recommended NRST pin protection

9''
([WHUQDOUHVHWFLUFXLW

538 ,QWHUQDOUHVHW
1567
)LOWHU
)

670/[[

DLF

1. The reset network protects the device against parasitic resets.

2. The external capacitor must be placed as close as possible to the device.
3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 52. Otherwise the reset will not be taken into account by the device.

6.3.15 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 53 are values derived from tests
performed under ambient temperature, fPCLK frequency and VDDA supply voltage conditions
summarized in Table 17: General operating conditions.
Note: It is recommended to perform a calibration after each power-up.

Table 53. ADC characteristics

Symbol Parameter Conditions Min Typ Max Unit

Analog supply voltage for Fast channel 1.65 - 3.6

VDDA V
ADC ON Standard channels 1.75(1) - 3.6

Current consumption of the 1.14 Msps - 200 -

ADC on VDDA 10 ksps - 40 -
IDDA (ADC) µA
Current consumption of the 1.14 Msps - 70 -
ADC on VDD(2) 10 ksps - 1 -
Voltage scaling Range 1 0.14 - 16
fADC ADC clock frequency Voltage scaling Range 2 0.14 - 8 MHz
Voltage scaling Range 3 0.14 - 4
fS(3) Sampling rate - 0.05 - 1.14 MHz
fADC = 16 MHz,
- - 941 kHz
fTRIG(3) External trigger frequency 16-bit resolution
- - - 17 1/fADC
VAIN Conversion voltage range - 0 - VDDA V
See Equation 1 and
RAIN(3) External input impedance - - 50 kΩ
Table 54 for details

RADC(3)(4) Sampling switch resistance - - - 1 kΩ

80/114 DocID027982 Rev 5

STM32L021x4 Electrical characteristics

Table 53. ADC characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

Internal sample and hold

CADC(3) - - - 8 pF
capacitor
fADC = 16 MHz 5.2 µs
tCAL(3) Calibration time
- 83 1/fADC
1.5 ADC 1.5 ADC
ADC clock = HSI16 cycles + 2 - cycles + 3 -
fPCLK cycles fPCLK cycles
ADC_DR register write fPCLK
WLATENCY
latency ADC clock = PCLK/2 - 4.5 -
cycle
fPCLK
ADC clock = PCLK/4 - 8.5 -
cycle
fADC = fPCLK/2 = 16 MHz 0.266 µs
fADC = fPCLK/2 8.5 1/fPCLK
tlatr(3) Trigger conversion latency fADC = fPCLK/4 = 8 MHz 0.516 µs
fADC = fPCLK/4 16.5 1/fPCLK
fADC = fHSI16 = 16 MHz 0.252 - 0.260 µs
ADC jitter on trigger
JitterADC fADC = fHSI16 - 1 - 1/fHSI16
conversion
fADC = 16 MHz 0.093 - 10.03 µs
tS(3) Sampling time
- 1.5 - 239.5 1/fADC
tSTAB(3) Power-up time - 0 0 1 µs
fADC = 16 MHz 0.875 10.81 µs
(3) Total conversion time
tConV 14 to 173 (tS for sampling +12.5 for
(including sampling time) - 1/fADC
successive approximation)
1. VDDA minimum value can be decreased in specific temperature conditions. Refer to Table 54: RAIN max for fADC = 16
MHz.
2. A current consumption proportional to the APB clock frequency has to be added (see Table 31: Peripheral current
consumption in run or Sleep mode).
3. Guaranteed by design, not tested in production.
4. Standard channels have an extra protection resistance which depends on supply voltage. Refer to Table 54: RAIN max for
fADC = 16 MHz.

Equation 1: RAIN max formula

TS
R AIN < ---------------------------------------------------------------
N+2
- – R ADC
f ADC × C ADC × ln ( 2 )

The simplified formula above (Equation 1) is used to determine the maximum external
impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

DocID027982 Rev 5 81/114

93
Electrical characteristics STM32L021x4

Table 54. RAIN max for fADC = 16 MHz(1)

RAIN max for standard channels (kΩ)
RAIN max for
Ts tS
fast channels VDD > 1.65 V VDD > 1.65 V
(cycles) (µs) VDD > VDD > VDD > VDD > VDD >
(kΩ) and and
2.7 V 2.4 V 2.0 V 1.8 V 1.75 V
TA > −10 °C TA > 25 °C

1.5 0.09 0.5 < 0.1 NA NA NA NA NA NA

3.5 0.22 1 0.2 < 0.1 NA NA NA NA NA
7.5 0.47 2.5 1.7 1.5 < 0.1 NA NA NA NA
12.5 0.78 4 3.2 3 1 NA NA NA NA
19.5 1.22 6.5 5.7 5.5 3.5 NA NA NA < 0.1
39.5 2.47 13 12.2 12 10 NA NA NA 5
79.5 4.97 27 26.2 26 24 < 0.1 NA NA 19
160.5 10.03 50 49.2 49 47 32 < 0.1 < 0.1 42
1. Guaranteed by design.

Table 55. ADC accuracy(1)(2)(3)(4)

Symbol Parameter Conditions Min Typ Max Unit

ET Total unadjusted error - 2 4

EO Offset error - 1 2.5
EG Gain error - 1 2 LSB
EL Integral linearity error - 1.5 2.5
ED Differential linearity error - 1 1.5
Effective number of bits 1.65 V < VDDA < 3.6 V, range 10.2 11
ENOB 1/2/3, except for TSSOP14 bits
Effective number of bits (16-bit mode package 11.3 12.1 -
oversampling with ratio =256)(5)

SINAD Signal-to-noise distortion 62 67.8 -

Signal-to-noise ratio 63 68 -
SNR Signal-to-noise ratio (16-bit mode dB
70 76 -
oversampling with ratio =256)(5)
THD Total harmonic distortion - -81 -68.5

82/114 DocID027982 Rev 5

STM32L021x4 Electrical characteristics

Table 55. ADC accuracy(1)(2)(3)(4)

Symbol Parameter Conditions Min Typ Max Unit

ET Total unadjusted error - 3 5

EO Offset error - 2 2.5
EG Gain error - 2 2.5 LSB
EL Integral linearity error - 1.5 2.5
ED Differential linearity error - 1 1.7
Effective number of bits 9.5 10.5 -
1.65 V < VDDA < 3.6 V, range
ENOB 1/2/3, TSSOP14 package bits
Effective number of bits (16-bit mode 10.7 11.6 -
oversampling with ratio =256)(5)

SINAD Signal-to-noise distortion 59 65 -

Signal-to-noise ratio 59 65 -
SNR Signal-to-noise ratio (16-bit mode dB
66 73 -
oversampling with ratio =256)(5)
THD Total harmonic distortion - -75 -63
1. ADC DC accuracy values are measured after internal calibration.
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input
pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input.
It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative
current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.12 does not affect the ADC
accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. In TSSOP14 package, where VDDA pin is shared with VDD pin, I/O toggling should be minimized to reach the values given in
the above table. I/O toggling with loaded I/O pins can generate ripple on VDD/VDDA and degrade the ADC accuracy.
5. This number is obtained by the test board without additional noise, resulting in non-optimized value for oversampling mode.

Figure 26. ADC accuracy characteristics

966$
(* ([DPSOHRIDQDFWXDOWUDQVIHUFXUYH

7KHLGHDOWUDQVIHUFXUYH
(QGSRLQWFRUUHODWLRQOLQH

(7 7RWDO8QDMXVWHG(UURUPD[LPXPGHYLDWLRQ
EHWZHHQWKHDFWXDODQGLGHDOWUDQVIHUFXUYHV
(7 (2 2IIVHW(UURUPD[LPXPGHYLDWLRQ

EHWZHHQWKHILUVWDFWXDOWUDQVLWLRQDQGWKHILUVW

LGHDORQH
(* *DLQ(UURUGHYLDWLRQEHWZHHQWKHODVW

(2 (/
LGHDOWUDQVLWLRQDQGWKHODVWDFWXDORQH
(' 'LIIHUHQWLDO/LQHDULW\(UURUPD[LPXP
GHYLDWLRQEHWZHHQDFWXDOVWHSVDQGWKHLGHDORQHV
('
(/ ,QWHJUDO/LQHDULW\(UURUPD[LPXPGHYLDWLRQ

EHWZHHQDQ\DFWXDOWUDQVLWLRQDQGWKHHQGSRLQW
/6%,'($/
FRUUHODWLRQOLQH

9''$

069

DocID027982 Rev 5 83/114

93
Electrical characteristics STM32L021x4

Figure 27. Typical connection diagram using the ADC

9''$

97 6DPSOHDQGKROG$'&
FRQYHUWHU
5$,1 5$'&
$,1[ ELW
,/Q$ FRQYHUWHU
&SDUDVLWLF 97
9$,1
&$'&

06Y9

1. Refer to Table 53: ADC characteristics for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.

6.3.16 Temperature sensor characteristics

Table 56. Temperature sensor calibration values

Calibration value name Description Memory address

TS ADC raw data acquired at

TS_CAL2 temperature of 130 °C ± 5 °C, 0x1FF8 007E - 0x1FF8 007F
VDDA= 3 V ± 10 mV

Table 57. Temperature sensor characteristics

Symbol Parameter Min Typ Max Unit

TL(1) VSENSE linearity with temperature - ±1 ±2 °C

Avg_Slope(1) Average slope 1.48 1.61 1.75 mV/°C
V130 Voltage at 130°C ±5°C(2) 640 670 700 mV
I DDA(TEMP)
(3)
Current consumption - 3.4 6 µA
tSTART(3) Startup time - - 10
ADC sampling time when reading the µs
TS_temp(4)(3) 10 - -
temperature
1. Guaranteed by characterization results, not tested in production.
2. Measured at VDD = 3 V ±10 mV. V30 ADC conversion result is stored in the TS_CAL1 byte.
3. Guaranteed by design, not tested in production.
4. Shortest sampling time can be determined in the application by multiple iterations.

84/114 DocID027982 Rev 5

STM32L021x4 Electrical characteristics

6.3.17 Comparators

Table 58. Comparator 1 characteristics

Symbol Parameter Conditions Min(1) Typ Max(1) Unit

VDDA Analog supply voltage - 1.65 3.6 V

R400K R400K value - - 400 -
kΩ
R10K R10K value - - 10 -
Comparator 1 input
VIN - 0.6 - VDDA V
voltage range
tSTART Comparator startup time - - 7 10
µs
(2)
td Propagation delay - - 3 10
Voffset Comparator offset(3) - - ±3 ±10 mV
VDDA = 3.6 V
Comparator offset
VIN+ = 0 V
dVoffset/dt variation in worst voltage 0 1.5 10 mV/1000 h
VIN- = VREFINT
stress conditions(3)
TA = 25 ° C
ICOMP1 Current consumption(4) - - 160 260 nA
1. Guaranteed by characterization, not tested in production.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-
inverting input set to the reference.
3. In TSSOP14 package, where VDDA pin is shared with VDD pin, I/O toggling should be minimized to reach
the values given in the above table. I/O toggling with loaded I/O pins can generate ripple on VDD/VDDA and
degrade the comparator performance.
4. Comparator consumption only. Internal reference voltage not included.

Table 59. Comparator 2 characteristics

Symbol Parameter Conditions Min Typ Max(1) Unit

VDDA Analog supply voltage - 1.65 - 3.6 V

VIN Comparator 2 input voltage range - 0 - VDDA V
Fast mode - 15 20
tSTART Comparator startup time
Slow mode - 20 25
1.65 V ≤ VDDA ≤ 2.7 V - 1.8 3.5
td slow Propagation delay(2) in slow mode µs
2.7 V ≤ VDDA ≤ 3.6 V - 2.5 6
1.65 V ≤ VDDA ≤ 2.7 V - 0.8 2
td fast Propagation delay(2) in fast mode
2.7 V ≤ VDDA ≤ 3.6 V - 1.2 4
Voffset Comparator offset error(3) - ±4 ±20 mV
VDDA = 3.3V
TA = 0 to 50 ° C
dThreshold/ Threshold voltage temperature V- =VREFINT, ppm
- 15 30
dt coefficient 3/4 VREFINT, /°C
1/2 VREFINT,
1/4 VREFINT.

DocID027982 Rev 5 85/114

93
Electrical characteristics STM32L021x4

Table 59. Comparator 2 characteristics (continued)

Symbol Parameter Conditions Min Typ Max(1) Unit

Fast mode - 3.5 5

ICOMP2 Current consumption(4) µA
Slow mode - 0.5 2
1. Guaranteed by characterization results, not tested in production.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-
inverting input set to the reference.
3. In TSSOP14 package, where VDDA pin is shared with VDD pin, I/O toggling should be minimized to reach
the values given in the above table. I/O toggling with loaded I/O pins can generate ripple on VDD/VDDA and
degrade the comparator performance.
4. Comparator consumption only. Internal reference voltage (necessary for comparator operation) is not
included.

6.3.18 Timer characteristics

TIM timer characteristics
The parameters given in the Table 60 are guaranteed by design.
Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).

Table 60. TIMx(1) characteristics

Symbol Parameter Conditions Min Max Unit

1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 32 MHz 31.25 - ns

Timer external clock 0 fTIMxCLK/2 MHz

fEXT
frequency on CH1 to CH4 f
TIMxCLK = 32 MHz 0 16 MHz
ResTIM Timer resolution - 16 bit
16-bit counter clock - 1 65536 tTIMxCLK
period when internal clock
tCOUNTER
is selected (timer’s fTIMxCLK = 32 MHz 0.0312 2048 µs
prescaler disabled)
- - 65536 × 65536 tTIMxCLK
tMAX_COUNT Maximum possible count
fTIMxCLK = 32 MHz - 134.2 s
1. TIMx is used as a general term to refer to the TIM2 and TIM21 timers.

86/114 DocID027982 Rev 5

STM32L021x4 Electrical characteristics

6.3.19 Communications interfaces

I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm) : with a bit rate up to 100 kbit/s
• Fast-mode (Fm) : with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+) : with a bit rate up to 1 Mbit/s.
The I2C timing requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to the reference manual for details) and when the I2CCLK frequency is
greater than the minimum given in Table 62. The SDA and SCL I/O requirements are met
with the following restrictions: the SDA and SCL I/O pins are not "true" open-drain. When
configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is
disabled, but is still present. Only FTf I/O pins support Fm+ low level output current
maximum requirement (refer to Section 6.3.13: I/O port characteristics for the I2C I/Os
characteristics).
All I2C SDA and SCL I/Os embed an analog filter (see Table 61 for the analog filter
characteristics).
The analog spike filter is compliant with I2C timings requirements only for the following
voltage ranges:
• Fast mode Plus: 2.7 V ≤VDD ≤3.6 V and voltage scaling Range 1
• Fast mode:
– 2 V ≤VDD ≤3.6 V and voltage scaling Range 1 or Range 2.
– VDD < 2 V, voltage scaling Range 1 or Range 2, Cload < 200 pF.
In other ranges, the analog filter should be disabled. The digital filter can be used instead.
Note: In Standard mode, no spike filter is required.

Table 61. I2C analog filter characteristics(1)

Symbol Parameter Conditions Min Max Unit

Range 1 260(3)
Maximum pulse width of spikes that
tAF Range 2 50(2) - ns
are suppressed by the analog filter
Range 3 -
1. Guaranteed by characterization results.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered

DocID027982 Rev 5 87/114

93
Electrical characteristics STM32L021x4

Table 62. I2C frequency in all I2C modes

Symbol Parameter Condition Min Unit

Standard-mode 2
Fast-mode 8

fI2CCLK I2C clock frequency Analog filter ON, MHz

18
DNF = 0
Fast-mode Plus
Analog filter OFF,
16
DNF = 1

88/114 DocID027982 Rev 5

STM32L021x4 Electrical characteristics

SPI characteristics
Unless otherwise specified, the parameters given in the following tables are derived from
tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 17.
Refer to Section 6.3.12: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Table 63. SPI characteristics in voltage Range 1 (1)

Symbol Parameter Conditions Min Typ Max Unit

Master mode 16
- -
Slave mode receiver 16
fSCK Slave mode Transmitter
SPI clock frequency - - 12(2) MHz
1/tc(SCK) 1.71<VDD<3.6V
Slave mode Transmitter
- - 16(2)
2.7<VDD<3.6V
Duty cycle of SPI clock
Duty(SCK) Slave mode 30 50 70 %
frequency
tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4Tpclk - -
th(NSS) NSS hold time Slave mode, SPI presc = 2 2Tpclk - -
tw(SCKH)
SCK high and low time Master mode Tpclk-2 Tpclk Tpclk+2
tw(SCKL)
tsu(MI) Master mode 3 - -
Data input setup time
tsu(SI) Slave mode 3 - -
th(MI) Master mode 3.5 - -
Data input hold time
th(SI) Slave mode 0 - - ns
ta(SO Data output access time Slave mode 15 - 36
tdis(SO) Data output disable time Slave mode 10 - 30
Slave mode 1.71<VDD<3.6V - 14 35
tv(SO)
Data output valid time Slave mode 2.7<VDD<3.6V - 14 20
tv(MO) Master mode - 4 6
th(SO) Slave mode 10 - -
Data output hold time
th(MO) Master mode 3 - -
1. Guaranteed by characterization results, not tested in production.
2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit
into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates
with a master having tsu(MI) = 0 while Duty(SCK) = 50%.

DocID027982 Rev 5 89/114

93
Electrical characteristics STM32L021x4

Table 64. SPI characteristics in voltage Range 2 (1)

Symbol Parameter Conditions Min Typ Max Unit

Master mode 8
Slave mode Transmitter
fSCK 8
SPI clock frequency 1.65<VDD<3.6V - - MHz
1/tc(SCK)
Slave mode Transmitter
8(2)
2.7<VDD<3.6V
Duty cycle of SPI clock
Duty(SCK) Slave mode 30 50 70 %
frequency
tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4Tpclk - -
th(NSS) NSS hold time Slave mode, SPI presc = 2 2Tpclk - -
tw(SCKH)
SCK high and low time Master mode Tpclk-2 Tpclk Tpclk+2
tw(SCKL)
tsu(MI) Master mode 3 - -
Data input setup time
tsu(SI) Slave mode 3 - -
th(MI) Master mode 6 - -
Data input hold time ns
th(SI) Slave mode 2 - -
ta(SO Data output access time Slave mode 18 - 52
tdis(SO) Data output disable time Slave mode 12 - 42

Slave mode - 16 33
tv(SO) Data output valid time
Master mode - 4 6
tv(MO) Slave mode 11 - -
Data output hold time
th(SO) Master mode 3 - -
1. Guaranteed by characterization results, not tested in production.
2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit
into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates
with a master having tsu(MI) = 0 while Duty(SCK) = 50%.

90/114 DocID027982 Rev 5

STM32L021x4 Electrical characteristics

Table 65. SPI characteristics in voltage Range 3 (1)

Symbol Parameter Conditions Min Typ Max Unit

fSCK Master mode 2

WF 6&.
6&.2XWSXW

&3+$
&32/
&3+$
&32/
6&.2XWSXW

&3+$
&32/
&3+$
&32/

WZ 6&.+ WU 6&.
WVX 0, WZ 6&./ WI 6&.
0,62
,13 87 06%,1 %,7,1 /6%,1

WK 0,
026,
06%287 % , 7287 /6%287
287387
WY 02 WK 02

DLG

1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.

DocID027982 Rev 5 93/114

93
Package information STM32L021x4

7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at [Link]
ECOPACK® is an ST trademark.

7.1 LQFP32 package information

Figure 31. LQFP32 - 32-pin, 7 x 7 mm, 32-pin low-profile quad flat package outline

3%!4).'
0,!.%
#
!
!

C
!

MM
'!5'% 0,!.%
CCC #

+
$
,
!

$
,
$

%
%

0).
)$%.4)&)#!4)/.

E 7@.&@7

1. Drawing is not to scale.

94/114 DocID027982 Rev 5

STM32L021x4 Package information

Table 66. LQFP32 - 32-pin, 7 x 7 mm, 32-pin low-profile quad flat package
mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.300 0.370 0.450 0.0118 0.0146 0.0177
c 0.090 - 0.200 0.0035 - 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 - 5.600 - - 0.2205 -
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 - 5.600 - - 0.2205 -
e - 0.800 - - 0.0315 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
ccc - - 0.100 - - 0.0039
k 0° 3.5° 7° 0° 3.5° 7°
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 32. LQFP32 recommended footprint

6?&0?6

1. Dimensions are expressed in millimeters.

DocID027982 Rev 5 95/114

110
Package information STM32L021x4

LQFP32 device marking

The following figure gives an example of topside marking versus pin 1 position identifier
location.
Other optional marking or inset/upset marks, which depends assembly location, are not
indicated below.

Figure 33. Example of LQFP32 marking (package top view)

3URGXFWLGHQWLILFDWLRQ

670/

'DWHFRGH
< ::
5HYLVLRQFRGH
3LQ
LQGHQWLILHU
5

06Y9

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.

96/114 DocID027982 Rev 5

STM32L021x4 Package information

7.2 UFQFPN32 package information

Figure 34. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package outline

GGG &
H $
&
$
6($7,1*3/$1(
'
E

( E
( (

/

' /
3,1,GHQWLILHU
$%B0(B9

1. Drawing is not to scale.

2. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this backside pad to PCB ground.

DocID027982 Rev 5 97/114

110
Package information STM32L021x4

Table 67. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 - - 0.050 - - 0.0020
A3 - 0.152 - - 0.0060 -
b 0.180 0.230 0.280 0.0071 0.0091 0.0110
D 4.900 5.000 5.100 0.1929 0.1969 0.2008
D1 3.400 3.500 3.600 0.1339 0.1378 0.1417
D2 3.400 3.500 3.600 0.1339 0.1378 0.1417
E 4.900 5.000 5.100 0.1929 0.1969 0.2008
E1 3.400 3.500 3.600 0.1339 0.1378 0.1417
E2 3.400 3.500 3.600 0.1339 0.1378 0.1417
e - 0.500 - - 0.0197 -
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
ddd - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 35. UFQFPN32 recommended footprint

$%B)3B9

1. Dimensions are expressed in millimeters.

98/114 DocID027982 Rev 5

STM32L021x4 Package information

7.3 UFQFPN28 4 x 4 mm package information

Figure 36. UFQFPN28 - 28-lead, 4x4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline

' 'HWDLO<

(

'HWDLO=
!"?-%?6

1. Drawing is not to scale.

Table 68. UFQFPN28 - 28-lead, 4x4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data(1)
millimeters inches
Symbol
Min Typ Max Min Typ Max

A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 - 0.000 0.050 - 0.0000 0.0020
D 3.900 4.000 4.100 0.1535 0.1575 0.1614
D1 2.900 3.000 3.100 0.1142 0.1181 0.1220
E 3.900 4.000 4.100 0.1535 0.1575 0.1614
E1 2.900 3.000 3.100 0.1142 0.1181 0.1220
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
L1 0.250 0.350 0.450 0.0098 0.0138 0.0177
T - 0.152 - - 0.0060 -

DocID027982 Rev 5 99/114

110
Package information STM32L021x4

Table 68. UFQFPN28 - 28-lead, 4x4 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data(1) (continued)
millimeters inches
Symbol
Min Typ Max Min Typ Max

b 0.200 0.250 0.300 0.0079 0.0098 0.0118

e - 0.500 - - 0.0197 -
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 37. UFQFPN28 recommended footprint

!"?&0?6

1. Dimensions are expressed in millimeters.

100/114 DocID027982 Rev 5

STM32L021x4 Package information

UFQFPN28 device marking

Figure 38. Example of UFQFPN28 marking (package top view)

3URGXFWLGHQWLILFDWLRQ /*

'DWHFRGH 5HYLVLRQFRGH

3LQ < :: 5
LQGHQWLILHU

06Y9

DocID027982 Rev 5 101/114

110
Package information STM32L021x4

7.4 UFQFPN20 package information

Figure 39. UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package outline

3LQ (

7239,(:

/
'
GGG
/ '
H / $

H
E
( (

/ $
$

%277209,(: 6,'(9,(:
$$B0(B9

1. Drawing is not to scale.

Table 69. UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
A3 - 0.152 - - 0.060 -
D 2.900 3.000 3.100 0.1142 0.1181 0.1220
D1 - 2.000 - - 0.0790 -
E 2.900 3.000 3.100 0.1142 0.1181 0.1220
E1 - 2.000 - - 0.0790 -
L1 0.500 0.550 0.600 0.0197 0.0217 0.0236
L2 0.300 0.350 0.400 0.0118 0.0138 0.0157
L3 - 0.200 - 0.0079
L5 - 0.150 - 0.0059

102/114 DocID027982 Rev 5

STM32L021x4 Package information

Table 69. UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package mechanical data (continued)
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

b 0.180 0.250 0.300 0.0071 0.0098 0.0118

e - 0.500 - - 0.0197 -
ddd - - 0.050 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 40. UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
package recommended footprint

!!?&0?6

1. Dimensions are expressed in millimeters.

DocID027982 Rev 5 103/114

110
Package information STM32L021x4

UFQFPN20 device marking

Figure 41. Example of UFQFPN20 marking (package top view)

3URGXFWLGHQWLILFDWLRQ
)8

'DWHFRGH 5HYLVLRQFRGH

< :: 5
3LQ
LQGHQWLILHU

06Y9

104/114 DocID027982 Rev 5

STM32L021x4 Package information

7.5 TSSOP20 package information

Figure 42.TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package outline

( (
6($7,1* PP
3/$1( *$8*(3/$1(
&

3,1
,'(17,),&$7,21
N
DDD & $ /
$ $
/

E H

<$B0(B9

1. Drawing is not to scale.

Table 70. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package mechanical data
millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.

A - - 1.200 - - 0.0472
A1 0.050 - 0.150 0.0020 - 0.0059
A2 0.800 1.000 1.050 0.0315 0.0394 0.0413
b 0.190 - 0.300 0.0075 - 0.0118
c 0.090 - 0.200 0.0035 - 0.0079
(2)
D 6.400 6.500 6.600 0.2520 0.2559 0.2598
E 6.200 6.400 6.600 0.2441 0.2520 0.2598
E1(3) 4.300 4.400 4.500 0.1693 0.1732 0.1772
e - 0.650 - - 0.0256 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -

DocID027982 Rev 5 105/114

110
Package information STM32L021x4

Table 70. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package mechanical data (continued)
millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.

k 0° - 8° 0° - 8°
aaa - - 0.100 - - 0.0039
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15mm per side.
3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25mm per side.

Figure 43. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
package footprint

<$B)3B9

1. Dimensions are expressed in millimeters.

106/114 DocID027982 Rev 5

STM32L021x4 Package information

7.6 TSSOP14 package information

Figure 44.TSSOP14 – 14-lead thin shrink small outline, 5.0 x 4.4 mm, 0.65 mm pitch,
package outline

% %
3%!4).' MM
0,!.% '!'% 0,!.%
#

0).
)$%.4)&)#!4)/.
K
AAA #
! ,
! !
,

B E
433/0?2?-%?6

1. Drawing is not to scale.

Table 71. TSSOP14 – 14-lead thin shrink small outline, 5 x 4.4 mm, 0.65 mm pitch,
package mechanical data
millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.

A - - 1.200 - - 0.0472
A1 0.050 - 0.150 0.0020 - 0.0059
A2 0.800 1.000 1.050 0.0315 0.0394 0.0413
b 0.190 - 0.300 0.0075 - 0.0118
c 0.090 - 0.200 0.0035 - 0.0079
D 4.900 5.000 5.100 0.1929 0.1969 0.2008
E 6.200 6.400 6.600 0.2441 0.2520 0.2598
E1 4.300 4.400 4.500 0.1693 0.1732 0.1772
e - 0.650 - - 0.0256 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° - 8° 0° - 8°
aaa - - 0.100 - - 0.0039
1. Values in inches are converted from mm and rounded to four decimal digits.

DocID027982 Rev 5 107/114

110
Package information STM32L021x4

TSSOP14 device marking

Figure 45. Example of TSSOP14 marking (package top view)

3URGXFWLGHQWLILFDWLRQ
/'3

'DWHFRGH 5HYLVLRQFRGH

< :: 5
3LQ
LQGHQWLILHU

06Y9

7.7 Thermal characteristics

The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max × ΘJA)
Where:
• TA max is the maximum ambient temperature in ° C,
• ΘJA is the package junction-to-ambient thermal resistance, in ° C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.

108/114 DocID027982 Rev 5

STM32L021x4 Package information

Table 72. Thermal characteristics

Symbol Parameter Value Unit
Thermal resistance junction-ambient
60
LQFP32 - 7 x 7 mm / 0.8 mm pitch
Thermal resistance junction-ambient
39
UFQFPN32 - 5 x 5 mm / 0.5 mm pitch
Thermal resistance junction-ambient
97
UFQFPN28 - 4 x 4 mm, 0.5 mm pitch
Thermal resistance junction-ambient
ΘJA 102 °C/W
UFQFPN20 - 3 x 3 mm, 0.5 mm pitch
Thermal resistance junction-ambient
74
TSSOP20 - 169 mils
Thermal resistance junction-ambient
95
TSSOP14 - 169 mils

Figure 46. Thermal resistance

/4)31
84)1

8)4)31

8)4)31

3' P: 76623

76623

7HPSHUDWXUH &
06Y9

1. The above curves are valid for range 3.

7.7.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from [Link].

DocID027982 Rev 5 109/114

110
Ordering information STM32L021x4

8 Ordering information
Table 73. STM32L021x4 ordering information scheme
Example: STM32 L 021 K 4 T 6 D xxx

Device family
STM32 = Arm-based 32-bit microcontroller

Product type
L = Low power

Device subfamily
021 = Access line with AES

Pin count
K = 32 pins
G = 28 pins
F = 20 pins
D = 14 pins

Flash memory size

4 = 16 Kbytes

Package
T = LQFP
U = UFQFPN
P = TSSOP

Temperature range
6 = Industrial temperature range, –40 to 85 °C
7 = Industrial temperature range, –40 to 105 °C
3 = Industrial temperature range, –40 to 125 °C

Options
No character = VDD range: 1.8 to 3.6 V and BOR enabled
D = VDD range: 1.65 to 3.6 V and BOR disabled

Packing
TR = tape and reel
No character = tray or tube

For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.

110/114 DocID027982 Rev 5

STM32L021x4 Revision history

9 Revision history

Table 75. Document revision history

Date Revision Changes

07-Dec-2015 1 Initial release.

Features: modified current consumption in run mode,
Cortex®-M0+ core frequency range and total number of timers.
Updated ADC conversion consumption on cover page.
Updated ADC conversion consumption on cover page.
Updated UFQFPN28 pinout: Figure 5: STM32L021x4
UFQFPN28 pinout and Table 12: Pin definitions.
11-Feb-2016 2
Updated Table 54: RAIN max for fADC = 16 MHz.
Modified TS_CAL2 description in Table 56: Temperature
sensor calibration values.
Added Section : UFQFPN20 device marking, Section :
TSSOP14 device marking and Section : UFQFPN28
device marking.
Changed minimum comparator supply voltage to 1.65 V
on cover page.
Added baudrate allowing to wake up the MCU from Stop
mode in Section 3.16.3: Low-power universal
asynchronous receiver transmitter (LPUART).
Added number of fast and standard channels in
Section 3.10: Analog-to-digital converter (ADC).
Updated Table 15: Current characteristics to add the
total output current for STM32L021GxUx.
Changed VDDA minimum value to 1.65 V in Table 17:
General operating conditions.
Updated Table 25: Current consumption in Sleep mode,
Table 26: Current consumption in Low-power Run
mode, Table 27: Current consumption in Low-power
Sleep mode and Table 29: Typical and maximum current
17-Mar-2016 3 consumptions in Standby mode.
Section 6.3.15: 12-bit ADC characteristics:
– Table 53: ADC characteristics:
Distinction made between VDDA for fast and standard
channels; added note 1.
Updated condition for fTRIG measurement.
Added note 4. related to RADC and removed
measurement condition.
Updated tS and tCONV.
– Updated equation 1 description.
– Updated Table 54: RAIN max for fADC = 16 MHz for
fADC = 16 MHz and distinction made between fast and
standard channels.
– Updated measurement condition in Table 55: ADC
accuracy.
Added Table 63: USART/LPUART characteristics.

DocID027982 Rev 5 111/114

113
Revision history STM32L021x4

Table 75. Document revision history

Date Revision Changes

Updated:
– Features in cover page: Stop mode values, number of
DMA channels, number of I/Os, number of
communication peripherals.
20-Jun-2016 4 – Table 26: Current consumption in Low-power Run
mode, Table 27: Current consumption in Low-power
Sleep mode, Table 33: Low-power mode wakeup
timings, Table 35: Low-speed external user clock
characteristics

Removed I/O operation from Table 2: Functionalities

depending on the operating power supply range.
Updated Section 3.4.4: Boot modes and added Note 7.
in Table 12: Pin definitions.
Changed USARTx_RTS and LPUARTx_RTS into
USARTx_RTS_DE and LPUARTx_RTS_DE,
respectively in Section 4: Pin descriptions.
In Section 5: Memory mapping, replaced memory
mapping schematic by reference to the reference
manual.
Updated introduction text in Section 6.2: Absolute
maximum ratings to mention device mission profile and
extended mission profiles.
Added note in Table 48: I/O current injection
susceptibility.
12-Sep-2017 5
Updated minimum and maximum values of I/O weak
pull-up equivalent resistor (RPU) and weak pull-down
equivalent resistor (RPD) in Table 49: I/O static
characteristics.
Updated minimum and maximum values of NRST weak
pull-up equivalent resistor (RPU) in Table 52: NRST pin
characteristics. Added note 2 related to the position of
the external capacitor below Figure 25: Recommended
NRST pin protection.
Updated Section : I2C interface characteristics.
Removed section USART/LPUART characteristics.
Updated Figure 28: SPI timing diagram - slave mode
and CPHA = 0, Figure 29: SPI timing diagram - slave
mode and CPHA = 1(1) and Figure 30: SPI timing
diagram - master mode(1).

112/114 DocID027982 Rev 5

STM32L021x4 Revision history

Table 75. Document revision history

Date Revision Changes

In Section 7: Package information:

– Added paragraph related to optional marking or
inset/upset marks in all device marking sections.
– Updated Table 66: LQFP32 - 32-pin, 7 x 7 mm, 32-pin
low-profile quad flat package mechanical data.
– Updated Figure 34: UFQFPN32 - 32-pin, 5x5 mm,
0.5 mm pitch ultra thin fine pitch quad flat package
outline and Table 67: UFQFPN32 - 32-pin, 5x5 mm,
0.5 mm pitch ultra thin fine pitch quad flat package
mechanical data.
– Updated Figure 39: UFQFPN20 - 20-lead, 3x3 mm,
0.5 mm pitch, ultra thin fine pitch quad flat package
outline and Table 70: UFQFPN20 - 20-lead, 3x3 mm,
12-Sep-2017 5 (continued) 0.5 mm pitch, ultra thin fine pitch quad flat package
mechanical data.
– Added notes related to D and E1 in Table 71:
TSSOP20 – 20-lead thin shrink small outline, 6.5 x
4.4 mm, 0.65 mm pitch, package mechanical data.
– Updated Figure 44: TSSOP14 – 14-lead thin shrink
small outline, 5.0 x 4.4 mm, 0.65 mm pitch, package
outline and Table 71: TSSOP20 – 20-lead thin shrink
small outline, 6.5 x 4.4 mm, 0.65 mm pitch, package
mechanical data
– Added notes related to D and E1 in Table 71:
TSSOP20 – 20-lead thin shrink small outline, 6.5 x
4.4 mm, 0.65 mm pitch, package mechanical data.
Section 8 renamed into Ordering information.

DocID027982 Rev 5 113/114

113
STM32L021x4

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

114/114 DocID027982 Rev 5

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

STMicroelectronics:
STM32L021K4T6 STM32L021F4U6TR STM32L021G4U6 STM32L021D4P6 STM32L021D4P7
STM32L021D4P7TR STM32L021D4P7D STM32L021D4P7DTR

STM32L031x4 STM32L031x6
No ratings yet
STM32L031x4 STM32L031x6
126 pages
stm32l051t8 PDF
No ratings yet
stm32l051t8 PDF
133 pages
STM32L031 Ultra-Low-Power MCU Datasheet
No ratings yet
STM32L031 Ultra-Low-Power MCU Datasheet
118 pages
STM32L051 Ultra-Low-Power MCU Datasheet
No ratings yet
STM32L051 Ultra-Low-Power MCU Datasheet
127 pages
Data Sheet y
No ratings yet
Data Sheet y
109 pages
stm32l010rb Datasheet
No ratings yet
stm32l010rb Datasheet
89 pages
STM32L010C6T6
No ratings yet
STM32L010C6T6
90 pages
IC STMicroelectronics STM32L010F4P6 Eec
No ratings yet
IC STMicroelectronics STM32L010F4P6 Eec
91 pages
STM 32 L 010 F 4
No ratings yet
STM 32 L 010 F 4
91 pages
STM 32 L 071 CB
No ratings yet
STM 32 L 071 CB
148 pages
STM32L072 Ultra-Low-Power MCU Datasheet
No ratings yet
STM32L072 Ultra-Low-Power MCU Datasheet
160 pages
STM32L083 Ultra-Low-Power MCU Datasheet
No ratings yet
STM32L083 Ultra-Low-Power MCU Datasheet
149 pages
STM 32 L 072 CZ
No ratings yet
STM 32 L 072 CZ
149 pages
STM 32 L 082 CZ
No ratings yet
STM 32 L 082 CZ
132 pages
STM32L052x6 STM32L052x8
No ratings yet
STM32L052x6 STM32L052x8
150 pages
stm32l010k8 1851374
No ratings yet
stm32l010k8 1851374
93 pages
STM 32 C 091 CB
No ratings yet
STM 32 C 091 CB
123 pages
STM32L100RC Ultra-Low-Power MCU Datasheet
No ratings yet
STM32L100RC Ultra-Low-Power MCU Datasheet
106 pages
STM32C011x4/x6: Arm Cortex - M0+ 32-Bit MCU, 32 KB Flash, 6 KB RAM, 2 X USART, Timers, ADC, Comm. I/Fs, 2-3.6 V
No ratings yet
STM32C011x4/x6: Arm Cortex - M0+ 32-Bit MCU, 32 KB Flash, 6 KB RAM, 2 X USART, Timers, ADC, Comm. I/Fs, 2-3.6 V
92 pages
STM32L100C6 STM32L100R8 STM32L100RB
No ratings yet
STM32L100C6 STM32L100R8 STM32L100RB
103 pages
STM 32 L 152 Re
No ratings yet
STM 32 L 152 Re
136 pages
STM32L152 Ultra-Low-Power MCU Datasheet
No ratings yet
STM32L152 Ultra-Low-Power MCU Datasheet
133 pages
STM32L152VCT6 - Datasheet
No ratings yet
STM32L152VCT6 - Datasheet
136 pages
STM32 F042 X 4
No ratings yet
STM32 F042 X 4
118 pages
STM32L053R8
0% (1)
STM32L053R8
136 pages
STM 32 L 073 RZ
No ratings yet
STM 32 L 073 RZ
163 pages
STM32C051x6/x8 MCU Datasheet
No ratings yet
STM32C051x6/x8 MCU Datasheet
110 pages
STM 32 L 073 RZ
No ratings yet
STM 32 L 073 RZ
157 pages
En DM00034689
No ratings yet
En DM00034689
154 pages
STM32G031 MCU Datasheet Overview
No ratings yet
STM32G031 MCU Datasheet Overview
126 pages
STM32C011x4/x6: Arm Cortex - M0+ 32-Bit MCU, 32 KB Flash, 6 KB RAM, 2 X USART, Timers, ADC, Comm. I/Fs, 2-3.6 V
No ratings yet
STM32C011x4/x6: Arm Cortex - M0+ 32-Bit MCU, 32 KB Flash, 6 KB RAM, 2 X USART, Timers, ADC, Comm. I/Fs, 2-3.6 V
94 pages
STM32G0B0KE/CE/RE/VE: Arm Cortex - M0+ 32-Bit MCU, 512KB Flash, 144KB RAM, 6x USART, Timers, ADC, Comm. I/Fs, 2.0-3.6V
No ratings yet
STM32G0B0KE/CE/RE/VE: Arm Cortex - M0+ 32-Bit MCU, 512KB Flash, 144KB RAM, 6x USART, Timers, ADC, Comm. I/Fs, 2.0-3.6V
105 pages
STM32F070CB/RB/F6 Datasheet Overview
No ratings yet
STM32F070CB/RB/F6 Datasheet Overview
84 pages
STM 32 L 152 ZD
No ratings yet
STM 32 L 152 ZD
155 pages
STM32F301x6/x8 MCU Datasheet
No ratings yet
STM32F301x6/x8 MCU Datasheet
141 pages
En DM00039193
No ratings yet
En DM00039193
122 pages
Ds 14693
No ratings yet
Ds 14693
131 pages
STM32L152VET6
No ratings yet
STM32L152VET6
136 pages
STM32F301
No ratings yet
STM32F301
135 pages
STM32G030 MCU Datasheet Overview
No ratings yet
STM32G030 MCU Datasheet Overview
100 pages
STM32
No ratings yet
STM32
88 pages
DM 00088500
No ratings yet
DM 00088500
88 pages
STM32G0B0KE 32-bit MCU Datasheet
No ratings yet
STM32G0B0KE 32-bit MCU Datasheet
111 pages
STM32G070CB/KB/RB: Arm Cortex - M0+ 32-Bit MCU, 128 KB Flash, 36 KB RAM, 4x USART, Timers, ADC, Comm. I/Fs, 2.0-3.6V
No ratings yet
STM32G070CB/KB/RB: Arm Cortex - M0+ 32-Bit MCU, 128 KB Flash, 36 KB RAM, 4x USART, Timers, ADC, Comm. I/Fs, 2.0-3.6V
93 pages
Processor RSA Stm32f302cb-956187
No ratings yet
Processor RSA Stm32f302cb-956187
145 pages
STM32F334x4 STM32F334x6 STM32F334x8
No ratings yet
STM32F334x4 STM32F334x6 STM32F334x8
125 pages
Stm32f303re PDF
No ratings yet
Stm32f303re PDF
173 pages
STM32F302VB Datasheet
No ratings yet
STM32F302VB Datasheet
142 pages
STM32F303xB STM32F303xC Datasheet - Production Data
No ratings yet
STM32F303xB STM32F303xC Datasheet - Production Data
148 pages
STM32G031x4/x6/x8: Arm Cortex - M0+ 32-Bit MCU, Up To 64 KB Flash, 8 KB RAM, 2x USART, Timers, ADC, Comm. I/Fs, 1.7-3.6V
No ratings yet
STM32G031x4/x6/x8: Arm Cortex - M0+ 32-Bit MCU, Up To 64 KB Flash, 8 KB RAM, 2x USART, Timers, ADC, Comm. I/Fs, 1.7-3.6V
117 pages
STM32F303
No ratings yet
STM32F303
146 pages
STM32G031 32-bit MCU Datasheet
No ratings yet
STM32G031 32-bit MCU Datasheet
117 pages
STM32G030F6P6 MCU Datasheet
No ratings yet
STM32G030F6P6 MCU Datasheet
94 pages
stm32g051f8
No ratings yet
stm32g051f8
131 pages
STM32F334x4 6 8
No ratings yet
STM32F334x4 6 8
121 pages
Memory Organization and Hierarchy Overview
No ratings yet
Memory Organization and Hierarchy Overview
36 pages
Low Voltage Dry-Type Transformers Guide
No ratings yet
Low Voltage Dry-Type Transformers Guide
20 pages
Mikrotik Point-to-Point Link Guide
No ratings yet
Mikrotik Point-to-Point Link Guide
61 pages
Heidenhain ECN 1313/1325/ERN 1387 Guide
No ratings yet
Heidenhain ECN 1313/1325/ERN 1387 Guide
6 pages
Solid State vs. Conventional Transformers
No ratings yet
Solid State vs. Conventional Transformers
5 pages
Microwave Engineering Lab Manual ECE-410N
No ratings yet
Microwave Engineering Lab Manual ECE-410N
51 pages
Optimizing IBC-SHJ Solar Cells via 2D Simulation
No ratings yet
Optimizing IBC-SHJ Solar Cells via 2D Simulation
6 pages
RF Sputtering Process Explained
No ratings yet
RF Sputtering Process Explained
1 page
Fisher HC6010 Calibration Guide
93% (15)
Fisher HC6010 Calibration Guide
14 pages
Choosing Shakers for Modal Analysis
No ratings yet
Choosing Shakers for Modal Analysis
4 pages
21-Level Inverter Design with SHE PWM
No ratings yet
21-Level Inverter Design with SHE PWM
8 pages
Computer Literacy Mid-Term Test 2009
No ratings yet
Computer Literacy Mid-Term Test 2009
13 pages
JWI-586 Digital Weighing Indicator Guide
No ratings yet
JWI-586 Digital Weighing Indicator Guide
16 pages
Inertial Navigation Systems Overview
0% (1)
Inertial Navigation Systems Overview
12 pages
Single Phase AC Circuits Overview
No ratings yet
Single Phase AC Circuits Overview
3 pages
GST200N Fire Alarm Panel Overview
No ratings yet
GST200N Fire Alarm Panel Overview
83 pages
Power Electronics Lab Overview
No ratings yet
Power Electronics Lab Overview
206 pages
Hitano EMR Series Capacitors Data Sheet
No ratings yet
Hitano EMR Series Capacitors Data Sheet
3 pages
EVlink Pro AC Charging Station Specs
No ratings yet
EVlink Pro AC Charging Station Specs
8 pages
Aviation Manuals for Enthusiasts
100% (2)
Aviation Manuals for Enthusiasts
256 pages
Tehnicka Preporuka 4, Prilog
No ratings yet
Tehnicka Preporuka 4, Prilog
8 pages
Icom IC7000 Tuner Connector Warning
No ratings yet
Icom IC7000 Tuner Connector Warning
13 pages
An Honet - Technical Manual (V7.11) PDF
No ratings yet
An Honet - Technical Manual (V7.11) PDF
202 pages
EnPower33 Silver UPS Inverter Test Guide
No ratings yet
EnPower33 Silver UPS Inverter Test Guide
5 pages
Instruction Manual: Please Read All The Instructions Completely Before Use and Save This Manual For Future Reference
No ratings yet
Instruction Manual: Please Read All The Instructions Completely Before Use and Save This Manual For Future Reference
24 pages
Circuit Module Assemblies A4004
No ratings yet
Circuit Module Assemblies A4004
2 pages
Infrastructure Equipment Inspection Register
No ratings yet
Infrastructure Equipment Inspection Register
2 pages
IT Course Descriptions for WVCST
No ratings yet
IT Course Descriptions for WVCST
6 pages
NC 1000
No ratings yet
NC 1000
2 pages
ATS48C66Q Soft Starter Discontinuation
No ratings yet
ATS48C66Q Soft Starter Discontinuation
6 pages

STM32L021 Ultra-Low-Power MCU Datasheet

Uploaded by

STM32L021 Ultra-Low-Power MCU Datasheet

Uploaded by

STM32L021D4 STM32L021F4

September 2017 DocID027982 Rev 5 1/114

2/114 DocID027982 Rev 5

3.16 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

DocID027982 Rev 5 3/114

6.3.15 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

4/114 DocID027982 Rev 5

Table 1. Ultra-low-power STM32L021x4 device features and peripheral counts . . . . . . . . . . . . . . . 11

DocID027982 Rev 5 5/114

Table 46. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6/114 DocID027982 Rev 5

Figure 1. STM32L021x4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

DocID027982 Rev 5 7/114

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

8/114 DocID027982 Rev 5

The ultra-low-power STM32L021x4 family includes devices in 6 different package types

DocID027982 Rev 5 9/114

The access line ultra-low-power STM32L021x4 family incorporates the high-performance

10/114 DocID027982 Rev 5

2.1 Device overview

Data EEPROM (bytes) 512

Clocks: HSE(2)/LSE/HSI/MSI/LSI 1/1/1/1/1

12-bit synchronized ADC 1 1 1

Max. CPU frequency 32 MHz

1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option

DocID027982 Rev 5 11/114

Figure 1. STM32L021x4 block diagram

3+>@ *3,23257+ 5;7;576

&.B,1 +6( +6,0

12/114 DocID027982 Rev 5

2.2 Ultra-low-power device continuum

DocID027982 Rev 5 13/114

3.1 Low-power modes

14/114 DocID027982 Rev 5

(if internal reference voltage is on), it can be the RTC alarm/tamper/timestamp/wakeup

DocID027982 Rev 5 15/114

Table 2. Functionalities depending on the operating power supply range

ADC only, conversion time Range 2 or

ADC only, conversion time

Conversion time up to 1.14

Conversion time up to 1.14

Conversion time up to 1.14

Table 3. CPU frequency range depending on dynamic voltage scaling

CPU frequency range Dynamic voltage scaling range

16 MHz to 32 MHz (1ws)

32 kHz to 4.2 MHz (0ws) Range 3

16/114 DocID027982 Rev 5

Table 4. Functionalities depending on the working mode

DocID027982 Rev 5 17/114

Table 4. Functionalities depending on the working mode

3.2 Interconnect matrix

Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power

18/114 DocID027982 Rev 5

Table 5. STM32L021x4 peripherals interconnect matrix

Timer input channel,

3.3 Arm® Cortex®-M0+ core

DocID027982 Rev 5 19/114

Nested vectored interrupt controller (NVIC)

3.4 Reset and supply management

3.4.1 Power supply schemes

3.4.2 Power supply supervisor

20/114 DocID027982 Rev 5

3.4.3 Voltage regulator

3.4.4 Boot modes

DocID027982 Rev 5 21/114

3.5 Clock management

22/114 DocID027982 Rev 5

Figure 2. Clock tree

/68 /6' /6'

#9 0&26(/ $'&HQDEOH

DocID027982 Rev 5 23/114

3.6 Low-power real-time clock and backup registers

3.7 General-purpose inputs/outputs (GPIOs)

Extended interrupt/event controller (EXTI)

3+>@ *3,23257+ 5;7;576

&.B,1 +6( +6,0

#9 0&26(/ $'&HQDEOH

3&26&B,1 3$