© April 2018 | IJIRT | Volume 4 Issue 11 | ISSN: 2349-6002
Evolution of Pulse width modulation techniques of
modular multilevel converter
Khushbu Saradva 1 , Meeta Matnani2 , Tapankumar Trivedi3
1
Student Member, IEEE
Abstract- The modular multilevel converter (MMC) is a small motor drives such as laminators, compressors,
promising converter technology for various high- mills and large electric drives systems. Due to its
voltage high-power applications. The reason to that is power electronic switches balancing and distributed
low-distortion output quantities can be achieved with
voltage stress, multilevel nature which means having
low average switching frequencies per switch and
nearly stepped sinusoidal waveforms and reduced
without output filters. Modular multilevel converter
pulse width modulation based control approaches are harmonics. Its working principle is based on
evaluated. The multicarrier PWM techniques such as producing small output voltage steps which results in
Phase disposition PWM (PDPWM), Phase opposition better power quality. They operate at low voltage
disposition PWM (PODPWM), Alternate phase levels and also at a low switching frequency so that
opposition disposition PWM (APODPWM) is employed the switching losses are also reduced. Other
and a comparative study is done based on the quality of advantages include better electromagnetic
the load voltage and load current output. This paper compatibility due to the low dv/dt transitions.
presents the simulation of single phase modular
Generally multi-level inverters employ a number of
multilevel converter based on Half-Bridge sub module
cascaded power switches in order to increase either
topology. S imulation has been carried out for various
modulation techniques using MATLAB/S imulink and the voltage or power capability of inverter, the idea
the results are observed. behind this concept is to use multiple small voltage
level sources including storage devices , such as
Index Terms- Modular Multilevel Converter (MMC), capacitors or batteries to generate a required signal
S ubmodule (S M), Multicarrier PWM (MCPWM), Total taking advantage of using lower-rated
harmonic distortion (THD). semiconductors.
INTRODUCTION STRUCTURE OF MMC
Modular multilevel converters have great potential in Modular multilevel converter (MMC) topology was
high-power applications, such as DC firstly proposed by Lesnicar and Marquardt in 2003.
interconnections, DC power grids, and off-shore The main circuit a three-phase MMC is outlined in
wind power generation are in need of accurate power Figure 1. Each of the three parallel-connected phase
flow control and high efficiency power conversion in legs comprises two phase arms. Each arm consists of
order to reduce both their operating costs and their a string of series-connected submodules, and a series
environmental impact [1]. High power converters for inductor. Each submodule contains a switch-mode
utility applications require line-frequency half-bridge and a capacitor [4]. A specific submodule
transformers for the purpose of enhancing their can be inserted or bypassed in this series -connection
voltage or current rating. The use of line-frequency by control of the associated half-bridge. The desired
transformers, however, not only makes the converter instantaneous voltage across the arm is controlled by
heavy and bulky, but also induces the so-called DC series connecting a suitable number of charged sub
magnetic flux deviation when a single-line-to-ground module capacitors in the arm as commanded by the
fault occurs [2]. modulator.
MMC applications are mainly in the field of high- When modeling a converter arm, there is some
voltage high power applications such as in flexible resistive voltage drop that appears across conducting
A.C transmission system (FACTS) applications, switches, cables, connections and the inductor, which
IJIRT 146103 INTERNATIONAL JO URNAL OF INNOVATIVE RESEARCH IN TECHNOLOGY 1609
© April 2018 | IJIRT | Volume 4 Issue 11 | ISSN: 2349-6002
is often disregarded. This is reasonable, as in a large- i
scale converter resistive voltage drops need to be as Where diffj is the inner difference current of phase j,
small as possible, because they cause losses. which flows through both the upper and lower arms
Dimensioning an MMC is not an obvious procedure. and is given as
It depends very much on each specific application. i pj inj
The first step is to decide the number of sub modules
idiffj ...................(3)
2
per arm, depending on the voltage level the converter According to [11], the MMC can be characterized by
will be connected to and the ratings of the the following equations:
semiconductors that are more cost efficient[6]. The
R0ivj
L0 divj
number of levels determines also the nominal uvj e j . ................(4)
capacitor voltage in each sub module. The arm 2 2 dt
inductor values are determined based on external di U u unj
fault criteria, and should be high enough to limit the Lo ( diffj ) Roidiffj dc pj ..........(5)
dt 2 2
current from an AC short-circuit. On the other hand,
from a control perspective, large inductors will slow here, ( j a, b, c)
down the effect of the controllers, which is e
Where j in (4) is the inner emf generated in phase j
undesirable. The fault currents also contribute to the
and is expressed as
capacitor dimensioning, where the output power
level, as well as the level of active control applied are unj u pj
ej ..............(6)
also important factors. 2
SM
DC uvj
According to (4), when is regarded as the ac
SM
ivj
network voltage, the current can be controlled
SM ej
directly by regulating the control variable .
L
DC
Figure 1 Schematic of a three phase MMC
Figure 2 shows the single-phase equivalent circuit of
the MMC. L0 and R0 are the arm inductance and
equivalent arm resistance,
respectively. Udc and Idc are the total dc bus voltage
and dc current, respectively. u vj is the converter
output voltage of phase j at point V whereas ivj is the
corresponding line current. The arm voltages
generated by the cascaded SMs are expressed as u pj
and u nj where the subscripts p and n denote the upper Figure 2 Single-phase equivalent circuit of the MMC
(positive) and lower (negative) arms, respectively.
According to Figure 2 and [11], the corresponding
arm currents can be expressed as s1 D1
ivj
i pj idiffj ...................(1) C Vc
2
ivj s2 D2
inj idiffj ...................(2) V0
2
Figure 3 Configuration of Half bridge sub-module
Table 1 switching state of Half-bridge sub module
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© April 2018 | IJIRT | Volume 4 Issue 11 | ISSN: 2349-6002
State The frequency modulation index (mf) for level shifted
1 ON OFF and phase shifted PWM techniques is defined as the
2 OFF ON 0 ratio of frequency of the carrier wave (fc) to the
frequency of the reference sine wave (fr) and it is
OPERATION OF HALF BRIDGE SM given in equation (2).
The sub module produces the required AC phase fc
voltage. AC side terminals of the converter branch mf
fr (2)
out between the two inductors of upper and lower
arms. The submodule topology, being half-bridge A. Phase Disposition PWM (PDPWM)
circuit as shown in Figure 3, is composed of only two PD method should be implemented with two different
switches in cascade and a submodule capacitor carrier sets for upper and lower arms in order to
paralleled to the switches. This simple and efficient construct the phase voltage in N+1 level. The carrier
structure allows the half-bridge circuit to dominate set has again N identical carriers with amplitude of
the others as the common submodule structure. Vdc/N and displaced contiguously in the Vdc band,
At any time, only one of the switches of half-bridge ranging from 0 to Vdc, Submodules in upper and
circuit should be ON. If S1 is ON and S2 is OFF, then lower arms are switched with the first and second
the half-bridge circuit is “switched on” or “inserted to carrier sets.
the current path”. Else if S1 is OFF and S2 is ON, then
the half-bridge circuit is “switched off” or B. Phase Opposition Disposition PWM
“bypassed”. The terminal voltage of half-bridge (PODPWM)
circuit is equal to the voltage across the submodule POD method should be implemented with a single
capacitor, Vc, if switched on/inserted or zero if carrier set for both upper and lower arms in order to
switched off/bypassed. If both of the switches are ON construct the phase voltage in N+1 level. Submodules
then the submodule capacitor is short-circuited. If in upper and lower arms are switched with this carrier
both of the switches are OFF then terminal voltage of set. Phase Opposition Disposition (POD) PWM
the submodule is undetermined and according to the where the carriers above the zero reference are in
direction of the current, different voltages may phase but shifted by 180° from those carriers below
appear at the terminals. Depending on the states of the zero reference.
half-bridge circuit and the direction of submodule
current, submodule capacitor is either charged or C. Alternate Phase Opposition Disposition PWM
discharged. (APODPWM)
In order to construct the phase voltage in N+1 level,
MULTI CARRIER PWM STRATEGIES FOR MMC APOD method should be implemented with a single
carrier set for both upper and lower arms. Alternative
Multi-Carrier PWM strategies is widely used, Phase Opposition Disposition (APOD) PWM where
because it can be easily implemented to low voltage each carrier band is shifted by 180° from the adjacent
modules.. The level shifted PWM (LS-PWM) are In band. also all the carriers have the same frequency
Phase Disposition (PD), Phase Opposition and the adjustable amplitude (different or unequal
Disposition (POD) and Alternative Phase Opposition Amplitudes).
Disposition (APOD). In general the amplitude SIMULATION RESULTS
modulation index (ma) for level shifted PWM
technique is defined as the ratio of amplitude of the In order to verify the modulation method, a three
reference sine wave (A r) to the amplitude of the phase MMC is simulated using Matlab/Simulink and
carrier wave (A c) and it is given in equation (1). its performance is studied for RL load.
2 Ar
ma Table 2 simulation parameters
(m 1) Ac (1) DC link voltage
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© April 2018 | IJIRT | Volume 4 Issue 11 | ISSN: 2349-6002
Carrier frequency
Reference frequency
Dc link capacitance of SM
Arm inductance
Frequency Index 20
Figure 8 Output voltage for 3 level MMC with PSC
M odulation Index 0.9 modulation technique
Load
Figure 9 FFT analysis &THD for 3 level MMC with
Figure 4 Output voltage for 3 level MMC with PD PSC modulation technique
modulation technique
Figure 10 FFT analysis &THD for MMC with PD
Figure 5 FFT analysis &THD for 3 level MMC with
modulation technique
PD modulation technique
Figure 6 Output voltage for 5 level MMC with PD Figure 11 FFT analysis & current THD for MMC
modulation technique with PD modulation technique
Figure 7 FFT analysis & THD for 5 level MMC Figure 12 Output current for MMC with PD
With PD modulation rechnique modulation technique
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© April 2018 | IJIRT | Volume 4 Issue 11 | ISSN: 2349-6002
Electron., vol. 26, no. 11, pp. 3119–3130, Nov.
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[2] M. Hagiwara, P. V. Pham, and H. Akagi,
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system during single-line-to-ground faults,”
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Figure 23 FFT analysis &THD for MMC with POD 698–706, Mar. 2008.
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with POD modulation technique IEEE transactions on power electronics. 2015
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