A WIDE-RANGE PLL USING PARALLEL COUNTER

BASED ON STATE LOOK-AHEAD LOGIC

Jesulin Rachel.J*,Shafiq Mansoor.J#

*III ME(VLSI Design),Karpagam University,Coimbatore.

#
Assistant Professor(ECE),Karpagam University,Coimbatore.

*jesulinrachel@[Link]

#
shafiqid@[Link]

Abstract— The variability and leakage current in to the clock. edge. The structure is scalable to arbitrary
nanoscale CMOS technology may degrade the circuit N-bit counter widths (2-to-N range) using only the three
performances significantly. To accommodate the above module types and no fan-in or fan-out increase. The
issues in a wide range phase-locked loop (PLL), a self- counter’s delay is comprised of the initial module access
healing prescaler, a self-healing voltage-controlled time, one three-input AND-gate delay and a D-flip-flop
oscillator (VCO), and a calibrated charge pump (CP) setup-hold time. The counter uses a 0.15 µm2 TSMC
are presented. This PLL is fabricated in a 65-nm CMOS digital cell library and verified maximum operating
technology and its active area is 0.0182 mm. For the speeds of 2 and 1.8 GHz for 8 and 17-bit counters,
self-healing VCO, its measured frequency range is from respectively. Finally, the area of a sample 8-bit counter
60 to 1489MHz. When this PLL operates at 855MHz, was 78 125 µm2 (510 transistors) and consumed
the measured Rms and peak-to-peak jitters are 8.03 and 13.89mW at 2 GHz.
55.6ps respectively. This PLL consumes 4.3mW from
Index Terms— Leakage current, nanoscale CMOS
1.2V supply without buffers. The proposed provides
technology, phased-locked loop (PLL). Architecture
several techniques to avoid the circuits to degrade by
design, high-performance counter design, parallel
the process variability and leakage current in nanoscale
counter design, pipeline counter design
CMOS technology. In addition, the active area and
power of this PLL will be increased because of these I. INTRODUCTION
self-healing circuits. To reduce the active area, a state
look ahead logic is used for counting in order to reduce When a CMOS technology approaches to a nanometer
the area of counter. A high speed wide-range parallel scale, the non-idealities such as variability and leakage
counter that achieves high operating frequencies current, may significantly affect the circuit performances.
through a novel pipeline partitioning methodology (a The process variability leads to the large variations to
counting path and state look-ahead path), using only degrade the device matching and performances. It may
three simple repeated CMOS-logic module types: an result in only a few dies on a wafer to meet the target
initial module generates anticipated counting states for performance specifications. The undesired leakage currents
higher significant bit modules through the state look- also degrade the accuracy and resolution of analog circuits
ahead path, simple D- flip-flops and 2-bit counters. The and make digital dynamic circuits not to work properly. A
state look-ahead path prepares the counting path’s next phase-locked loop (PLL) is widely employed in wire line
counter state prior to the clock edge such that the clock and wireless communication systems. The poor device
edge triggers all modules simultaneously, thus matching and leakage current vary the common-mode
concurrently updating the count state with a uniform voltage of a ring-based voltage-controlled oscillator
delay at all counting path modules/stages with respect (VCO)over a it’s wide frequency range. It may limit the
oscillation frequency range of a VCO and causes a VCO occur at the node A as shown in Fig. 2(b), respectively. The
not to oscillate in a worst case. To realize a wide-range first case is that the initial state of the node A is high;
PLL, the divider following a VCO should operate between
however, a leakage current discharges it to ground. The
the highest and lowest frequencies. When a PLL works at a
second one is that the initial state of the node A is low, but
higher frequency which the static circuits cannot operate,
a leakage current charges it to high. To consider the node B
dynamic circuits are needed. To deal with the process
in Fig. 2(a), assume that the leak
Variability and leakage current in nanoscale CMOS
process, a self-healing prescaler, a self-healing VCO and a age current charges the

calibrated charge pump are used. In addition, the active node B to be high when CK is high. It will not affect the
area and power of this PLL will be increased because of original state of the node Q. Thus, the leakage problem
these self-healing circuits. To reduce the active area, a state occurred at the node B is not considered here. For a
look ahead logic is used for counting in order to reduce the malfunction occurred at the node Q, the simplified circuit is
area of counter. shown in Fig. 2(c). Assume the transistor M1 is turned off,
CK is low, and the initial state of the node is low. Since the
[Link] DESCRIPTION node is floating, the leakage current from M1 may charge
A. Existing Method the node to high and a malfunction occurs. Note that the
leakage current through M2 and M3 is smaller than that
The PLL is composed of a phase-frequency detector
from M1. It is because the cascade transistors, M2 and M3,
(PFD), a digital-controlled CP, a lock detector (LD), a
induce a lower leakage current. To detect and heal the
time-to-digital converter (TDC) with a 4-bit encoder, a self-
above issues occurred at the nodes A and Q the proposed
healing VCO, a programmable divider, and a second-order
self-healing circuit is shown in Fig. 3(a).This self-healing
passive loop filter. The programmable divider is composed
circuit consists of a detector and three compensators. By
of a 5-bit counter, a 3-bit swallow counter, a modulus
using a self-healing circuit, the timing diagrams of a TPSC
control, and a self-healing divide-by-4/5 prescaler. When
DFF with and without a malfunction are shown Fig. 3(b).
this PLL locks, the LD is enabled to turn on the TDC and
Assume the signal Enable in the self-healing circuit
an encoder. A 4-bit TDC digitizes this static phase error to
is low to disable the latch in
reflect the amount of the current mismatching. Then, the
digital code of this TDC is used to calibrate the charge Fig 3(b). When the clock CK goes high, the pulse generator

pump. To deal with the process variability and leakage outputs a short pulse at the gate of M2A, which goes high

current in nanoscale CMOS process, a self-healing to clear DLK. When the input D of the DFF is high, the

prescaler, a self-healing VCO, and a calibrated CP are rising edge of the clock CK triggers the DFF’s output Q to

presented. Due to additional active devices, the jitter go high (or goes low) to turn off M3A. The pulse generator

performance of a self healing PLL will be degraded, outputs a low pulse at the gate of M1A to turn off M4A.
compared to a PLL without a self-healing technique. In Before the next rising edge of CK arrives, is assumed to be
addition, the active area and power of this PLL will be charged to high due to the undesired leakage current. In the
increased because of these self-healing circuits. meantime, Q goes low to turn on M3A and enables. It
a. Self-Healing Divide-by-4/5 Dual-Modulus Prescaler
indicates that the malfunction of this TSPC DFF occurs.
Fig. 2(a) shows a conventional divide-by-4/5 dual- The size ratio of M4A and M3A is 5 to ensure, when both
modulus prescaler using TSPC DFFs. The undesired M3A and M4A are turned on. For a case that the
leakage current may charge or discharge to alter the states malfunction is fixed, the timing diagram is shown in the
of the nodes A, B, and in this TSPC DFF as shown in right-hand side of Fig. 3(b) where is always low. In Fig.
Fig. 2(a). For example, two kinds of the malfunctions may 3(a), when the signal Enable is high and the malfunction is
detected, DLK=1 is latched by latch and the Compensator
is active.

Fig.2. (a) Self-healing circuit and (b) timing diagrams of a TPSC

DFF with and without a malfunction by using a self-healing
Fig.1. (a) Conventional divide-by4/5 dual-modulus prescaler (b) circuit.
Two kinds of malfunctions occurred at A. (c) The malfunction
occurred at Q.

b. Self Healing VCO

A self-healing VCO is realized by four gain dependent upon the process variations. For example, when
stages, a bottom level Detector and a current compensator. the resistances of M3 and M4 are decreased, the oscillation
Fig. 4(a) shows a bottom-level detector, a current frequency of this VCO is increased. It will result in the
compensator, and a gain stage. This gain stage consists of a output swing decreased and the bottom level is increased. It
differential amplifier with active loads and a cross-coupled also leads to a limited oscillation frequency range. If a
pair with digitally-controlled current sources. In the larger biasing current and the cross-coupled pair with larger
differential amplifier, the transistors,M1 and M2 realize dimensions are selected for this VCO, the output swing can
the input stage, and the transistors, M3 and M4 , act as a be increased. However, it may waste the power when the
operation frequency of this PLL is low. In this work, the
variable resistor controlled by Vctrl. The cross-coupled
self-healing VCO using a bottom-level detector can achieve
pair, M5 and M6, enhances the output swing of this VCO.
a wide tuning range and low power. The bottom-level
The output common-mode voltage and the output swing of
detector is shown in Fig. 4(b) and it detects the bottom
the VCO are altered by the leakage currents, the total tail
level of the VCO’s output swing. A self-biased buffer
currents, and the resistances of M3 and M4 . They are
enlarges the output of a VCO into a rail-to-rail swing. So,
the output Vbuf , of this self-biased buffer and VOUT+ steady state, the voltage on the capacitor, , will track the
have the same polarity. When VOUT+ goes high and Vbuf bottom level of the VCO’s swing. For the current
is high, the NOR gate will enable MB1 and disable MB2, compensator in Fig. 4(a), a reference voltage represents the
respectively. The current of the transistor will charge the target bottom level of the VCO’s swing and it is compared
capacitor to increase Vbl, When VOUT goes low and Vbuf by a comparator. When the VCO’s bottom level is smaller
is low, two cases will be discussed. In Fig. 4(b), if the than the target one or the output common-mode voltage of
bottom level of VOUT+ is larger than VBL , the this VCO is high enough, is larger than . Then, the output
comparator’s output goes high and the NOR gate goes low of the comparator goes high and enables Q1. The current
to enable MB1 and disable MB2 , respectively. The compensator enables the auxiliary tail current to lower the
transistor will charge the capacitor to increase. For the output common-mode voltage. The timing diagram is
other case, if the bottom level of is lower than ,the shown in Fig. 4(b). Then, it reduces the VCO’s bottom
comparator’s output goes low and the NOR gate goes high level to be lower than. If the above case is not true, Q2 will
to disable MB1 and enable MB2, respectively. The be enabled and turn on the auxiliary tail current. It further
transistor will discharge the capacitor, , to decrease . In the lowers the VCO’s Bottom level.

the active area, a state look ahead logic is used for counting
in order to reduce the area of counter.

Fig.3 Existing PLL

b. Proposed Method

To deal with the process variability and leakage current in

nanoscale CMOS process, a self-healing prescaler, a self-
healing VCO and a calibrated charge pump are used. In
addition, the active area and power of this PLL will be
increased because of these self-healing circuits. To reduce
 Fig. 4(a) Gain stage, a bottom-level detector, and a current
compensator, and (b) the bottom-level detector

B. Parallel counter: and propagation delays such as register load time, AND
Counters are widely considered as essential building logic chain decoding, and the half incrementer component
blocks for a variety of circuit operations such as delays in half adders dictated operating frequency.
programmable frequency dividers, shifters, code Subsequent methodologies improved counter operating
generators, memory select management, and various frequency using half adders in theparallel counting modules
arithmetic operations. Since many applications are that enabled carry signals generated at counting modules of
comprised of these fundamental operations, much research lower significance to serve as the count enable for counting
focuses on efficient counter architecture design. Counter modules of higher significance, essentially implementing a
architecture design methodologies explore tradeoffs carry chain from modules of lower significance to modules
between operating frequency, power consumption, area of higher significance. The carry chain cascaded
requirements and target application specialization. Early synchronously through intermediate D-type flip-flops
design methodologies improved counter operating (DFFs).The maximum operating frequency was limited by
frequency by partitioning large counters into multiple the half adder module delay, DFF access time, and the
smaller counting modules, such that modules of higher detector logic delay.
significance (containing higher significant bits) were
enabled when all bits in all modules of lower significance 1) A single clock input triggers all counting modules
(containing lower significant bits) saturate. Initializations simultaneously, resulting in an operating frequency
independent of counter width (assuming ideal parasitic A. Architectural Functionality
capacitance on the clock wire path, without loss of The counting path’s counting logic controls counting
generality). The total critical path delay (regardless of operations and the state look-ahead path’s state look-
counter width) is uniform at all counting stages and is equal ahead logic anticipates future states and thus prepares the
to the combination of the access time of a 2-bit counting counting path for these future states. Fig. 1 shows the three
module, a single three-input AND gate delay, and the DFF module types Module-1 and module-3 are exclusive to the
setup-hold time. counting path and each module represents two counter bits.
Module-2 is a conventional positive edge triggered DFF
and is present in both paths. In the counting path, each
2) Our parallel counter architecture leverages modularity, module-3 is preceded by an associated module-2. Module-
which enables high flexibility and reusability, and thus 3’s serve two main purposes. Their first purpose is to
enables short design time for wide counter applications. generate all counter bits associated with their ordered
The architecture is composed of three basic module types position and the second purpose is to enable (in conjunction
separated by DFFs in a pipelined organization. These three with stimulus from the state look-ahead path) future states
module types are placed in a highly repetitious structure in in subsequent module-3 ’s (higher values) in conjunction
both the counting path and the state look-ahead paths, with stimulus from the state look-ahead path.
which limits localized connections to only three signals 1) Counting Path:
3) The counter output is in radix-2 representation so the Module-1 is a standard parallel synchronous binary 2-
count value can be read on-the-fly with no additional logic bit counter, which is responsible for low-order bit
decoding. counting and generating future states for all module-3
4) Unlike previous parallel counter designs that have count in the counting path by pipelining the enable for these
latencies of two or three cycles, depending on the counter future states through the state look-ahead path. Fig. 3
width, our parallel counter has no count latency, which depicts the (a) hardware schematic and (b) state
enables the count value to be read on-the-fly. The counter diagram for module-1. Module-1 outputs (the
is partitioned into modules of higher significance are
enabled The architecture functionality is as follows
counter’s two low-order bits) and (the 1 in denotes lengthy AND-gate rippling and large AND gate fan-in
that this is the for module-1). Connects to the module- and fan-out typically present in large width parallel
2’s input. The placement of module-2s in the counting counters.
path is critical to the novelty of our counter structure. 2) State Look-Ahead Path:
Module-2s in the counting path act as a pipeline The state look-ahead path operates similarly to a carry
between the module-1 and module-3 1 and between look-ahead adder in that it decodes the low order count
subsequent module- s. Module-2 placement increases states and carries this decoding over several clock
counter operating frequency by eliminating the cycles in order to trigger high-order count states.

fig.5 Functional block diagram of parallel counter

[Link] RESULTS:

[Link]:

To deal with the process variability and leakage current in

nanoscale CMOS process, a self-healing prescaler, a self-
[Link] topology
healing VCO, and a calibrated CP are presented. In
addition, the active area and power of this PLL will be
increased because of these self-healing circuits. To reduce
the active area, a state look ahead logic is used for counting
in order to reduce the area of counter. A high speed wide-
range parallel counter that achieves high operating
frequencies through a novel pipeline partitioning
methodology (a counting path and state look-ahead path),
using only three simple repeated CMOS-logic module
types thus reducing the area of the counter.

[Link]

[1][Link]-Hafeez, [Link], and [Link], [4] A. Bellaour and M. I. Elmasry, Low-Power

“HighspeeddigitalCMOS divide-by-N frequency Digital VLSI Design Circuits and Systems. Norwell,
divider,” in Proc. IEEE Int. [Link] Syst. MA: Kluwer, 1995.
(ISCAS), 2008, pp. 592–595. [5] J. Ousterhout, Berkeley, 1980, “Berkley magic
[2] M. Alioto, R. Mita, and G. Palumbo, “Design of layout tools,” 1980.
high-speed power-efficient [6] A. Fard and D. Aberg, “A novel 18 GHZ
MOS current-mode logic frequency dividers,” IEEE 1.3mWCMOS frequency dividerwith high input
Trans. Circuits Syst. II, Expr. Briefs, vol. 53, no. 11, sensitivity,” in Proc. Int. Symp. Signals, Circuits,
pp. 1165–1169, Nov. 2006. Syst., Jul. 2005, pp. 409–412.
[3] Altera Corp., Santa Clara, CA, “FLEX8000, field [7] C. Foster and F. Stockton, “Counting responders
programmable gatearray logic device,” 2008. in an associative memory,” IEEE Trans. Comput.,
vol. 20, no. 12, pp. 1580–1583, Dec. 1971
 IEEE Wposium on Compuler Arithmetrc, 1991, 180-
[8] D. C. Hendry, “Sequential look ahead method for 183.
digital counters,” [l0] P. Larsson and 1. Yuan, ‘Wove1 carry
IEEE Electron. Lett., vol. 32, no. 3, pp. 160–161, propagation in high speed synchronous counters and
Feb. 1996. divide;,” IEEE Electronic Letters, vol. 29, no. 16, pp.
[9] I.E. Vuillemin “Constant Time Arbitrary Length 1457-1458,1993.
Synchronous Binary Counters,” in Proc. of the 10th