Assignment

Serial No Question Marks

1 Design an odd parity generator and checker for a system with 4 (four) 5+10+5+10
data bits, using Karnaugh Maps (K-map) to minimize the logic. Derive
the truth table for both the generator and checker, where the generator
ensures the total number of '1's, including the parity bit, is odd, and the
checker validates the parity with an error for invalid parity. Simplify
the logic equations for the parity bit and error using K-map
minimization, and draw the corresponding logic diagrams. Also,
implement the simplified logic equations using NAND (universal) gate.

Instructions:
1. This is for those who missed the Lab Test and Lab Viva.
2. Submit in .pdf format.