Question bank:Advanced VLSI

Module 1

Introduction to ASICs

1. Define and differentiate between full custom, semi-custom, and programmable

ASICs. In what scenarios might each type be preferred?
2. Describe the ASIC design flow from specification to tape-out. Explain the key stages
and the importance of each in ensuring functional and efficient ASICs.
3. Explain the purpose and structure of ASIC cell libraries. How do these libraries
contribute to design standardization and optimization in ASIC development?
4. Discuss the challenges involved in designing a robust cell library for ASICs. What
factors are crucial for library design, and how are these libraries validated?

5. Discuss the role of data path elements in CMOS logic design. What considerations
must be made when selecting or designing these elements for an ASIC?
6. Explain the design and function of carry skip, carry bypass, carry save, carry select,
and conditional sum adders. Compare their performance trade-offs and identify
which types are most suitable for high-speed applications.
7. Describe the Booth encoding algorithm used in multiplier design. How does it
improve the efficiency of multiplication in digital circuits?
8. Discuss the key types of data path operators used in CMOS logic. How are these
operators optimized to meet specific speed and area requirements in ASICs?
9. What role do I/O cells play in ASICs, and what types of functionality do they
provide? Discuss some of the challenges associated with designing I/O cells.
10. Explain the concept of cell compilers in ASIC design. How do cell compilers
contribute to the automation and flexibility of creating custom cells in a design?

Module 2

Floor Planning and Placement

1. Explain the main goals and objectives of floor planning in ASIC design. Why are
these critical in the physical design process?
2. Describe the different methods used for measuring delay during floor planning.
How does delay measurement impact the design decisions?
3. Discuss the significance of I/O and power planning in ASIC floor planning. What
challenges might arise if these are not properly planned?
4. What role does clock planning play in floor planning? Describe methods to ensure
optimal clock planning in a complex ASIC layout.
5. Compare and contrast floor planning tools commonly used in ASIC design. What
are the main features that differentiate them?
 6. Outline the primary goals and objectives of placement in the physical design of
ASICs. How does it differ from floor planning?
7. Describe the min-cut placement algorithm and its application in physical design.
What are its advantages and potential drawbacks?
8. Explain the concept of iterative placement improvement. How does this method help
refine the initial placement in ASIC design?
9. Define time-driven placement methods and discuss their importance in timing-
sensitive ASIC applications. How are timing constraints incorporated in this
approach?
10. Explain the overall role of placement within the physical design flow of ASICs. Why
is correct placement crucial before routing?

11. Discuss the goals and objectives of global routing in ASIC design. Why is global
routing a necessary step before detailed routing?
12. Explain different global routing methods. How do these methods handle congestion
and ensure efficient signal flow?
13. Describe the process of global routing between blocks. What factors must be
considered to avoid bottlenecks in this phase?
14. What is back annotation, and why is it critical in the ASIC design process? Describe
how back annotation is used to verify and optimize design accuracy.

Module 3

Verification Guidelines

1. Describe the verification process in ASIC design. What are the primary goals of
verification, and how does it contribute to the overall design cycle?
2. Explain the basic functionality of a test bench in verification. What are its essential
components, and how does it simulate real-world scenarios for the ASIC?
3. What is directed testing in the context of ASIC verification? Compare it with
constrained random testing and discuss when each method is most effective.
4. Outline the basic principles of verification methodology. Why is it important to
follow a structured verification methodology in large-scale ASIC projects?
5. Define constrained random stimulus in verification. How does it improve test
coverage, and what role does randomization play in detecting edge-case issues?
6. Discuss the concept of functional coverage in verification. How does it differ from
code coverage, and why is it essential for verifying ASIC functionality?
7. List and describe the various test bench components in a layered test bench. How
does each component contribute to the overall testing framework?
8. Explain the concept of a layered test bench. How does layering improve the
reusability and scalability of verification code?

Data Types
 9. Describe the built-in data types commonly used in ASIC verification. What are their
roles, and how are they chosen based on application requirements?
10. Differentiate between fixed and dynamic arrays. What are the advantages of using
dynamic arrays in verification environments?
11. Explain the purpose and use of queues, associative arrays, and linked lists in ASIC
verification. How do these data structures enhance data handling within test
benches?
12. Discuss array methods and their applications in managing data structures. Give
examples of some commonly used methods and their advantages in handling large
data sets.
13. Explain the process of choosing the right data type in verification. What factors are
considered when selecting a type for efficient data management?
14. Describe how typedef is used to create new types in ASIC verification. Why is it
helpful to define new types for complex verification projects?
15. Discuss the importance of user-defined structures in verification. How are
structures used to group related data, and what are the benefits?
16. Explain the significance of type conversion in verification. Provide examples of
when type conversion is necessary and its impact on simulation accuracy.
17. Describe enumerated types and their use cases in verification. How do enumerated
types improve code readability and maintainability?
18. What roles do constants and strings play in ASIC verification? Explain how each is
applied within a test bench to streamline data handling.
19. Discuss the importance of expression width in verification. How does expression
width affect performance and accuracy in simulation?

Module 4

Procedural Statements and Routines

1. Define procedural statements in SystemVerilog. How do they differ from continuous

assignments, and what roles do they play in simulation?
2. Explain the differences between tasks, functions, and void functions in
SystemVerilog. When should each be used within a test bench or design?
3. Provide an overview of tasks and functions in SystemVerilog. Describe their main
characteristics and discuss how they enhance modularity and code reusability in
verification.
4. Discuss the role of routine arguments in tasks and functions. How are arguments
passed, and what are best practices for using arguments to improve readability?
5. Describe how returning from a routine works in SystemVerilog. How does the
return mechanism differ between tasks and functions?
6. Explain the concept of local data storage within tasks and functions. Why is local
storage important, and how does it affect the behavior of routines in a test bench?
7. Discuss the use of time values in procedural statements. How do time values
influence simulation timing, and why are they crucial in ASIC verification?

Connecting the Test Bench and Design

 8. Explain the importance of separating the test bench from the design in verification.
What are the advantages of keeping these components isolated?
9. Describe the purpose and structure of the interface construct in SystemVerilog.
How does it facilitate communication between the test bench and the design under
test (DUT)?
10. Discuss the significance of stimulus timing in test benches. How does proper timing
control impact the accuracy of verification?
11. Explain interface driving and sampling in SystemVerilog. How do these processes
support effective signal communication between the test bench and the design?
12. Define SystemVerilog assertions and discuss their role in verification. How do
assertions help in identifying functional errors and enhancing test coverage?
13. Describe how to implement and use assertions in a test bench. What types of issues
can assertions detect, and how do they improve verification quality?

Module 5

1. Explain the concept of randomization in verification. Why is randomization crucial

in verifying complex ASIC designs?
2. Describe what aspects of a design should be randomized for effective verification.
How does selecting the right parameters impact coverage and bug detection?
3. Discuss how randomization is implemented in SystemVerilog. What features does
SystemVerilog provide to facilitate controlled random testing?
4. Explain the role of random number functions in SystemVerilog. How are these
functions used to generate diverse test scenarios, and what limitations might they
have?
5. Identify and discuss some common problems encountered during randomization.
How can these issues be mitigated in a test bench?
6. Describe the function and importance of random number generators in a
verification environment. How do random number generators contribute to
achieving unbiased and varied test cases?

Functional Coverage

7. Define functional coverage and explain its importance in the context of ASIC
verification. How does functional coverage differ from code coverage?
8. Describe the different types of coverage used in functional verification. How does
each type provide insight into the design’s performance and functionality?
9. Outline some common strategies used for achieving effective functional coverage.
How does choosing an appropriate coverage strategy impact verification quality?
10. Provide a simple example of a coverage group in SystemVerilog. What are the
essential components of a cover group, and how does it track verification metrics?
11. Explain the process of triggering a cover group in SystemVerilog. Why is triggering
important, and how does it influence the accuracy of coverage data?
12. Discuss the concept of data sampling in functional coverage. How does data
sampling affect the precision of coverage measurements?
13. Define cross coverage and explain its significance in complex verification
environments. What insights can cross coverage provide that individual coverage
points cannot?
14. Describe generic cover groups and their use in verification. How do generic cover
groups increase flexibility and reusability in a test bench?
15. Discuss the various coverage options available in SystemVerilog. How do these
options allow engineers to tailor coverage goals for specific verification needs?
16. Explain how coverage data is analyzed post-simulation. What metrics are most
commonly used, and how do they indicate the thoroughness of verification?
17. Describe how to measure coverage statistics during simulation. How do these
statistics help identify gaps in test scenarios and improve overall test coverage?
 USN

YENEPOYA INSTITUTE OF TECHNOLOGY

NH-13, Thodar, Moodbidri- 574225 , Mangaluru, D.K.
I Internal Assessment Test Question Paper

Program: ECE Semester: VII

Course Title: VLSI DESIGN Course Code: 21EC71
Duration: 1 Hour Max Marks: 30
Date: 08/10/2024 Time: 09:30AM

Answer any TWO full questions, choosing one full question from the Following:

Question Questions Marks CO Bloom

Number Taxonomy
Level
1 a) Illustrate the ASIC Design Flow with relevant flow 8 1 3
diagram.

b) Discuss with relevant figures the functioning of 7 1 3

Standard- Cell based ASICs

OR
2 a) With a neat classification diagram, classify the ASIC 8 1 3
family and explain Full Custom ASIC in detail.

b) Discuss with relevant figures the classifications of 7 1 3

Programmable ASICs.

-----------------------
3 a) Discuss about all the three classifications of Gate- 8 1 3
Array based ASICs with relevant diagrams.

b) Write a note on ASIC Cell Libraries. 7 1 3

OR
4 a) What is a Data Path Logic Cell? With all the relevant 8 1 3
diagram explain the implementation of n- bit Ripple
Carry Adder using Data Path Logic Cells.

b) With required diagrams demonstrate the working of 7 1 3

three- state bidirectional output buffer.
 ANSWER SCHEME- I Internal Assessment Test
Program: ECE Semester: VII
Course Title: ADVANCED VLSI DESIGN Course Code: 21EC71
Date : 08/10/2024 Max Marks: 30
Course Coordinator: Dr. Shashank M Gowda
Question Solution Marks
Number Allocated
1 a) Illustrate the ASIC Design Flow with relevant flow diagram.

Explanation about each stage of the ASIC Design flow. 5

8 Marks

Question Solution Marks

Number Allocated
1 b) Discuss with relevant figures the functioning of Standard- Cell based ASICs
• Standard-Cell based ASICs (CBIC- “sea-bick”)
• Use predesigned logic cells AND, OR Gates, MUX, and Flip- Flops
• mega-cells (Microcontroller or Microprocessors)
• full-custom blocks
• System- Level Macros (SLMs)
• Functional Standard Blocks (FSBs)
• Cores etc
• Called standard cells or Standard cell libraries
2
• time, money, and reduce risk
• using a predesigned, pretested, and precharacterized standard-cell library.
• Get all mask layers customized- transistors and interconnect
• Manufacturing lead time is about 8 weeks
• Custom blocks can be embedded
 2

7 Marks

Question Solution Marks

Number Allocated
2a) With a neat classification diagram, classify the ASIC family and explain Full
Custom ASIC in detail.

4
Explanation about the full Custom ASIC design

8 Maks
Question Solution Marks
Number Allocated
2 b) Discuss with relevant figures the classifications of Programmable ASICs.
• Programmable logic devices ( PLDs )
▪ Standard ICs that are available in standard configurations
▪ Sold in very high volume to many different customers
• PLDs may be configured or programmed to create a part customized to a specific
application
• They belong to the family of ASICs
• important features that all PLDs have in common:
• No customized mask layers or logic cells
• Fast design turnaround time
3
• A single large block of programmable interconnect
• A matrix of logic macrocells that usually consist of programmable array logic
followed by a flip-flop or latch
• PLD Types
• PAL (Programmable Array Logic),
• PLA (Programmable Logic Array),
• Programmable Array Logic (PAL)
• Contains a programmable array of AND gates and a fixed array of OR gates.
• Good for simpler, specific tasks where you don't need too much flexibility.
• Programmable Logic Array (PLA)
• Consists of two programmable arrays: AND gates followed by OR gates.
• Good for complex tasks where you need more customization

7 Marks
Question Solution Marks
Number Allocated
3 a) Discuss about all the three classifications of Gate- Array based ASICs with
relevant diagrams.
Types of MGA or gate- array based ASICs
1
• Channeled Gate Array
• Channelless Gate Array
• Structured Gate Array

2
Relevant Explanation related to gate array types.
8 Marks
Question Solution Marks
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3 b) Write a note on ASIC Cell Libraries.

◼ Key part of ASIC design

◼ For a programmable ASIC
◼ FPGA company supplies with a library of logic cells as Design Kits

◼ For MGAs and CBICs there are three choices

◼ ASIC vendor will supply a cell library 3
◼ Buy a cell library from a third-party library vendor
◼ Build your own cell library

◼ ASIC vendor library is normally a phantom library

◼ The cells are empty boxes, or phantoms, but contain enough
information for layout
◼ After the layout is completed, the netlist is sent to the ASIC vendor
◼ ASIC vendor fills in the empty boxes before manufacturing the chip.
◼ Requires you to use a set of design tools approved by the ASIC vendor to
enter and simulate your design
◼ Tools prescribed by the vendor has to be purchased
◼ Some vendors provide in-house developed tools
3
◼ Buying a Cell Library
◼ You purchase a cell library from a third-party vendor.
◼ The library is often developed using specs provided by an ASIC
foundry
◼ a company that only manufactures the chip but doesn’t help
with design.

◼ Building Your Own Library

◼ You can create your own custom cell library, but it requires significant
design effort.

◼ Each cell in an ASIC cell library must contain the following:

◼ A physical layout
◼ A behavioral model
◼ A Verilog/VHDL model 1
◼ A detailed timing model
◼ A test strategy
◼ A circuit schematic
◼ A cell icon
◼ A wire-load model
◼ A routing model 7 Marks
Question Solution Marks
Number Allocated
4 a) What is a Data Path Logic Cell? With all the relevant diagram explain the
implementation of n- bit Ripple Carry Adder using Data Path Logic Cells.

◼ Data path logic cells are fundamental building blocks in digital systems
◼ Performs arithmetic and logical operations on data.

◼ They are essential for the functionality of processors and other digital
devices
◼ Operations such as addition, subtraction, and data routing. 3

◼ Examples:
◼ Arithmetic Logic Units (ALUs): Combine multiple data path
logic cells to perform a variety of arithmetic and logical
operations.
◼ Registers: Temporary storage locations that hold data being
processed
◼ Adders: Used for performing addition operations.
◼ Multiplexers (MUX): Allow selection of data from multiple
sources.
◼ Shifters: Enable bit manipulation through shifting operations.

8 Marks
Question Solution Marks
Number Allocated
4 b) With required diagrams demonstrate the working of three- state bidirectional
output buffer.

When the output enable (OE) signal is high, the circuit functions as a
noninverting buffer driving the value of DATAin onto the I/O pad. When OE 2
is low, the output transistors or drivers , M1 and M2, are disconnected. This
allows multiple drivers to be connected on a bus.

The three-state buffer allows us to employ the same pad for input and output
bidirectional I/O . When we want to use the pad as an input, we set OE low
and take the data from DATAin.

To protect the I/O cells from ESD, the input pads are normally tied to device 2
structures that clamp the input voltage to below the gate breakdown voltage
(which can be as low as 10 V with a 100 Å gate oxide). Some I/O cells use
transistors with a special ESD implant that increases breakdown voltage and 7 Marks
provides protection.