SRI VENKATESWARA COLLEGE OF

ENGINEERING
(AUTONOMOUS)
Karakambadi Road, TIRUPATI – 517507

Question bank

Name of the
Branch/Course [Link] (ECE)
Subject DIGITAL CIRCUITS DESIGN
Subject Code EC23APC301
Year & Sem II-I
10 Marks Questions

Unit – 1

Convert the following numbers:

i. (4567)8 to base 10.

1 ii. (11001101.0101)2 to base 8 and base 4.

iii. (53.1575)10 to base 2.
iv. (1AC.D)16 to base 8.
a) Convert the following to binary and then to gray code:

2 i. (AB33)16
ii. (1764)8
Perform the following operations using 2’s complement method:

3 i. (+55) – (+15)
ii. 110110 – 110011
Reduce the following expressions
4 i. F 1=ABC + A ’ B+ ABC ’
ii. F 2=xy + x (wz+ wz ’)
Implement the following Boolean equation using only NAND gates
5
Y = AB+CDE+ F .
a) State and prove the De-Morgan’s Theorem with truth tables.
6
b) State and prove the Consensus theorem.
a) Implement the Boolean function F= A(B+CD )+ BC ' using only NOR
gates.
7
b) Convert the given equation Y = AB+ AC '+ BC into Canonical SOP
form.
Simplify the function F(A,B,C,D)=∑m(1,3,5,8,9,11,15)+d(2,13) using

8 K-map. Obtain the real minimal expression and implement with

Universal logic.
9 Minimize the function using k-map and obtain minimal POS function?
 F ( A , B ,C , D )=Π ( 1, 2 , 3 , 4 , 6 , 9 , 10 ,12 , 14 ) . d (5 , 7 ,11). And implement with
NOR gates.
Simplify the following using K-maps:

10 F ( A , B ,C , D )=∑ ( 0 , 1 , 4 , 5 ,7 ,8 , 10 , 13 ) +∑ d (2 , 6) And realize the circuit

using NAND gates.

Unit – 2

1 Design BCD adder and explain the operation.

a) Design a 4-bit adder/subtractor circuit and explain the operation
in detail.
2
b) Implement a 2-bit Magnitude comparator and write down its
design procedure.
Implement a 4-bit Magnitude comparator and write down its design
3
procedure.
Draw and explain the working of a carry-look ahead adder with
4
necessary equations.
a) Design the 2 × 2 binary multiplier with neat diagram.
5
b) What is Priority Encoder? Design 4 input Priority Encoder.
a) Design the 4 to 16 line decoder by using 3 to 8 decoders.

6 b) Design Octal to Binary Encoder and explain the operation in

detail.
a) Design the 4:1 MUX and explain its operation in detail.
7
b) Discuss the difference between Decoder and De-multiplexer.
Implement the following function F(A,B,C,D)=Σ(0,1,3,4,7,10,12,14)
8
using (i) 16:1 MUX and (ii) 8:1 MUX
a) Implement the following Boolean functions using decoder and OR
gates. F1 (A, B, C, D) = Σ (1, 5, 7, 9). F2 (A, B, C, D) = Σ (12, 13, 14,

9 15).
b) Design 32:1 MUX using 8:1 MUX with necessary truth tables and
equations.
a) Design 1:8 De-MUX with 1:2 and 1:4 De-MUX.
10
b) Write the difference between Multiplexer and De-multiplexer.

Unit – 3

Design and Write the Verilog code for Full adder using Case
1
statements and Gate level modeling.
Design and Write the Verilog code for 3 to 8 decoder using
2
Behavioral level modeling and Data flow level modeling.
3 a) Write Verilog code for 4-bit adder/subtractor.
 b) Implement a full adder and write Verilog code using Hierarchical
model.
a) Write the Syntax of Case statements and Verilog code for 2:1
MUX using Case statements.
4
b) Write the syntax of If-else statements and Verilog code for a 4-bit
magnitude comparator using the If-else statements.
a) Write the syntax for Conditional operator and Verilog code for a
4:1 MUX using conditional operator & Case statements.
5
b) Write the syntax of For loop and Verilog code for 4-bit binary
multiplier using for loop.
Write Verilog code for 64:1 MUX using 8:1 MUX by using Hierarchical
6
model.
a) Write the Verilog code BCD to 7 segment decoder.
7
b) Write Verilog code for 4:2 Priority Encoder using case statements.
Design and Write the Verilog code for Full Subtractor using Gate
8
level and Behavioral level modeling.
9 Write the Verilog code for 4-bit comparator using If-else statements.
10 Design and Write the Verilog code for 1:4 De-MUX.

Unit – 4

Describe the operation of universal shift register with neat block

1
diagram.
Explain in detail about the Positive edge-triggered SR Flip Flop with
2
necessary diagrams along with Verilog code.
Explain in detail about the Negative edge-triggered JK Flip Flop with
3
necessary diagrams along with Verilog code.
Explain in detail about the Positive edge-triggered D Flip Flop with
4
necessary diagrams along with Verilog code.
Determine the characteristic table and an excitation table for JK, D
5
and T Flip flop.
6 Convert the SR flip flop to JK flip flop.
7 Examine a synchronous MOD-8 counter and explain the operation.
Using D flip-flop, Design a synchronous counter which counts in the
8
sequence 000,001,010,011,100,101,110,111,000.
9 Design Asynchronous 3-bit Up/Down counter.
10 Design a 4-bit Ring counter using D-flip flops and write Verilog code.

Unit – 5
1 Implement binary to excess 3 code converter using PROM.
Implement the following functions using a PROM

2 i) F(w,x,y,z)=∑m(1,9,12,15)
ii) G(w,x,y,z)=∑m(0,1,2,3,4,5,7,8,10,11,12,13,14,15)
Implement the following functions using a PLA

3 i) f1(w,x,y)=∑m(3,5,6,7)
ii) f2(w,x,y)=∑m(0,2,4,7)
Generate the following Boolean function with PAL with 4 inputs and
4 outputs
Y3= a’bc’d+a’bcd’+abc’d
4
Y2=a’bcd’+a’bcd+abcd
Y1=a’bc’+a’bc+ab’c+abc’
Y0=abcd
5 Draw and Explain the Basic Architecture of CPLD in detail.
6 Draw and Explain the Basic Architecture of FPGA in detail.
Design a clocked sequential machine using JK flip flop for the
following state table diagram. Use the state reduction procedure if
possible.

A sequential circuit has one input and one output. The state diagram
is shown below: Design a circuit with SR flip-flop.

9 Design Sequence detector 101 using Mealy machine.

10 Design Sequence detector 1001 using Moore machine.

2 Marks Questions

Unit – 1
1 State De-Morgan’s theorem.
2 Express the function Y=A+B’C in canonical POS.
3 Outline the concept of duality in Boolean algebra.
Convert the given decimal numbers to their binary equivalent
4
108.364.
Simplify the following Boolean expression into one literal.
5
W’X (Z’+YZ) + X (W+Y’Z).
6 Convert (115)10 and (235)10 into octal and hexadecimal numbers.
7 Show how to connect NAND gates to get an AND gate and OR gate?
Implement the given function using NAND gates only.
8
F(X, Y, Z) =∑m(0,6).
9 Find the equivalent Gray code for [10110]2 .
Determine the Boolean expression for the output of the system
shown in figure.

10

Unit – 2

1 Determine the Boolean expression for a half adder and full adder
2 How do you draw a Half subtractor and full subtractor circuit?
3 Implement full adder using half adders.
4 State the concept of parallel binary adder.
5 Compare the function of decoder and encoder.
Obtain the design of the given function using suitable multiplexer
6
F= Σm(0,2,5,7).
Outline the characteristics of a priority encoder and how it differs
7
from a regular encoder?
8 Design a 4:1 Multiplexer using 2:1 MUX
9 How does a 1-bit comparator work?
10 Draw and explain 2 bit Multiplier.

Unit – 3

1 What is Verilog? Name the types of ports in Verilog

What is the difference between blocking and non-blocking in
2
Verilog?
3 What is the difference between == and === in Verilog?
4 What are the main differences between Wire and Reg?
5 What is the structure of combinational circuits
6 What are the various levels of modelings available in Verilog code?
7 Define IF-ELSE statement.
8 List Verilog operators.
9 Give the syntax for behavioral modeling of a Verilog Code.
10 List the behavioral specification of logic circuits

Unit – 4

1 List the classification of Sequential circuits.

2 Prepare the truth table for JK Flip flop.
3 Construct the state diagram of Mod-10 ring counter.
4 Draw the circuit diagram of Johnson Counter.
How many flip-flops are required to build a binary counter that
5
counts from 0 to 7?
6 Summarize the excitation table of JK FF, T FF and D FF.
7 Analyze the differences between Latch and Flip-Flop.
Examine how does a ripple counter differ from a synchronous
8
counter?
9 Determine the characteristic table and an excitation table
10 Summarize 4-bit SISO SIPO, PIPO and PISO shift register.

Unit – 5

1 Write the difference between PROM and PLA. Also list the types of
ROMs.
2 Distinguish between PAL and PLA.
3 Define Mealy Machine.
4 Define Moore Machine.
5 Define the term "state table".
6 Integrate the realization of Ex OR function into the PROM.
7 Compare between PROM, PLA and PAL.
8 Define FPGA.
9 Give the difference between CPLD and FPGA.
10 What are the advantages of FPGAs?