E2.
1 – Digital Electronics II
Solutions to Problem Sheet 2 – Counters & Shift Registers (Lecture 5)
(Question ratings: A=Easy, …, E=Hard. All students should do questions rated A, B or C as a minimum)
1B. Z = Q2•Q1•~Q0. Note that (a) Q2 is always the MSB and (b) we must include the ~Q0 term.
Glitches in Z are possible for the transitions 3→4 and 7→0.
CLOCK
Q0:2 0 1 2 3 4 5 6 7 0
Z
2C. The XOR gate goes high twice per cycle whereas the more complicated circuit only goes high once
per cycle. The advantage of the complicated circuit is that it covers a full 360° monotonically.
A
B
X
Y
5V 5V
X Y
0V 0V
0° 180° 360° 0° 180° 360°
3B. Z = B ⊕ C + ~D • E
Note that since this expression does not involve A, it will be glitch-free/
4C. The output of the first shift-register stage can go metastable if D↑ occurs just before the CLOCK↑
edge. This will only affect the P output because Z will be low at the time which will force Q low
regardless of X.
The average time delay between GO↑ and Q↑ will be 2½ clock periods.
CLOCK
GO
D
X
Y
Z
P=X⊕Y
Q=X•Z
Rev: Oct 2016 E2.1 Digital Electronics II – Solutions to Problem Sheet 2 Page 1
5C. The P input of the adder equals 7 when Q is 9, 11, 13 or 15. For all other values of Q it equals 1.
Bearing in mind that the adder result is modulo 16 (i.e. 10+7=1), this results in the following state
diagram:
1 2 3 4 5 6
0 10 11 12 13 14 15 7
9 8
6C. We want to make 10 the maximum count rather than 9, so we need to detect when Q3 and Q1 are
high. We will now add 7 onto Q in states 10, 11, 14 and 15.
CLOCK
Q3
Σ C1
0 3
Q1 & Q3
P 3 1D
1 0 Q2
Σ Q1
Q3 3
Q2 Q Q0
Q1 0
Q0 0
1 2 3 4 5 6
10 0 11 12 13 14 15 7
9 8
7B.
Rev: Oct 2016 E2.1 Digital Electronics II – Solutions to Problem Sheet 2 Page 2
8B. According to table in Lecture 5 slide 17, a 7-bit
3 7
LFSR primitive polynomial is 1 + X + X .
9C. Here is a 1kHz clock with a high pulse of 20ns every microsecond:
Rev: Oct 2016 E2.1 Digital Electronics II – Solutions to Problem Sheet 2 Page 3