Serial-In Serial-Out Shift Register (SISO)
The shift register, which allows serial input (one bit after the other through a single data line)
and produces a serial output is known as a Serial-In Serial-Out shift register. Since there is
only one output, the data leaves the shift register one bit at a time in a serial pattern, thus the
name Serial-In Serial-Out Shift Register. The circuit consists of four D flip-flops which are
connected in a serial manner. All these flip-flops are synchronous with each other since the
same clock signal is applied to each flip-flop.
Serial-In Serial-Out Shift Register (SISO)
Serial-In Parallel-Out Shift Register (SIPO)
The shift register, which allows serial input (one bit after the other through a single data line)
and produces a parallel output is known as the Serial-In Parallel-Out shift register. The logic
circuit given below shows a serial-in-parallel-out shift register. The circuit consists of four D
flip-flops which are connected. The clear (CLR) signal is connected in addition to the clock
signal to all 4 flip flops in order to RESET them. The output of the first flip-flop is connected
to the input of the next flip flop and so on. All these flip-flops are synchronous with each
other since the same clock signal is applied to each flip-flop.
Serial-In Parallel-Out shift Register (SIPO)
Parallel-In Serial-Out Shift Register (PISO)
The shift register, which allows parallel input (data is given separately to each flip flop and in
a simultaneous manner) and produces a serial output is known as a Parallel-In Serial-Out shift
register. The logic circuit given below shows a parallel-in-serial-out shift register. The circuit
consists of four D flip-flops which are connected. The clock input is directly connected to all
the flip-flops but the input data is connected individually to each flip-flop through
a multiplexer at the input of every flip-flop. The output of the previous flip-flop and parallel
data input are connected to the input of the MUX and the output of MUX is connected to the
next flip-flop. All these flip-flops are synchronous with each other since the same clock
signal is applied to each flip-flop.
Parallel-In Serial-Out Shift Register (PISO)
Parallel-In Parallel-Out Shift Register (PIPO)
The shift register, which allows parallel input (data is given separately to each flip flop and in
a simultaneous manner) and also produces a parallel output is known as Parallel-In parallel-
Out shift register. The logic circuit given below shows a parallel-in-parallel-out shift register.
The circuit consists of four D flip-flops which are connected. The clear (CLR) signal and
clock signals are connected to all 4 flip-flops. In this type of register, there are no
interconnections between the individual flip-flops since no serial shifting of the data is
required. Data is given as input separately for each flip flop and in the same way, output is
also collected individually from each flip flop.
Parallel-In Parallel-Out Shift Register (PIPO)
Bidirectional Shift Register
To shift a binary number to the left by one position, it is equivalent to multiplying the number
by 2 and if we shift a binary number to the right by one position, it is equivalent to dividing
the number by 2. To perform these operations we need a register which can shift the data in
either direction. Bidirectional shift registers are the registers that are capable of shifting the
data either right or left depending on the mode selected. If the mode selected is 1(high), the
data will be shifted toward the right direction and if the mode selected is 0(low), the data will
be shifted towards the left direction. The logic circuit given below shows a Bidirectional shift
register. The circuit consists of four D flip-flops which are connected. The input data is
connected at two ends of the circuit and depending on the mode selected only one gate is in
the active state.