MP2315S

3A, 24V, 500kHz, High-Efficiency,

Synchronous, Step-Down Converter
The Future of Analog IC Technology

DESCRIPTION FEATURES
The MP2315S is a high-efficiency, synchronous, • Wide 4.5V to 24V Operating Input Range
rectified, step-down, switch mode converter • 3A Load Current
with built-in, internal power MOSFETs. It is a • 110mΩ/55mΩ Low RDS(ON) Internal Power
next generation of the MP2315. It offers a very MOSFETs
compact solution to achieve 3A continuous • Low Quiescent Current
output current over a wide input supply range • High-Efficiency Synchronous Mode
with excellent load and line regulation. Operation
The MP2315S uses synchronous mode • Fixed 500kHz Switching Frequency
operation for higher efficiency over the output • AAM Power Save Mode
current-load range. Current mode operation • Internal Soft Start
provides fast transient response and eases loop • Output Over-Voltage Protection (OVP)
stabilization. • Over-Current Protection (OCP) and Hiccup
Full protection features include over-current • Thermal Shutdown
protection (OCP), over-voltage protection • Output Adjustable from 0.8V
(OVP), and thermal shutdown. • Available in a TSOT23-8 Package
The MP2315S requires a minimal number of APPLICATIONS
readily available, standard, external • Notebook Systems and I/O Power
components and is available in a compact
• Digital Set-Top Boxes
TSOT23-8 package.
• Flat Panel Television and Monitors
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under quality
assurance. “MPS” and “The Future of Analog IC Technology” are registered
trademarks of Monolithic Power Systems, Inc.

TYPICAL APPLICATION

100
95

90
85

80
75
70

65
60
0.01 0.10 1.00 10.00

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 MP2315S – 3A, 24V, SYNCHRONOUS, STEP-DOWN CONVERTER

ORDERING INFORMATION
Part Number* Package Top Marking
MP2315SGJ TSOT23-8 See below
* For Tape & Reel, add suffix –Z (e.g. MP2315SGJ–Z)

TOP MARKING

AQT: Product code

Y: Year code

PACKAGE REFERENCE
TOP VIEW

TSOT23-8

ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance

(5)
θJA θJC
VIN .................................................-0.3V to +26V TSOT23-8…………………....…..100…..55...°C/W
VSW ..... -0.3V (-5V < 10ns) to +28V (30V < 10ns)
NOTES:
VBST ...................................................... VSW + 6V 1) Exceeding these ratings may damage the device.
(2)
All other pins ........................... -0.3V to +5.5V 2) For details on EN’s ABS MAX rating, please refer to the
(3) Enable Control section on page 9.
Continuous power dissipation (TA = +25°C) ... 3) The maximum allowable power dissipation is a function of the
................................................................. 1.25W maximum junction temperature TJ (MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
Junction temperature ................................150°C TA. The maximum allowable continuous power dissipation at
Lead temperature .....................................260°C any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
Storage temperature .................. -65°C to 150°C dissipation produces an excessive die temperature, causing
(4) the regulator to go into thermal shutdown. Internal thermal
Recommended Operating Conditions shutdown circuitry protects the device from permanent
Supply voltage (VIN) ........................... 4.5 to 24V damage.
4) The device is not guaranteed to function outside of its
Output voltage (VOUT)..............0.8V to VIN * DMAX operating conditions.
Operating junction temp (TJ). ... -40°C to +125°C 5) Measured on JESD51-7, 4-layer PCB.

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 MP2315S – 3A, 24V, SYNCHRONOUS, STEP-DOWN CONVERTER

ELECTRICAL CHARACTERISTICS
(6)
VIN = 12V, TJ = -40°C to +125°C. Typical value is tested at TJ = +25°C, unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
Supply current (shutdown) IIN VEN = 0V, TJ = 25°C 1 μA
VEN = 2V, VFB = 0.85V,
Supply current (quiescent) Iq 120 μA
AAM = 0.4V
HS switch on resistance HSRDS-ON VBST-SW = 5V 110 mΩ
LS switch on resistance LSRDS-ON VCC = 5V 55 mΩ
VEN = 0V, VSW = 12V,
Switch leakage SWLKG 1 μA
TJ = 25°C
Current limit ILIMIT Duty cycle = 40% 4.5 5.5 6.5 A
Oscillator frequency fSW VFB = 750mV 400 500 600 kHz
Foldback frequency fFB VFB = 200mV 0.5 fSW
Maximum duty cycle DMAX VFB = 750mV 90 95 %
Minimum on time (7) TON_MIN 60 ns

Feedback voltage VFB 783 791 800 mV

Feedback current IFB VFB = 820mV 10 50 nA

EN rising threshold VEN_RISING 1.26 1.4 1.54 V
EN hysteresis VEN_HYS 150 mV
VEN = 2V 1 2 3 μA
EN input current IEN
VEN = 0 0 50 nA
EN turn-off delay ENTd-off 5 9 13 μs
VIN under-voltage lockout
INUVVth 3.85 4.05 4.25 V
threshold rising
VIN under-voltage lockout
INUVHYS 600 750 900 mV
threshold hysteresis
VCC regulator VCC 4.85 5.1 5.35 V
VCC load regulation ICC = 5mA 1.5 %
Soft-start period TSS 10% to 90% 0.8 1.5 2.2 ms
Thermal shutdown (7) TSD 150 ºC
Thermal hysteresis (7) THYS 20 ºC
AAM source current IAAM 6.7 μA
OVP rising threshold OVH_RISE FB voltage 115% 120% 125% VREF
OVP falling threshold OVL_FALL FB voltage 104% 109% 114% VREF
OVP delay (7) OVDEY 2 μs
NOTES:
6) Not tested in production. Guaranteed by over-temperature correlation.
7) Guarantee by engineering sample characterization.

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 MP2315S – 3A, 24V, SYNCHRONOUS, STEP-DOWN CONVERTER

TYPICAL CHARACTERISTICS
VIN = 19V, VOUT = 5V, L = 4.9μH, TA = 25°C, unless otherwise noted.

100 100 100

95 95 95
90
90 90
85
85 85
80
80 80 75
75 75 70
65
70 70
60
65 65 55
60 60 50
0.01 0.10 1.00 10.00 0.01 0.10 1.00 10.00 0.01 0.10 1.00 10.00

6
0.9 0.9

0.7 0.7 5.8

0.5 0.5
5.6
0.3 0.3

0.1 0.1 5.4

-0.1 -0.1
5.2
-0.3 -0.3
-0.5 -0.5 5
0 1 2 3 6 8 10 12 14 16 18 20 22 24 0 10 20 30 40 50 60 70 80 90 100

150 200 60

140 50
150
40
130
100 30
120
20
50
110
10

100 0 0
4 8 12 16 20 24 4 8 12 16 20 24 1 1.5 2 2.5 3

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TYPICAL PERFORMANCE CHARACTERISTICS

VIN = 19V, VOUT = 5V, L = 4.9μH, TA = 25°C, unless otherwise noted.

VOUT VOUT VOUT

2V/div. 2V/div. 2V/div.

VIN VIN VIN

10V/div. 5V/div. 10V/div.
VSW VSW VSW
10V/div. 10V/div. 10V/div.
IINDUCTOR IINDUCTOR IINDUCTOR
2A/div. 5A/div.
2A/div.

VOUT VOUT VOUT

2V/div. 2V/div. 2V/div.

VIN VEN VEN

5V/div. 5V/div. 5V/div.
VSW VSW
VSW
5V/div. 20V/div.
20V/div.
IINDUCTOR IINDUCTOR
IINDUCTOR
5A/div. 2A/div.
2A/div.

VOUT/AC
VOUT VOUT 50mV/div.
2V/div. 2V/div.
VIN/AC
100mV/div.
VEN VEN
5V/div. 5V/div.
VSW VSW VSW
20V/div. 20V/div. 20V/div.
IINDUCTOR IINDUCTOR IINDUCTOR
5A/div. 5A/div. 2A/div.

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

VIN = 19V, VOUT = 5V, L = 4.9μH, TA = 25°C, unless otherwise noted.

VOUT/AC
20mV/div.
VOUT
200mV/div.
VIN/AC VOUT
200mV/div. 2V/div.

VSW VSW
20V/div. 20V/div.

IINDUCTOR IOUT IINDUCTOR

2A/div. 2A/div. 5A/div.

60 180

40 120

VOUT 20 60
2V/div.
0 0
VSW
20V/div. -20 -60

-40 -120
IINDUCTOR
5A/div.
-60 -180
1000 10000 100000 1000000

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PIN FUNCTIONS
Pin # Name Description
Advanced asynchronous modulation. Connect AAM to a voltage supply through a
resistor divider to force the MP2315S into non-synchronous mode under light-load
1 AAM
conditions. Tie AAM to VCC or leave AAM floating to disable AAM mode and force the
MP2315S into CCM.
Supply voltage. The MP2315S operates with a 4.5V to 24V input rail. C1 is needed to
2 IN
decouple the input rail. Connect using a wide PCB trace.
3 SW Switch output. Connect using a wide PCB trace.
System ground. GND is the reference ground of the regulated output voltage. GND
4 GND requires special consideration during PCB layout. Connect GND with copper traces and
vias.
Bootstrap. A capacitor and a resistor are required between SW and BST to form a
5 BST
floating supply across the high-side switch driver.
6 EN Enable. Drive EN high to enable the MP2315S.
Internal bias supply, internal 5.1V LDO output. Decouple VCC with a 0.1μF - 0.22μF
7 VCC
capacitor. The capacitance should be no more than 0.22μF.
Feedback. Connect FB to the tap of an external resistor divider from the output to GND
to set the output voltage. The frequency foldback comparator lowers the oscillator
8 FB
frequency when the FB voltage is below 400mV to prevent current-limit runaway during a
short-circuit fault condition.

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BLOCK DIAGRAM

Figure 1: Functional Block Diagram

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OPERATION Under light-load conditions, the value of VCOMP

is low. When VCOMP is less than VAAM, and VFB is
The MP2315S is a high-efficiency, synchronous, less than VREF, VCOMP ramps up until it exceeds
rectified, step-down, switch mode converter VAAM. During this time, the internal clock is
with built-in internal power MOSFETs. It offers a blocked, and the MP2315S skips some pulses
very compact solution that achieves 3A of for pulse frequency modulation (PFM) mode
continuous output current with excellent load and achieves a light-load power save.
and line regulation over a wide input supply
range.
When the MP2315S operates in a fixed
frequency, the peak-current control mode
regulates the output voltage. A pulse width
modulation (PWM) cycle is initiated by the
Figure 2: Simplified AAM Control Logic
internal clock. The integrated high-side power
MOSFET (HS-FET) turns on and remains on Enable Control (EN)
until its current reaches the value set by the Enable (EN) is a digital control that turns the
COMP voltage (VCOMP). When the power switch regulator on and off. Drive EN high to turn on
is off, it remains off until the next clock cycle the regulator; drive EN low to turn off the
begins. If the current in the power MOSFET regulator. An internal 1MΩ resistor from EN to
does not reach the COMP set current value GND allows EN to be floated to shut down the
within 95% of one PWM period, the power chip.
MOSFET is forced off.
EN is clamped internally using a 5.6V series
Internal Regulator Zener diode. Connect the EN input through a
Most of the internal circuitries are powered by pull-up resistor to the voltage on VIN to limit the
the 5.1V internal regulator. This regulator takes EN input current below 100µA. For example,
the VIN input and operates in the full VIN range. with 19V connected to VIN, RPULLUP ≥ (19V -
When VIN is greater than 5.1V, the output of the 5.6V) ÷ 100µA = 134kΩ.
regulator is in full regulation. When VIN drops Connecting EN directly to a voltage source
below 5.1V, the output decreases. A 0.1µF without a pull-up resistor requires limiting the
ceramic capacitor is required for decoupling. amplitude of the voltage source below 5.5V to
Error Amplifier (EA) prevent damage to the Zener diode.
The error amplifier compares the FB voltage Under-Voltage Lockout (UVLO)
with the internal 0.791V reference (REF) and Under-voltage lockout (UVLO) is implemented
outputs a COMP voltage which is used to to prevent the chip from operating at an
control the power MOSFET current. The insufficient supply voltage. The MP2315S
optimized internal compensation network UVLO comparator monitors the output voltage
minimizes the external component count and of the internal regulator (VCC). The UVLO
simplifies the control loop design. rising threshold is about 4.05V, while its falling
AAM Operation threshold is 3.3V.
The MP2315S uses advanced asynchronous Internal Soft-Start (SS)
modulation (AAM) power save mode in light The soft start (SS) is implemented to prevent
load. Set the AAM voltage with the tap of an the converter output voltage from overshooting
external resistor divider from VCC to GND. during start-up. When the chip starts up, the
Under heavy-load conditions, VCOMP is higher internal circuitry generates a soft-start voltage
than VAAM. When the clock goes low, the HS- that ramps up from 0V. The soft-start period
FET turns on and remains on until VILsense lasts until the voltage on the soft-start capacitor
reaches the value set by VCOMP. The internal exceeds the reference voltage of 0.791V. At
clock resets whenever VCOMP is higher than this point, the reference voltage takes over. The
VAAM. soft-start time is internally set to around 1.5ms.

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Output Over-Voltage Protection (OVP) Floating Driver and Bootstrap Charging

The MP2315S monitors the FB voltage to The floating power MOSFET driver is powered
detect output over-voltage. When the FB by an external bootstrap capacitor. This floating
voltage rises higher than 120% of the reference driver has its own UVLO protection with a rising
voltage, the MP2315S enters a dynamic threshold of 2.2V and a hysteresis of 150mV.
regulation period. During this period, the IC The bootstrap capacitor voltage is regulated
forces the low-side MOSFET (LS-FET) on until internally by VIN through D1, R3, C3, L1, and C2
a -800mA negative current limit is achieved. (see Figure 3). If VIN - VSW is more than 5V, U2
This discharges the output to keep it within the regulates M3 to maintain a 5V BST voltage
normal range. The MP2315S exits dynamic across C3.
regulation when FB falls below 109% of the
reference voltage.
Over-Current Protection (OCP) and Hiccup
The MP2315S uses a cycle-by-cycle over-
current limit when the inductor current peak
value exceeds the set current-limit threshold.
R3
The output voltage begins dropping until FB is
3
below the under-voltage (UV) threshold,
typically 50% below the reference. Once UV is
triggered, the MP2315S enters hiccup mode to
restart the part periodically. This protection
mode is especially useful when the output is Figure 3: Internal Bootstrap Charging Circuit
dead-shorted to ground. The average short- Start-Up and Shutdown
circuit current is reduced greatly to alleviate the If both VIN and EN are higher than their
thermal issue and protect the regulator. The appropriate thresholds, the chip starts up. The
MP2315S exits hiccup mode once the over- reference block starts first, generating a stable
current condition is removed. reference voltage and current. The internal
Pre-Bias Start-Up regulator is then enabled. The regulator
provides a stable supply for the remaining
The MP2315S is designed for monotonic start-
circuitries.
up into pre-biased loads. If the output is pre-
biased to a certain voltage during start-up, the Three events can shut down the chip: EN low,
BST voltage is refreshed and charged, and the VIN low, and thermal shutdown. In the shutdown
voltage on the soft-start capacitor is charged as procedure, the signaling path is blocked first to
well. If the BST voltage exceeds its rising prevent any fault triggering. VCOMP and the
threshold voltage, and the soft-start capacitor internal supply rail are then pulled down. The
voltage exceeds the sensed output voltage at floating driver is not subject to this shutdown
FB, the part begins working normally. command.
Thermal Shutdown
Thermal shutdown is implemented to prevent
the chip from operating at exceedingly high
temperatures. When the silicon die temperature
is higher than 150°C, the entire chip shuts down.
When the temperature is lower than its lower
threshold, typically 130°C, the chip is enabled
again.

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APPLICATION INFORMATION
Setting the Output Voltage Choose the inductor current to be
approximately 40% of the maximum load
An external resistor divider is used to set the
current. The maximum inductor peak current
output voltage. The feedback resistor (R1) also
can be calculated with Equation (3):
sets the feedback loop bandwidth with the
internal compensation capacitor (see Typical ΔIL
IL(MAX) = ILOAD +
Application on page 1). R2 can then be 2
(3)
calculated with Equation (1): Under light-load conditions below 100mA, a
R1 larger inductance is recommended for better
R2 = efficiency.
VOUT
−1
0.791V (1) Setting the AAM Voltage
The T-type network is highly recommended The AAM voltage is used to set the transition
(see Figure 4). point from AAM to PWM. It should be chosen to
provide the best combination of efficiency,
8 RT R1 stability, ripple, and transient.
FB VOUT
If the AAM voltage is set low, then the stability
R2
and ripple improve, but AAM mode and
transient efficiency degrade. Likewise, if the
AAM voltage is set high, then AAM mode and
Figure 4: T-Type Network
transient efficiency improves, but the stability
Table 1 lists the recommended T-type resistor and ripple degrade.
values for common output voltages.
Adjust the AAM threshold by connecting divider
Table 1: Resistor Selection for Common Output resistors from VCC to GND. Note that there is a
Voltages(8) 6.7µA current source at AAM (see Figure 5).
VOUT (V) R1 (kΩ) R2 (kΩ) Rt (kΩ)
1.05 20.5 62 100
1.2 20.5 39.2 75
1.8 40.2 31.6 59
2.5 40.2 18.7 40.2
3.3 40.2 12.7 33
5 40.2 7.5 20
NOTE:
8) The recommended parameters are based on a 44µF output
capacitor. A different input voltage, output inductor value, and
output capacitor value may affect the selection of R1, R2, and
Rt. For additional component parameters, please refer to the Figure 5: AAM Network
Typical Application Circuits section on pages 15 and 16.
Generally, VAAM can be calculated with Equation
Selecting the Inductor (4):
A 1µH to 10µH inductor with a DC current rating
R5 × (VCC + 6.7μA × R 4 )
at least 25% percent higher than the maximum VAAM =
load current is recommended for most R 4 + R5 (4)
applications. For the highest efficiency, the
inductor DC resistance should be less than R5 should be no larger than 20k.
20mΩ. For most designs, the inductance value
can be derived using Equation (2):
VOUT × (VIN − VOUT )
L1 =
VIN × ΔIL × fOSC (2)
Where ΔIL is the inductor ripple current.

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 MP2315S – 3A, 24V, SYNCHRONOUS, STEP-DOWN CONVERTER

The optimized AAM can be found in Figure 6. The input voltage ripple caused by the
0. 7 capacitance can be estimated with Equation (7):
ILOAD V ⎛ V ⎞
0. 6 ΔVIN = × OUT × ⎜ 1 − OUT ⎟
fS × C1 VIN ⎝ VIN ⎠
0. 5 (7)
0. 4
Selecting the Output Capacitor
The output capacitor (C2) is required to
0. 3
maintain the DC output voltage. Ceramic,
0. 2 tantalum, or low ESR electrolytic capacitors are
0. 1 recommended. Low ESR capacitors are
recommended to keep the output voltage ripple
0
0 2 4 6 8 low. The output voltage ripple can be estimated
with Equation (8):
Figure 6: AAM Selection for Common Output VOUT ⎛ VOUT ⎞ ⎛ 1 ⎞
Voltages (VIN = 4.5V - 24V) ΔVOUT = × ⎜1 − ⎟ × ⎜ RESR + ⎟
fS × L1 ⎝ VIN ⎠ ⎝ 8 × fS × C2 ⎠ (8)
Selecting the Input Capacitor
Where L1 is the inductor value and RESR is the
The input current to the step-down converter is equivalent series resistance (ESR) value of the
discontinuous and therefore requires a output capacitor.
capacitor to supply AC current to the step-down
converter while maintaining the DC input For ceramic capacitors, the impedance at the
voltage. Use low ESR capacitors for best switching frequency is dominated by the
performance. Ceramic capacitors with X5R or capacitance. The output voltage ripple is mainly
X7R dielectrics are highly recommended caused by the capacitance. For simplification,
because of their low ESR and small the output voltage ripple can be estimated with
temperature coefficients. For most applications, Equation (9):
a 22µF capacitor is sufficient. VOUT ⎛ V ⎞
ΔVOUT = × ⎜ 1 − OUT ⎟
Since the input capacitor (C1) absorbs the input 8 × fS × L1 × C2 ⎝
2
VIN ⎠
(9)
switching current, it requires an adequate ripple In the case of tantalum or electrolytic capacitors,
current rating. The RMS current in the input the ESR dominates the impedance at the
capacitor can be estimated with Equation (5): switching frequency. For simplification, the
I C1 = ILOAD ×
VOUT ⎛⎜ VOUT
× 1−
⎞
⎟ output ripple can be approximated with
VIN ⎜⎝ VIN ⎟
⎠ Equation (10):
(5)
VOUT ⎛ V ⎞
The worst-case condition occurs at VIN = ΔVOUT = × 1 − OUT ⎟ × RESR
2VOUT, shown in Equation (6): fS × L1 ⎜⎝ VIN ⎠(10)
ILOAD The characteristics of the output capacitor also
IC1 =
2 (6) affect the stability of the regulation system. The
MP2315S can be optimized for a wide range of
For simplification, choose an input capacitor
capacitance and ESR values.
with an RMS current rating greater than half of
the maximum load current. External Bootstrap Diode
The input capacitor can be electrolytic, tantalum, An external bootstrap diode may enhance the
or ceramic. When using electrolytic or tantalum efficiency of the regulator. The applicable
capacitors, a small, high-quality ceramic conditions of the external BST diode are:
capacitor (i.e.: 0.1μF) should be placed as close • VOUT is 5V or 3.3V
to the IC as possible. When using ceramic VOUT
• Duty cycle is high: D = > 65%
capacitors, ensure that they have enough VIN
capacitance to a provide sufficient charge to
prevent excessive voltage ripple at input.

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 MP2315S – 3A, 24V, SYNCHRONOUS, STEP-DOWN CONVERTER

In these cases, an external BST diode is

recommended from VCC to BST (see Figure 7).

Figure 7: Add Optional External Bootstrap Diode

to Enhance Efficiency
The recommended external BST diode is
1N4148, and the recommended BST capacitor
is 0.1 - 1μF.
(9)
PCB Layout Guidelines
Efficient PCB layout is critical for stable
operation. For best results, refer to Figure 8 and
follow the guidelines below:
1. Keep the connection of the input ground
and GND as short and wide as possible.
2. Keep the connection of the input capacitor
and IN as short and wide as possible.
3. Place the VCC capacitor as close to VCC
and GND as possible.
4. Make the trace length of VCC - VCC
capacitor anode - VCC capacitor cathode -
IC GND as short as possible.
5. Ensure that all feedback connections are Figure 8: Sample Board Layout
short and direct.
Design Example
6. Place the feedback resistors and Table 2 is a design example following the
compensation components as close to the application guidelines for the specifications
IC as possible. below:
7. Route SW away from sensitive analog Table 2: Design Example
areas, such as FB. VIN 19V
NOTE: VOUT 5V
9) The recommended layout is based on Figure 9 on page 15. IO 3A
The detailed application schematic is shown in
Figure 9. The typical performance and circuit
waveforms are shown in the Typical
Performance Characteristics section. For more
device applications, please refer to the related
evaluation board datasheets.

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 MP2315S – 3A, 24V, SYNCHRONOUS, STEP-DOWN CONVERTER

TYPICAL APPLICATION CIRCUITS

Figure 9: VIN = 6.5V - 24V, VOUT = 5V, IOUT = 3A

Figure 10: VIN = 4.5V - 24V, VOUT = 3.3V, IOUT = 3A

Figure 11: VIN = 4.5V - 24V, VOUT = 2.5V, IOUT = 3A

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 MP2315S – 3A, 24V, SYNCHRONOUS, STEP-DOWN CONVERTER

Figure 12: VIN = 4.5V - 24V, VOUT = 1.8V, IOUT = 3A

Figure 13: VIN = 4.5V - 24V, VOUT = 1.2V, IOUT = 3A

Figure 14: VIN = 4.5V - 24V, VOUT = 1.05V, IOUT = 3A

MP2315S Rev. 1.0 [Link] 15

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© 2015 MPS. All Rights Reserved.
 MP2315S – 3A, 24V, SYNCHRONOUS, STEP-DOWN CONVERTER

PACKAGE INFORMATION
TSOT23-8

See note 7
EXAMPLE
TOP MARK

PIN 1 ID
IAAAA

TOP VIEW RECOMMENDED LAND PATTERN

SEATING PLANE

SEE DETAIL''A''

FRONT VIEW SIDE VIEW

NOTE:

1) ALL DIMENSIONS ARE IN MILLIMETERS.

2) PACKAGE LENGTH DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURR.
3) PACKAGE WIDTH DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
4) LEAD COPLANARITY(BOTTOM OF LEADS
AFTER FORMING) SHALL BE 0.10 MILLIMETERS
MAX.
DETAIL ''A'' 5) JEDEC REFERENCE IS MO-193, VARIATION BA.
6) DRAWING IS NOT TO SCALE.
7) PIN 1 IS LOWER LEFT PIN WHEN READING TOP
MARK FROM LEFT TO RIGHT, (SEE EXAMPLE TOP
MARK)

NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.

MP2315S Rev. 1.0 [Link] 16

12/21/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.