MODULE-5

Input-Output organization
Peripheral devices
● In addition to the processor and a set of memory modules, the third key element of a
computer system is a set of input-output subsystem referred to as I/O, provides an
efficient mode of communication between the central system and the outside
environment.
● Programs and data must be entered into computer memory for processing and results
obtained from computations must be recorded or displayed for the user.
● Devices that are under the direct control of the computer are said to be connected on-
line. These devices are designed to read information into or out of the memory unit
upon command from CPU.
● Input or output devices attached to the computer are also called peripherals.
● Among the most common peripherals are keyboards, display units, and printers.
● Perhaps those provide auxiliary storage for the systems are magnetic disks and tapes.
● Peripherals are electromechanical and electromagnetic devices of some complexity.
● We can broadly classify peripheral devices into three categories:
o Human Readable: Communicating with the computer users, e.g. video
display terminal, printers etc.
o Machine Readable: Communicating with equipments, e.g. magnetic disk,
magnetic tape, sensor, actuators used in robotics etc.
o Communication: Communicating with remote devices means exchanging
data with that, e.g. modem, NIC (network interface Card) etc.

Fig: Block diagram of Peripheral device

● Control signals determine the function that the device will perform such as send
data to I/O module, accept data from I/O module.
● Status signals indicate the state of the device i.e. device is ready or not.
● Data bits are actual data transformation.
 ● Control logic associated with the device controls the device's operation in
response to direction from the I/O module.
● The transducer converts data from electrical to other forms of energy during
output and from other forms to electrical during input.
● Buffer is associated with the transducer to temporarily hold data being transferred
between the I/O module and external devices i.e. peripheral environment.

Input Device
● Keyboard
● Optical input devices
o Card Reader
o Paper Tape Reader
o Optical Character Recognition (OCR)
o Optical Bar code reader (OBR)
o Digitizer
o Optical Mark Reader
● Magnetic Input Devices
o Magnetic Stripe Reader
o Magnetic Ink Character Recognition (MICR)
● Screen Input Devices
o Touch Screen
o Light Pen
o Mouse
● Analog Input Devices

Output Device
● Card Puncher, Paper Tape Puncher
● Monitor (CRT, LCD, LED)
● Printer (Impact, Ink Jet, Laser, Dot Matrix)
● Plotter
● Analog
● Voice

I/O modules
● I/O modules interface to the system bus or central switch (CPU and Memory), interfaces
and controls to one or more peripheral devices. I/O operations are accomplished through
a wide assortment of external devices that provide a means of exchanging data between
external environment and computer by a link to an I/O module. The link is used to
exchange control status and data between I/O module and the external devices.
 Fig: Model of I/O module
● Peripherals are not directly connected to the system bus instead an I/O module is used
which contains logic for performing a communication between the peripherals and the
system bus. The reasons due to which peripherals do not directly connected to the system
bus are:
o There are a wide variety of peripherals with various methods of operation. It
would be impractical to incorporate the necessary logic within the processor to
control a range of devices.
o The data transfer rate of peripherals is often much slower than that of the memory
or processor. Thus, it is impractical to use high speed system bus to communicate
directly with a peripheral and vice versa.
o Peripherals often use different data format and word length than the computer to
which they are connected.
● Thus an I/O module is required which performs two major functions.
● Interface to the processor and memory via the system bus
● Interface to one or more peripherals by tailored data links

I/O Module Functions

● The I/O module is a special hardware component interface between the CPU and
peripherals to supervise and synchronize all I/O transformation The detailed functions of
I/O modules are;
Control & Timing: I/O module includes control and timing to coordinate the flow of
traffic between internal resources and external devices. The control of the transfer of data
from external devices to processor consists following steps:
o The processor interrogates the I/O module to check status of the attached device.
o The I/O module returns the device status.
o If the device is operational and ready to transmit, the processor requests the
transfer of data by means of a command to I/O module.
o The I/O module obtains the unit of data from the external device.
o The data are transferred from the I/O module to the processor.
Processor Communication: I/O module communicates with the processor which
involves:
 o Command decoding: I/O module accepts commands from the processor.
o Data: Data are exchanged between the processor and I/O module over the bus.
o Status reporting: Peripherals are too slow and it is important to know the status of
I/O module.
o Address recognition: I/O module must recognize one unique address for each
peripheral it controls.
Device Communication: It involves commands, status information and data.
Data Buffering: I/O module must be able to operate at both device and memory speeds.
If the I/O device operates at a rate higher than the memory access rate, then the I/O
module performs data buffering. If I/O devices rate slower than memory, it buffers data
so as not to tie up the memory in slower transfer operation.
Error Detection: I/O module is responsible for error detection such as mechanical and
electrical malfunction reported by device e.g. paper jam, bad ink track & unintentional
changes to the bit pattern and transmission error.

I/O Module Structure

Fig: Block diagram of I/O Module

● The I/O bus from the processor is attached to all peripheral interfaces
● To communicate with the particular devices, the processor places a device address on the
address bus.
● Each interface contains an address decoder that monitors the address line. When the
interface detects the particular device address, it activates the path between the data line
and devices that it controls.
● At the same time that the address is made available in the address line, the processor
provides a function code in the control way includes control command, output data and
input data.
I/O Bus and Interface Modules
● The I/O bus consists of data lines, address lines and control lines.

Fig: Connection of I/O bus to input-output devices

● Interface performs the following:

o Decodes the device address (device code)
o Decodes the commands (operation)
o Provides signals for the peripheral controller

o Synchronizes the data flow and supervises the transfer rate between peripheral
and CPU or Memory
● I/O commands that the interface may receive:
o Control command: issued to activate the peripheral and to inform it what to do.
o Status command: used to test various status conditions in the interface and the
peripheral.
o Output data: causes the interface to respond by transferring data from the bus into
one of its registers.
o Input data: is the opposite of the data output.

I/O versus Memory Bus

● Computer buses can be used to communicate with memory and I/O in three ways:
o Use two separate buses, one for memory and other for I/O. In this method, all
data, address and control lines would be separate for memory and I/O.
o Use one common bus for both memory and I/O but have separate control lines.
There is a separate read and write lines; I/O read and I/O write for I/O and
memory read and memory write for memory.
o Use a common bus for memory and I/O with common control line. This I/O
configuration is called memory mapped.

Modes of transfer
● Data Transfer between the central computer and I/O devices may be handled in a variety of
modes.
● Some modes use CPU as an intermediate path, others transfer the data directly to and from
 the memory unit.
● Data transfer to and from peripherals may be handled in one of three possible modes.
o Programmed I/O
o Interrupt Driven I/O
o Direct Memory Access (DMA)

Programmed I/O
● Programmed I/O operations are the result of I/O instructions written in the
computer program.
● In programmed I/O, each data transfer in initiated by the instructions in the CPU
and hence the CPU is in the continuous monitoring of the interface.
● Input instruction is used to transfer data from I/O device to CPU, store instruction
is used to transfer data from CPU to memory and output instruction is used to
transfer data from CPU to I/O device.
● This technique is generally used in very slow speed computer and is not a
efficient method if the speed of the CPU and I/O is different.

Fig: Data transfer from I/O device to CPU

 ● I/O device places the data on the I/O bus and enables its data valid signal
● The interface accepts the data in the data register and sets the F bit of status
register and also enables the data accepted signal.
● Data valid line is disables by I/O device.
● CPU is in a continuous monitoring of the interface in which it checks the F bit of
the status register.
o If it is set i.e. 1, then the CPU reads the data from data register and sets F
bit to zero
o If it is reset i.e. 0, then the CPU remains monitoring the interface.
● Interface disables the data accepted signal and the system goes to initial state
where next item of data is placed on the data bus.

Fig: Flowchart for CPU program to input data

Characteristics:
● Continuous CPU involvement
● CPU slowed down to I/O speed
● Simple
● Least hardware

Polling, or polled operation, in computer science, refers to actively sampling the status of an
external device by a client program as a synchronous activity. Polling is most often used in terms
of input/output (I/O), and is also referred to as polled I/O or software driven I/O.
 Interrupt-driven I/O
● Polling takes valuable CPU time
● Open communication only when some data has to be passed -> Interrupt.
● I/O interface, instead of the CPU, monitors the I/O device
● When the interface determines that the I/O device is ready for data transfer, it
generates an Interrupt Request to the CPU
● Upon detecting an interrupt, CPU stops momentarily the task it is doing, branches
to the service routine to process the data transfer, and then returns to the task it
was performing

The problem with programmed I/O is that the processor has to wait a long time for
the I/O module of concern to be ready for either reception or transmission of data.
The processor, while waiting, must repeatedly interrogate the status of the I/O
module. As a result, the level of the performance of the entire system is severely
degraded. An alternative is for the processor to issue an I/O command to a module
and then go on to do some other useful work. The I/O module will then interrupt the
processor to request service when it is ready to exchange data with processor. The
processor then executes the data transfer, and then resumes its former processing. The
interrupt can be initiated either by software or by hardware.

Interrupt Driven I/O basic operation

● CPU issues read command
● I/O module gets data from peripheral whilst CPU does other work
● I/O module interrupts CPU
● CPU requests data
● I/O module transfers data

Interrupt Processing from CPU viewpoint

● Issue read command
● Do other work
● Check for interrupt at end of each instruction cycle
● If interrupted:-
o Save context (registers)
o Process interrupt
o Fetch data & store
 Fig: Simple Interrupt Processing

Priority Interrupt
● Determines which interrupt is to be served first when two or more requests are
made simultaneously
● Also determines which interrupts are permitted to interrupt the computer while
another is being serviced
● Higher priority interrupts can make requests while servicing a lower priority
interrupt

Direct Memory access

● Large blocks of data transferred at a high speed to or from high speed devices,
magnetic drums, disks, tapes, etc.
● DMA controller Interface that provides I/O transfer of data directly to and from
the memory and the I/O device
● CPU initializes the DMA controller by sending a memory address and the number
of words to be transferred
● Actual transfer of data is done directly between the device and memory through
DMA controller -> Freeing CPU for other tasks
The transfer of data between the peripheral and memory without the interaction of CPU
and letting the peripheral device manage the memory bus directly is termed as Direct
Memory Access (DMA).

Fig: CPU bus signal for DMA transfer

The two control signals Bus Request and Bus Grant are used to fascinate the DMA
transfer. The bus request input is used by the DMA controller to request the CPU for the
control of the buses. When BR signal is high, the CPU terminates the execution of the
current instructions and then places the address, data, read and write lines to the high
impedance state and sends the bus grant signal. The DMA controller now takes the
control of the buses and transfers the data directly between memory and I/O without
processor interaction. When the transfer is completed, the bus request signal is made low
by DMA. In response to which CPU disables the bus grant and again CPU takes the
control of address, data, read and write lines.

The transfer of data between the memory and I/O of course facilitates in two ways which
are DMA Burst and Cycle Stealing.
DMA Burst: The block of data consisting a number of memory words is transferred at a
time.

Cycle Stealing: DMA transfers one data word at a time after which it must return control
of the buses to the CPU.
● CPU is usually much faster than I/O (DMA), thus CPU uses the most of the
memory cycles
● DMA Controller steals the memory cycles from CPU
● For those stolen cycles, CPU remains idle
● For those slow CPU, DMA Controller may steal most of the memory cycles
which may cause CPU remain idle long time

DMA Controller
The DMA controller communicates with the CPU through the data bus and control lines.
DMA select signal is used for selecting the controller, the register select is for selecting
the register. When the bus grant signal is zero, the CPU communicates through the data
bus to read or write into the DMA register. When bus grant is one, the DMA controller
takes the control of buses and transfers the data between the memory and I/O.
 Fig: Block diagram of DMA controller

The address register specifies the desired location of the memory which is incremented
after each word is transferred to the memory. The word count register holds the number
of words to be transferred which is decremented after each transfer until it is zero. When
it is zero, it indicates the end of transfer. After which the bus grant signal from CPU is
made low and CPU returns to its normal operation. The control register specifies the
mode of transfer which is Read or Write.

DMA Transfer
● DMA request signal is given from I/O device to DMA controller.

● DMA sends the bus request signal to CPU in response to which CPU disables its current
instructions and initialize the DMA by sending the following information.
o The starting address of the memory block where the data are available (for read)
and where data to be stored (for write)
o The word count which is the number of words in the memory block
o Control to specify the mode of transfer
o Sends a bust grant as 1 so that DMA controller can take the control of the
busesDMA sends the DMA acknowledge signal in response to which peripheral
device puts the words in the data bus (for write) or receives a word from the data
bus (for read).
Fig: DMA transfer in a computer system

DMA Operation
● CPU tells DMA controller:-
o Read/Write
o Device address
o Starting address of memory block for data
o Amount of data to be transferred
 ● CPU carries on with other work
● DMA controller deals with transfer
● DMA controller sends interrupt when finished

INTRODUCTION TO BUSES: -

A bus is a communication system that transfers data between components inside a computer
or between computers. It consists of a set of parallel conductors (wires, copper tracks, or
microscopic trails on a silicon chip) that carry data, addresses, and control signals.
Bus Structure
The bus structure in computer architecture typically includes three main types of lines:

1. Data Lines: These lines transfer data between the CPU, memory, and I/O devices. The number of lines
determines the width of the data bus, which affects the system’s performance.
2. Address Lines: These lines carry the addresses of the data being transferred. The width of the address
bus determines the maximum addressable memory.
3. Control Lines: These lines carry control signals that manage the use of the data and address lines. Control
signals include commands like memory read/write and I/O read/write12.

Bus Connections
In a computer system, buses connect various components such as the CPU, memory, and I/O devices.
The main types of buses include:

● System Bus: Connects the CPU to the main memory.

● Address Bus: Carries the addresses of data (unidirectional).
● Data Bus: Carries the actual data (bidirectional).
● Control Bus: Carries control signals (bidirectional).

Types of Buses

1. Internal Bus: Connects internal components of the computer, such as the CPU and memory.
2. External Bus: Connects external devices to the computer, such as USB devices

BUS CONTENTION:-
Bus contention is an undesirable state in computer design where more than one device on
a bus attempts to place values on it at the same time.

Bus contention is the kind of telecommunication contention that occurs when all communicating
devices communicate directly with each other through a single shared channel, and contrasted with
"network contention" that occurs when communicating devices communicate indirectly with each
other, through point-to-point connections through routers or bridges.
Bus contention can lead to erroneous operation, excess power consumption, and, in unusual cases,
permanent damage to the hardware

BUS ARBITRATION
In a computer system, multiple devices, such as the CPU, memory, and I/O controllers,
are connected to a common communication pathway, known as a bus. In order to
transfer data between these devices, they need to have access to the bus. Bus
arbitration is the process of resolving conflicts that arise when multiple devices attempt to
access the bus at the same time.
When multiple devices try to use the bus simultaneously, it can lead to data corruption
and system instability. To prevent this, a bus arbitration mechanism is used to ensure
that only one device has access to the bus at any given time.
There are several types of bus arbitration methods, including centralized, decentralized,
and distributed arbitration. In centralized arbitration, a single device, known as the bus
controller, is responsible for managing access to the bus. In decentralized arbitration,
each device has its own priority level, and the device with the highest priority is given
access to the bus. In distributed arbitration, devices compete for access to the bus by
sending a request signal and waiting for a grant signal.

Bus Arbitration refers to the process by which the current bus master accesses and
then leaves the control of the bus and passes it to another bus requesting processor unit.
The controller that has access to a bus at an instance is known as a Bus master.
A conflict may arise if the number of DMA controllers or other controllers or processors
try to access the common bus at the same time, but access can be given to only one of
those. Only one processor or controller can be Bus master at the same point in time. To
resolve these conflicts, the Bus Arbitration procedure is implemented to coordinate the
activities of all devices requesting memory transfers. The selection of the bus master
must take into account the needs of various devices by establishing a priority system for
gaining access to the bus. The Bus Arbiter decides who would become the current bus
master.
Applications of bus arbitration in computer organization:
Shared Memory Systems: In shared memory systems, multiple devices need to access
the memory to read or write data. Bus arbitration allows multiple devices to access the
memory without interfering with each other.
Multi-Processor Systems: In multi-processor systems, multiple processors need to
communicate with each other to share data and coordinate processing. Bus arbitration
allows multiple processors to share access to the bus to communicate with each other
and with shared memory.
Input/Output Devices: Input/Output devices such as keyboards, mice, and printers
need to communicate with the processor to exchange data. Bus arbitration allows
multiple input/output devices to share access to the bus to communicate with the
processor and memory.
Real-time Systems: In real-time systems, data needs to be transferred between devices
and memory within a specific time frame to ensure timely processing. Bus arbitration can
help to ensure that data transfer occurs within a specific time frame by managing access
to the bus.
Embedded Systems: In embedded systems, multiple devices such as sensors,
actuators, and controllers need to communicate with the processor to control and
monitor the system. Bus arbitration allows multiple devices to share access to the bus to
communicate with the processor and memory.
There are two approaches to bus arbitration:
1. Centralized bus arbitration –
A single bus arbiter performs the required arbitration.

2. Distributed bus arbitration –

All devices participating in the selection of the next bus master.

Methods of Centralized BUS Arbitration:

There are three bus arbitration methods:

(i) Daisy Chaining method: It is a simple and cheaper method where all the bus
masters use the same line for making bus requests. The bus grant signal serially
propagates through each master until it encounters the first one that is requesting access
to the bus. This master blocks the propagation of the bus grant signal, therefore any
other requesting module will not receive the grant signal and hence cannot access the
bus.
During any bus cycle, the bus master may be any device – the processor or any DMA
controller unit, connected to the bus.

Advantages:
● Simplicity and Scalability.
● The user can add more devices anywhere along the chain, up to a certain
maximum value.
Disadvantages:
● The value of priority assigned to a device depends on the position of the master
bus.
● Propagation delay arises in this method.
● If one device fails then the entire system will stop working.

(ii) Polling or Rotating Priority method: In this, the controller is used to generate the
address for the master(unique priority), the number of address lines required depends on
the number of masters connected in the system. The controller generates a sequence of
master addresses. When the requesting master recognizes its address, it activates the
busy line and begins to use the bus.

Advantages –
● This method does not favor any particular device and processor.
● The method is also quite simple.
● If one device fails then the entire system will not stop working.
Disadvantages –
● Adding bus masters is difficult as increases the number of address lines of the
circuit.

(iii) Fixed priority or Independent Request method –

In this, each master has a separate pair of bus request and bus grant lines and each pair
has a priority assigned to it.
The built-in priority decoder within the controller selects the highest priority request and
asserts the corresponding bus grant signal.
Advantages –
● This method generates a fast response.
Disadvantages –
● Hardware cost is high as a large no. of control lines is required.

Distributed BUS Arbitration :

In this, all devices participate in the selection of the next bus master. Each device on the
bus is assigned a 4bit identification number. The priority of the device will be determined
by the generated ID.

Uses of BUS Arbitration in Computer Organization :

Bus arbitration is a critical process in computer organization that has several uses and
benefits, including:
1. Efficient use of system resources: By regulating access to the bus, bus
arbitration ensures that each device has fair access to system resources,
preventing any single device from monopolizing the bus and causing system
slowdowns or crashes.
2. Minimizing data corruption: Bus arbitration helps prevent data corruption by
ensuring that only one device has access to the bus at a time, which minimizes
 the risk of multiple devices writing to the same location in memory
simultaneously.
3. Support for multiple devices: Bus arbitration enables multiple devices to share a
common communication pathway, which is essential for modern computer
systems with multiple peripherals, such as printers, scanners, and external
storage devices.
4. Real-time system support: In real-time systems, bus arbitration is essential to
ensure that high-priority tasks are executed quickly and efficiently. By prioritizing
access to the bus, bus arbitration can ensure that critical tasks are given the
resources they need to execute in a timely manner.
5. Improved system stability: By preventing conflicts between devices, bus
arbitration helps to improve system stability and reliability. This is especially
important in mission-critical systems where downtime or data corruption could
have severe consequences.

Issues of BUS Arbitration in Computer Organization :

Bus arbitration is a critical process in computer organization that has several uses and
benefits, including:
1. Efficient use of system resources: By regulating access to the bus, bus
arbitration ensures that each device has fair access to system resources,
preventing any single device from monopolizing the bus and causing system
slowdowns or crashes.
2. Minimizing data corruption: Bus arbitration helps prevent data corruption by
ensuring that only one device has access to the bus at a time, which minimizes
the risk of multiple devices writing to the same location in memory
simultaneously.
3. Support for multiple devices: Bus arbitration enables multiple devices to share a
common communication pathway, which is essential for modern computer
systems with multiple peripherals, such as printers, scanners, and external
storage devices.
4. Real-time system support: In real-time systems, bus arbitration is essential to
ensure that high-priority tasks are executed quickly and efficiently. By prioritizing
access to the bus, bus arbitration can ensure that critical tasks are given the
resources they need to execute in a timely manner.
5. Improved system stability: By preventing conflicts between devices, bus
arbitration helps to improve system stability and reliability. This is especially
important in mission-critical systems where downtime or data corruption could
have severe consequences.