Q (Next Q' (Next asynchronous (ripple), depending on how the

J K
1. De-Multiplexer (DeMUX): State) State) flip-flops are connected.
A De-Multiplexer (DeMUX) is a combinational 0 0
Q (No Q' (No 4-bit Asynchronous Down Counter: This
logic circuit that takes a single input and routes it Change) Change) counter decreases its count from 15 (1111) to 0
to one of many output lines based on the values 0 1 0 1 (0000) with each clock pulse. The flip-flops are
of the selection lines. It performs the reverse 1 0 1 0 connected in series, with the clock signal
function of a Multiplexer (MUX), where a single 1 1 Q' (Toggles) Q (Toggles) propagating through each flip-flop. The down
input line is selected from multiple lines. The De- Logic Diagram: counter uses the feedback from the previous flip-
MUX ensures that only one of the output lines flop to determine the next state.
carries the input signal at any given time, based Timing Diagram: A typical timing diagram for
on the selection lines. this counter shows how the output changes on
For example, a 1:4 De-MUX takes one data input each clock pulse, starting from 1111 and
(D) and routes it to one of four output lines (O0, counting down to 0000.
O1, O2, O3) based on two selection lines (S1, S0). 4-bit Asynchronous Up-Down Ripple
1:4 De-MUX: Counter: This type of counter can count both up
Inputs: One data input (D), two selection lines and down based on the direction control input. In
(S1, S0). the up mode, it increments with each clock pulse,
Outputs: Four output lines (O0, O1, O2, O3). The JK flip-flop consists of two AND gates, a NOT while in the down mode, it decrements. The flip-
The truth table for a 1:4 De-MUX is as follows: gate, two OR gates, and two SR flip-flops. The flops are connected in a ripple configuration, and
S O O O inputs are connected to the gates in such a way the output changes one bit at a time, starting
S1 O3 that the output depends on both the inputs and
0 0 1 2 from 0000 or 1111.
the current state. Timing Diagram: The timing diagram for the up-
0 0 D 0 0 0
down ripple counter shows the binary values
0 1 0 D 0 0 2. RS Flip-Flop (Set-Reset Flip-Flop) incrementing or decrementing based on the
1 0 0 0 D 0 Working: The RS flip-flop (also known as SR flip- direction control signal.
1 1 0 0 0 D flop) has two inputs: S (Set) and R (Reset). It is
The De-MUX works by using AND gates, where one of the simplest types of flip-flops. When S is
high, the output Q is set to 1, and when R is high, 6. Registers:
each output line is activated based on the state
the output Q is reset to 0. If both inputs are low, A register is a set of flip-flops used to store
of the selection lines.
the state of Q remains unchanged. multi-bit data. Registers are essential
Truth Table: components in digital systems for storing
2. Karnaugh Maps (K-Maps): Q (Next Q' (Next temporary data, such as in processors or
S R memory.
A Karnaugh Map (K-map) is a graphical State) State)
representation of a Boolean function, allowing for Registers are faster than memory and usually
0 0 Q (No Change) Q' (No Change)
systematic simplification by grouping adjacent directly interact with the CPU's arithmetic and
0 1 0 1 logic units (ALU).
ones in a grid format. It eliminates the need for
complex Boolean algebraic manipulations. 1 0 1 0 Types of Registers:
Types of Grouping in K-map: Invalid (Both Invalid (Both Shift Registers:
1 1 Shift registers are specialized registers designed
1-cell group: A single minterm is represented by High) High)
a 1 in the K-map. It directly corresponds to a Note: The state (S = 1, R = 1) is not valid, and it to shift the data bits to the left or right. These are
Boolean product term. can lead to an unstable output. essential in digital circuits for operations such as
2-cell group: Groups two adjacent ones to Logic Diagram: data conversion, multiplication, and serial
eliminate one variable. The RS flip-flop is made using two NOR gates or communication. There are four main types of shift
4-cell group: Groups four adjacent ones, two NAND gates in a feedback configuration. The registers, each differing in how data is entered
simplifying two variables. S input is connected to one gate, and the R input and shifted.
8-cell group: Groups eight adjacent ones, to the other gate. Serial-In, Serial-Out (SISO) Shift Register:
simplifying three variables. Data Entry: Serial (one bit at a time).
Example: Simplify the Boolean expression 3. D Flip-Flop (Data Flip-Flop) Data Exit: Serial (one bit at a time).
F(ABCD)=Σm(1,5,7,9,11,13,15)F(ABCD) = \ Working: The D flip-flop (also known as the Data Use: Commonly used for data transmission,
Sigma m(1, 5, 7, 9, 11, 13, 15) or Delay flip-flop) has a single data input, D. where data enters one bit at a time and exits in
Step 1: Write the Boolean expression in minterm When the clock signal is active (rising or falling the same manner.
form and place the 1's in the K-map at positions edge), the value at the D input is transferred to Operation: As data enters from the input, it
corresponding to the minterms (1, 5, 7, 9, 11, 13, the output Q. It is a simplified version of the JK shifts one bit at a time, and after each shift, the
15). flip-flop where the state depends entirely on the last bit of the register is sent out serially.
Step 2: Group the adjacent 1's in the K-map. You value of the D input. Serial-In, Parallel-Out (SIPO) Shift Register:
will form two groups: one for AB‾A \overline{B} Truth Table: Data Entry: Serial (one bit at a time).
and another for CC. Data Exit: Parallel (all bits at once).
Step 3: The simplified Boolean expression is Use: Converts serial data to parallel data. Often
AB‾+CA \overline{B} + C. used in data communication where data is
This K-map simplification helps reduce the received serially but needs to be processed in
complexity of Boolean functions, making it easier parallel.
to design efficient circuits. Operation: Data enters serially but is available
3. Boolean Algebra: for access on multiple output pins simultaneously
Boolean Algebra is the mathematical after being shifted in.
foundation of digital logic. It deals with the Parallel-In, Serial-Out (PISO) Shift Register:
Cloc Q (Next Q' (Next
manipulation of binary variables using logical D Data Entry: Parallel (all bits at once).
k State) State)
operations like AND, OR, and NOT. Boolean Data Exit: Serial (one bit at a time).
0 ↑ 0 1 Use: Converts parallel data to serial data. This is
algebra allows us to simplify and analyze digital
circuits. 1 ↑ 1 0 useful in applications where parallel data needs
Prove the expression Note: The output Q only changes on the active to be transmitted serially.
ABCD+A‾BCD+ABC‾D+ABCD‾=B(D+C)ABCD clock edge (rising or falling). Operation: Data is loaded into the register in
+ \overline{A}BCD + AB\overline{C}D + Logic Diagram: parallel and is shifted out bit by bit serially.
ABC\overline{D} = B(D + C): The D flip-flop is implemented using an SR flip- Parallel-In, Parallel-Out (PIPO) Shift
Step 1: Group the terms with common factors. flop with feedback that ensures the state Register:
ABCD+A‾BCD=BC(D+A‾)ABCD + \ changes only according to the D input, Data Entry: Parallel (all bits at once).
overline{A}BCD = BC(D + \overline{A}) preventing the invalid state from occurring. Data Exit: Parallel (all bits at once).
ABC‾D+ABCD‾=B(D+C)AB\overline{C}D + ABC\ Use: Typically used to store data temporarily and
overline{D} = B(D + C) 4. T Flip-Flop (Toggle Flip-Flop) allows access to all bits simultaneously.
Step 2: Simplify the first and second parts. Working: The T flip-flop (Toggle flip-flop) is a Operation: Data is loaded in parallel and can be
The first part simplifies to BC(D+A‾)BC(D + \ simplified version of the JK flip-flop. It has a single read from multiple outputs at once.
overline{A}). input T (Toggle). When T is high, the state of the
The second part simplifies to B(D+C)B(D + C). flip-flop toggles (changes from 0 to 1 or 1 to 0). Number Systems and Their Conversions
Final Expression: Combining both parts: When T is low, the output remains unchanged. A number system is a writing system for
Truth Table: expressing numbers; it is a mathematical
BC(D+A‾)+B(D+C)=B(D+C)BC(D + \overline{A})
notation for representing numbers of a given set,
+ B(D + C) = B(D + C) Q (Next Q' (Next
T using digits or other symbols. The most
This simplification shows that the original State) State) commonly used number systems are Decimal,
Boolean expression can be reduced to a much Q (No Q' (No Binary, Octal, and Hexadecimal.
simpler form, making it easier to implement in a 0
Change) Change) Here is a detailed explanation of each system and
digital circuit. their conversions:
1 Q' (Toggles) Q (Toggles)
4. Flip-Flops and Latches: Note: The output toggles only when T is high,
Flip-flops are bistable devices that store one bit of otherwise it remains the same. 1. Decimal Number System (Base 10)
information. They are used in sequential circuits to store Logic Diagram: Definition: The decimal system uses 10 digits: 0, 1, 2, 3,
states and are fundamental for building memory elements 4, 5, 6, 7, 8, 9. It is the most commonly used number
The T flip-flop is essentially a JK flip-flop with both system in daily life.
in digital systems.
the J and K inputs tied together. When T is high, Place Value: The place value increases by powers of 10 as
Working: The JK flip-flop is a type of bistable multivibrator
the JK flip-flop toggles its state, making it a toggle we move from right to left. For example, in the number
with two inputs: J (set) and K (reset). It is a more versatile
234, the place value of each digit is:
version of the SR flip-flop and overcomes the invalid state flip-flop.
2 × 10² (Hundreds)
of the SR flip-flop. The JK flip-flop can toggle its state 3 × 10¹ (Tens)
depending on the inputs. 5. Counters: 4 × 10⁰ (Ones)
Truth Table: Number Systems and Their Conversions
A counter is a digital device that counts the
A number system is a way of expressing numbers using a
number of pulses from a clock signal, producing a set of symbols. The most commonly used number systems
binary output. Counters can be synchronous or are Decimal, Binary, Octal, and Hexadecimal.
1. Decimal Number System (Base 10)
Uses digits: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9.
Place value increases by powers of 10 from right to left.

2. Binary Number System (Base 2)

Uses digits: 0, 1.
Each digit represents a power of 2. For example, in 1011₂:
1×23+0×22+1×21+1×20=8+0+2+1=111 \times 2^3 + 0
\times 2^2 + 1 \times 2^1 + 1 \times 2^0 = 8 + 0 + 2 + 1
= 11.

3. Octal Number System (Base 8)

Uses digits: 0, 1, 2, 3, 4, 5, 6, 7.
Each digit represents a power of 8. For example, in 345₈:
3×82+4×81+5×80=192+32+5=2293 \times 8^2 + 4 \
times 8^1 + 5 \times 8^0 = 192 + 32 + 5 = 229.

4. Hexadecimal Number System (Base 16)

Uses digits: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F
(where A=10, B=11, etc.).

Converting Between Number Systems

1. Decimal to Binary
Divide the decimal number by 2, noting the remainders.
Example: 26₁₀ to binary:
26÷2=1326 ÷ 2 = 13 remainder 0,
13÷2=613 ÷ 2 = 6 remainder 1,
6÷2=36 ÷ 2 = 3 remainder 0,
3÷2=13 ÷ 2 = 1 remainder 1,
1÷2=01 ÷ 2 = 0 remainder 1.
So, 26₁₀ = 11010₂.
2. Binary to Decimal Multiply each bit by 2 raised to the
power of its position and sum the results.
Example: 11010₂ to decimal:
1×24+1×23+0×22+1×21+0×20=16+8+0+2+0=261 \
times 2^4 + 1 \times 2^3 + 0 \times 2^2 + 1 \times 2^1
+ 0 \times 2^0 = 16 + 8 + 0 + 2 + 0 = 26.
So, 11010₂ = 26₁₀.

3. Decimal to Octal
Divide the decimal number by 8, noting the remainders.
Example: 45₁₀ to octal:
45÷8=545 ÷ 8 = 5 remainder 5,
5÷8=05 ÷ 8 = 0 remainder 5.
So, 45₁₀ = 55₈.
4. Octal to Decimal
Multiply each digit by 8 raised to the power of its position
and sum the results.
Example: 55₈ to decimal:
5×81+5×80=40+5=455 \times 8^1 + 5 \times 8^0 = 40
+ 5 = 45.
So, 55₈ = 45₁₀.
5. Decimal to Hexadecimal
Divide the decimal number by 16, noting the remainders.
Example: 245₁₀ to hexadecimal:
245÷16=15245 ÷ 16 = 15 remainder 5,
15÷16=015 ÷ 16 = 0 remainder 15 (F).
So, 245₁₀ = F5₁₆.
6. Hexadecimal to Decimal
Multiply each digit by 16 raised to the power of its position
and sum the results.
Example: F5₁₆ to decimal:
F×161+5×160=15×16+5×1=240+5=245F \times 16^1 +
5 \times 16^0 = 15 \times 16 + 5 \times 1 = 240 + 5 =
245.
So, F5₁₆ = 245₁

De Morgan's Theorems
De Morgan’s Theorems are fundamental rules in Boolean
algebra that relate conjunctions (AND operations) and
disjunctions (OR operations) to negations (NOT operations).
These theorems are particularly useful for simplifying
Boolean expressions.
There are two De Morgan’s Theorems:

1. First De Morgan’s Theorem:

A⋅B‾=A‾+B‾\overline{A \cdot B} = \overline{A} + \
overline{B}
This theorem states that the negation of the conjunction
(AND) of two variables is equivalent to the disjunction (OR)
of the negations of the variables.
Proof:
Let’s prove the first De Morgan’s theorem using a truth
table:
A‾+B‾\
A A⋅B‾\ A‾\ B‾\
overline{A}
A B · overline{A overline{ overline{
+\
B \cdot B} A} B}
overline{B}
0 0 0 1 1 1 1
0 1 0 1 1 0 1
1 0 0 1 0 1 1
1 1 1 0 0 0 0
As we can see from the truth table, the columns for A⋅B‾\
overline{A \cdot B} and A‾+B‾\overline{A} + \overline{B}
are identical. Hence, the first De Morgan’s theorem is
proven.
2. Second De Morgan’s Theorem:
A+B‾=A‾⋅B‾\overline{A + B} = \overline{A} \cdot \
overline{B}
This theorem states that the negation of the disjunction
(OR) of two variables is equivalent to the conjunction (AND)
of the negations of the variables.
Proof:
Let’s prove the second De Morgan’s theorem using a truth
table:
A‾⋅B‾\
A A+B‾\ A‾\ B‾\
overline{A}
A B + overline{A overline{ overline{
\cdot \
B + B} A} B}
overline{B}
0 0 0 1 1 1 1
0 1 1 0 1 0 0
1 0 1 0 0 1 0
1 1 1 0 0 0 0
As we can see from the truth table, the columns for A+B‾\
overline{A + B} and A‾⋅B‾\overline{A} \cdot \overline{B}
are identical. Hence, the second De Morgan’s theorem is
proven.