Indian Institute Of Science
E3-245 Processor System Design
32 - Bit Pipeline RISC-V
Processor
Student:
Manish Sutradhar Instructor:
([Link], MVLSI) Kuruvilla Varghese
22478
Figure 1: Architecture
Figure 2: Instructions
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Figure 3: RISC V integer Instruction
Figure 4: Control Unit
2
1 Functionality
• Datapath is designed for entire integer instructions.
• Four Distributed RAM is used for Data.
• Instruction cache has been implemented.
• All instructions are tested and verified.
Figure 5: Timing Report
Achieved a maximum frequency of 72 MHz.
Figure 6: Resource Utilization
3
Figure 7: Power Report
Figure 8: Clock Summary
2 Code
Problem 1 Write a code to find the maximum number out of ten random num-
bers.
C Language
#include <stdio.h>
int main() {
int numbers[10] = {5, 10, 6, 2, 8, 19, 7, 3, 29, 6};
int i, max;
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// Initialize max to the first number
max = numbers[0];
// Compare max with each number in the array
for(i = 1; i < 10; i++) {
if(numbers[i] > max) {
max = numbers[i];
}
}
// Output the maximum number
printf("The maximum number is: %d\n", max);
return 0;
}
Assembly Language
_start:
# Initialize base address of array manually
addi t1, x0, array # t1 = base address of array
# Load the first number as the initial max
lw t2, 0(t0) # t2 = array[0]
# Initialize loop counter manually
addi t3, x0, 9 # t3 = 9 (loop counter for remaining 9 numbers)
find_max:
# Move to the next element in the array
addi t1, t1, 4 # t1 = t1 + 4 (next array element)
# Load the next number in the array
lw t4, 0(t0) # t4 = array[i]
# Compare and update max if necessary
blt t2, t4, update_max
# Continue to next iteration
j continue_loop
update_max:
addi t2, t4, 0 # t2 = t4 (update max)
continue_loop:
# Decrement the loop counter
addi t3, t3, -1 # t3 = t3 - 1
5
# Loop until all elements are processed
bnez t3, find_max
# Store the max value in memory manually
addi t1, x0, max # Load max address into t1
sw t2, 0(t0) # max = t2
# Infinite loop to stop execution
done:
j done # Infinite loop to end the program
3 Conclusion
In this assignment a 32 bit risc-v processor has been designed and implemented
on FPGA board (Basys-3) using verilog HDL language. Various instruction
formats and ALU functionality is implemented in the design. Moreover, after
successful testing of the program on FPGA board a maximum frequency of 72
MHz is achieved.