Annexure – I
Micro-Project Proposal
Logic Gates
1.0. Aims/Benefits of the Logic gates
Logic gates are quick yet use low energy. Logic gates don't get overworked. Logic gates can lessen the
prescribed number of I/O ports needed by a microcontroller. Logic gates can bring about
straightforward data encryption and decryption.
2.0. Course Outcomes Addressed
a) Use Number System and codes for interpreting working of Addressed
digital system
b) Use Boolean expressions to realize logic circuits Not Addressed
c) Build simple combinational circuits Not Addressed
d) Build simple Sequential circuits Addressed
e) Test data converters and PLDs in digital electronics Not Addressed
systems
3.0. Project Methodology
• Step 1: What do we want our logic circuit will do?
• Step 2: Define input-output relationship.
• Step 3: Find Boolean expressions equivalent to our truth table. ...
• Step 4: Simplify Boolean expressions.
• Step 5: Prepare logic circuit based on Bolean expressions.
step 6: Use real chips to implement logic circuit we have found
4.0. Action Plan.
Planned
Sr. Planned Name of Responsible
Details of activity Finish
No. Start Date Team Member
Date
Information Gathering and Topic Patil Om
1 31-07-2023 31-07-2023
Finalization
Preparing Project Proposal and 08-08-2023 08-08-2023 Ghule Akash
2
Approval
28-08-2023 28-08-2023 Dhondge Piyush
3 Implementing Project
04-09-2023 04-09-2023 Ghule Akash
4 Preparing Project Report
02-10-2023 02-10-2023 Patil Om
5 Presenting Project
09-10-2023 09-10-2023 Dhondge Piyush
6 Submission of Project and Report
MET’s Institute of Technology, Polytechnic, Nashik 1
Resource Required
Sr.
Name of Resource/Material Specifications Qty. Remarks
No.
1 Computer System I5 3rd gen, 8gb RAM 01
2 Development Package C,C++ Online Compiler 01
Sublime Text or
3 Editor 01
VS Code edior
Onlineiterpreter by
4 Online C Compiler 01
[Link]
Name of Member with Roll No and Enrollment No.
Roll No Enrollment No Name of Member
62 23611470243 Dhondge Piyush Jagdish
63 23611470239 Ghule Akash Bhausaheb
65 23611470241 Patil Om Sharad
Approved by
(Prof. Swati D. Jadhav)
Name and Signature of Staff
MET’s Institute of Technology, Polytechnic, Nashik 2
Annexure – II
Micro-Project Report
Report on microproject
1.0. Rationale
Logic gates are an important concept if you are studying electronics. These are important digital devices
that are mainly based on the Boolean function. Logic gates are used to carry out logical operations on
single or multiple binary inputs and give one binary output. In simple terms, logic gates are the
electronic circuits in a digital system.
2.0. Aims/Benefits of the Micro-Project
Logic gates are quick yet use low energy. Logic gates don't get overworked. Logic gates can lessen the
prescribed number of I/O ports needed by a microcontroller. Logic gates can bring about
straightforward data encryption and decryption.
3.0. Course Outcomes Addressed
a) Use Number System and codes for interpreting working of Addressed
digital system
b) Use Boolean expressions to realize logic circuits Not Addressed
c) Build simple combinational circuits Not Addressed
d) Build simple Sequential circuits Addressed
e) Test data converters and PLDs in digital electronics Addressed
systems
4.0. Literature Review
BASIC GATES
THE OR GATE – It is a device that combines A with B to give Y as the result. The OR gate
has two or more inputs and one output. The logic gate of OR gate with A and B input
andY
output is shown :-
In Boolean algebra, addition symbol (+) is referred as the OR. The Booleanexpression:
A+B = Y indicates Y equals A OR B.
i . I f s w i t c h A a n d B o p e n ( A = 0 , B = 0 ) t h e n , Y = 0 [Link] switch A open
B closed (A=0, B=1)then,Y=[Link] switch A closed B open (A=1, B=0)then,Y=[Link] switch A & B are
closed (A=1, B=1)then,Y=1
MET’s Institute of Technology, Polytechnic, Nashik 3
THE AND GATE –
It is a device that combines A with B to give Y as the result. The AND gate has twoor more inputs and
one output. The logic gate of AND gate with A and B input andY output is shown below:
In Boolean algebra, multiplication sign (either x or.) is referred as the AND. TheBoolean expression: A.B
= Y indicates Y equals A
✕
B.
i. I f b o t h s w i t c h e s A a n d B a r e o p e n ( A = 0 , B=0) then, Y=0.
ii. [Link] Switch A closed and B open (A=1, B=0)then, Y =0.
iii. [Link] switch A open and B closed (A=0, B=1)then, Y=0.
iv. [Link] switch A and B both closed (A=1, B=1)then, Y =1.
THE NOT GATE -
It is a device that inverts the inputs. The NOT is a one input and one output. The logic gate of NOT gate
with A and Y output is shown below:
A
Y=A
In Boolean algebra, bar symbol (-) is referred as the NOT. The Boolean expression: AY,
indicates Y equals NOT A.
MET’s Institute of Technology, Polytechnic, Nashik 4
i. I f s w i t c h A i s o p e n ( i . e . A = 0 ) , then, Y=1.
ii. i i . I f S w i t c h A i s c l o s e d ( i . e . A = 1 ) , then, Y=0
THE NOR GATE-
The Logic NOR Gate gate is a combination of the digital logic OR gate andan inverter or NOT gate
connected together in [Link] inclusive NOR(Not-OR) gate has an output that is normally at logic level
“1” and onlygoes “LOW” to logic level “0” when ANY of its inputs are at logic level “1”.
THE NOR GATE
Boolean expression of NOR giving us the Boolean expression of: A+B = Y.
i. I f S w i t c h A & B o p e n ( A = 0 , B = 0 ) t h e n Y=1.
i i . I f S w i t c h A c l o s e d & B o p e n ( A = 1 , B = 0 ) then,Y =0.I
[Link] Switch A open & B close (A=0, B=1)then, Y=0.
[Link] switch A& B are closed (A=1, B=1) then,Y=0.
The NAND gate-
The NAND gate or “NotAND” gate is the combination of two basic logic gates, the ANDgate and the NOT
gate connected in series. The NAND gate and NOR gate can be calledthe universal gates since the
combination of these gates can be used to accomplish anyof the basic operations. Hence, NAND gate
and NOR gate combination can produce aninverter, an OR gate or an AND gate.
THE NAND GATE
i. If Switch A & B open (A=0, B=0) then Y=1.
ii. If Switch A open B closed (A=0, B=1)then,Y=1.
iii. If switch A closed B open (A=1, B=0)then,Y=1.
iv. If switch A & B are closed (A=1, B=1) then,Y=0.
MET’s Institute of Technology, Polytechnic, Nashik 5
THE Exclusive-OR gate (XOR Gate)
Exclusive OR gate – is a digital logic gate that gives a true (i.e. a HIGH or 1)output when the number of
true inputs is odd. An XOR gate implements anexclusive OR, i.e., a true output result occurs if one – and
only one – of the gate’sinputs is true. If both inputs are false (i.e. LOW or 0) or both inputs are true,
theoutput is false.
i. If Switch A & B open (A=0, B=0) then Y=1
[Link] Switch A open B closed (A=0, B=1)then,Y=0
[Link] switch A closed B open (A=1, B=0)then,Y=0
[Link] switch A & B are closed (A=1, B=1) then,Y=1.
Actual Methodology Followed
• Step 1: What do we want our logic circuit will do?
• Step 2: Define input-output relationship.
• Step 3: Find Boolean expressions equivalent to our truth table. ...
• Step 4: Simplify Boolean expressions.
• Step 5: Prepare logic circuit based on Bolean expressions.
• step 6: Use real chips to implement logic circuit we have found
MET’s Institute of Technology, Polytechnic, Nashik 6
Planned
Sr. Planned Name of Responsible
Details of activity Finish
No. Start Date Team Member
Date
Information Gathering and Topic Patil Om
1 31-07-2023 31-07-2023
Finalization
Preparing Project Proposal and 08-08-2023 08-08-2023 Ghule Akash
2
Approval
28-08-2023 28-08-2023 Dhondge Piyush
3 Implementing Project
04-09-2023 04-09-2023 Ghule Akash
4 Preparing Project Report
02-10-2023 02-10-2023 Patil Om
5 Presenting Project
09-10-2023 09-10-2023 Dhondge Piyush
6 Submission of Project and Report
5.0. Actual Resources Used (Mention the actual resources used)
Sr.
Name of Resource/Material Specifications Qty. Remarks
No.
1 Computer System I5 3rd gen, 8gb RAM 01
2 Development Package C,C++ Online Compiler 01
Sublime Text or
3 Editor 01
VS Code edior
4 Online C Compiler [Link] 01
6.0. Output of the Micro-Project
If B is on, the switch is closed.
If B is off, the switch is open.
A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and
high-impedance (Z).
Each logic gate and logic family has unique electrical and electronics characteristic so they are unique
and we can optimize them in circuit design by understanding their functionality and behavior.
7.0. Skill Developed/Learning outcomes of Logic gates
1) Students will learn what logic gates are and how they represent logical operations.
2) Students will use logic gates to transform Boolean inputs into outputs that accomplish a goal. .
3) Students will become familiar with Boolean logic and truth tables
4)
5)
MET’s Institute of Technology, Polytechnic, Nashik 7
8.0. Application of Logic gates
1. In manufacturing more complex devices e.g. binary counters etc.
2. In decision–making regarding automatic control of machines and different industrial processes
3. In calculators and computers
4. In digital measuring techniques
5. In digital processing of communications
6. In musical instruments, games and different domestic appliances
MET’s Institute of Technology, Polytechnic, Nashik 8
Annexure - IV
Micro-Project Evaluation Sheet
Name of Student:Dhondge Piyush Jagdish Enrollment No: 23611470243
Name of Programme: Computer Engineering Semester: Third
Course Title: Digital Techniques Code: 22320
Title of the Micro-Project: Report on logic gates
Course Outcomes Achieved:-
a) Use Number System and codes for interpreting working of Addressed
digital system
b) Use Boolean expressions to realize logic circuits Not Addressed
c) Build simple combinational circuits Not Addressed
d) Build simple Sequential circuits Addressed
e) Test data converters and PLDs in digital electronics systems Not Addressed
Sr. Characteristics to be Poor Average Good Excellent Sub-
No. assessed (Marks 1-3) (Marks 4-5) (Marks 6-8) (Marks 9-10) Total
(A) Process and Product Assessment (Convert above total marks out of 6 Marks)
1 Relevance to the course
Literature Review/
2
Information Collection
Completion of the Target
3
as per Project Proposal
Analysis of Data and
4
Representation
Quality of
5
Prototype/Model
6 Report Preparation
(B) Individual Presentation/Viva (Convert above total marks out of 4 Marks)
7 Presentation
8 Viva
(A) Process and Product Assessment (B) Individual Presentation/Viva Total Marks
(6 Marks) (4 Marks) (10 Marks)
Comments/Suggestions about team work/leadership/inter-personal communication (if any)
Name and Designation of the Teacher: Prof. Swati D. Jadhav
Dated Signature:
MET’s Institute of Technology, Polytechnic, Nashik 9
Annexure - IV
Micro-Project Evaluation Sheet
Name of Student:Ghule Akash Bhausaheb Enrollment No: 23611470239
Name of Programme: Computer Engineering Semester: Third
Course Title: Digital Techniques Code: 22320
Title of the Micro-Project: Report on logic gates
Course Outcomes Achieved:-
a) Use Number System and codes for interpreting working of Addressed
digital system
b) Use Boolean expressions to realize logic circuits Not Addressed
c) Build simple combinational circuits Not Addressed
d) Build simple Sequential circuits Addressed
e) Test data converters and PLDs in digital electronics systems Not Addressed
Sr. Characteristics to be Poor Average Good Excellent Sub-
No. assessed (Marks 1-3) (Marks 4-5) (Marks 6-8) (Marks 9-10) Total
(A) Process and Product Assessment (Convert above total marks out of 6 Marks)
1 Relevance to the course
Literature Review/
2
Information Collection
Completion of the Target
3
as per Project Proposal
Analysis of Data and
4
Representation
Quality of
5
Prototype/Model
6 Report Preparation
(B) Individual Presentation/Viva (Convert above total marks out of 4 Marks)
7 Presentation
8 Viva
(A) Process and Product Assessment (B) Individual Presentation/Viva Total Marks
(6 Marks) (4 Marks) (10 Marks)
Comments/Suggestions about team work/leadership/inter-personal communication (if any)
Name and Designation of the Teacher: Prof. Swati D. Jadhav
Dated Signature:
MET’s Institute of Technology, Polytechnic, Nashik 10
Annexure - IV
Micro-Project Evaluation Sheet
Name of Student:Patil Om Sharad Enrollment No:23611470241
Name of Programme: Computer Engineering Semester: Third
Course Title: Digital Techniques Code: 22320
Title of the Micro-Project: Report on logic gates
Course Outcomes Achieved:-
a) Use Number System and codes for interpreting working of Addressed
digital system
b) Use Boolean expressions to realize logic circuits Not Addressed
c) Build simple combinational circuits Not Addressed
d) Build simple Sequential circuits Addressed
e) Test data converters and PLDs in digital electronics systems Not Addressed
Sr. Characteristics to be Poor Average Good Excellent Sub-
No. assessed (Marks 1-3) (Marks 4-5) (Marks 6-8) (Marks 9-10) Total
(A) Process and Product Assessment (Convert above total marks out of 6 Marks)
1 Relevance to the course
Literature Review/
2
Information Collection
Completion of the Target
3
as per Project Proposal
Analysis of Data and
4
Representation
Quality of
5
Prototype/Model
6 Report Preparation
(B) Individual Presentation/Viva (Convert above total marks out of 4 Marks)
7 Presentation
8 Viva
(A) Process and Product Assessment (B) Individual Presentation/Viva Total Marks
(6 Marks) (4 Marks) (10 Marks)
Comments/Suggestions about team work/leadership/inter-personal communication (if any)
Name and Designation of the Teacher: Prof. Swati D. Jadhav
Dated Signature:
MET’s Institute of Technology, Polytechnic, Nashik 11
MET’s Institute of Technology, Polytechnic, Nashik 12