Chapter 4

Modules and Ports

教師: 陳銘志

Electronic Engineering, NKFUST 1

 Learning Objects
 Identify the components of a Verilog module
definition.
 Understand how to define the port list for a
module and declare it in Verilog.
 Describe the port connection rules in a module
instantiation.
 Understand how to connect ports to external
signals, by ordered list, and by name.
 Explain hierarchical name referencing of Verilog
identifiers.

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 Modules
 Five components: variable declarations, dataflow
statements, instantiation of lower modules, behavioral
blocks, and tasks or functions.

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 SR Latch
// This example illustrates the different components of a module
// Module name and port list
// SR_latch module
module SR_latch(Q, Qbar, Sbar, Rbar);
//Port declarations
output Q, Qbar;
input Sbar, Rbar;
// Instantiate lower-level modules
// In this case, instantiate Verilog primitive nand gates
// Note, how the wires are connected in a cross-coupled fashion.
nand n1(Q, Sbar, Qbar);
nand n2(Qbar, Rbar, Q);
// endmodule statement
endmodule

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// Module name and port list
// Stimulus module
module Top;
// Declarations of wire, reg, and other variables
wire q, qbar;
reg set, reset;
// Instantiate lower-level modules
// In this case, instantiate SR_latch
// Feed inverted set and reset signals to the SR latch
SR_latch m1(q, qbar, ~set, ~reset);
// Behavioral block, initial
initial
begin
$monitor($time, " set = %b, reset= %b, q= %b\n",set,reset,q);
set = 0; reset = 0;
#5 reset = 1;
#5 reset = 0;
#5 set = 1;
end
// endmodule statement
endmodule
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 Ports
 If the module does not exchange any signals
with the environment, there are no ports in the
list.
No ports are
declared in the
Top module

Ports are declared in

the instance (full
adder)

module fulladd4(sum, c_out, a, b, c_in); //Module with a list of ports

module Top; // No list of ports, top-level module in simulation
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 Port Declaration (1)
Verilog Keyword Type of Port
input Input port
output Output port
inout Bidirectional port

module fulladd4(sum, c_out, a, b, c_in);

//Begin port declarations section
output[3:0] sum;
output c_cout;
input [3:0] a, b;
input c_in;
//End port declarations section
...
<module internals>
...
endmodule
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 Port Declaration (2)
 All port declarations are implicitly declared as
wire in Verilog.
 If output ports hold their value, they must be
declared as reg.
 Ports of the type input and inout cannot be
declared as reg because reg variables store
values and input ports should not store values
but simply reflect the changes in the external
signals they connected to.

Electronic Engineering, NKFUST 8

 Port Declaration (3)
module DFF (q, d, clk, reset);
output q;
reg q; // Output port q holds value; therefore it is declared as reg.
input d, clk, reset;
...
...
endmodule

module fulladd4 (output reg [3:0] sum,

output reg c_out,
input [3:0] a, b, //wire by default
input c_in); //wire by default
...
<module internals>
...
endmodule
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Port Connection Rules

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 Unconnected Ports
 Verilog allows ports to remain unconnected.

fulladd4 fa0(SUM, , A, B, C_IN); // Output port c_out is unconnected

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 Example of illegal port connection
 This problem is rectified if the variable SUM is declared as a net (wire).
module Top;
//Declare connection variables
reg [3:0]A,B;
reg C_IN;
reg [3:0] SUM;
wire C_OUT;
//Instantiate fulladd4, call it fa0
fulladd4 fa0(SUM, C_OUT, A, B, C_IN);
//Illegal connection because output port sum in module fulladd4
//is connected to a register variable SUM in module Top.
.
.
<stimulus>
.
.
endmodule
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 Connecting Ports to External Signals
 Two methods:
 Connecting by ordered list
 Connecting ports by name

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 module Top;
//Declare connection variables
reg [3:0]A,B;
reg C_IN;
wire [3:0] SUM;
wire C_OUT;
//Instantiate fulladd4, call it fa_ordered.
Connecting //Signals are connected to ports in order (by position)
by Ordered fulladd4 fa_ordered(SUM, C_OUT, A, B, C_IN);
List
...
<stimulus>
...
endmodule
module fulladd4(sum, c_out, a, b, c_in);
output[3:0] sum;
output c_cout;
input [3:0] a, b;
input c_in;
...
<module internals>
...
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endmodule
 Connecting ports by name
// Instantiate module fa_byname and connect signals to ports by name
fulladd4 fa_byname(.c_out(C_OUT), .sum(SUM), .b(B), .c_in(C_IN), .a(A),);

// Instantiate module fa_byname and connect signals to ports by name

fulladd4 fa_byname(.sum(SUM), .b(B), .c_in(C_IN), .a(A),);

 Unconnected ports can be dropped.

 Advantage: The order of ports in the port list of a module can be
rearranged without changing the port connections in module
instantiations.
 Eq.: C_out port was unconnected, it can be dropped from the
port list.

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 Hierarchical Names
 A hierarchical name is a list of identifiers
separated by dots (.).
 Hierarchical name referencing allows us to
denote every identifier in the design hierarchy
with a unique name.

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Design Hierarchy for SR Latch
Simulation

stimulus stimulus.q
[Link] [Link]
[Link] stimulus.m1
stimulus.m1.Q [Link]
stimulus.m1.S stimulus.m1.R
stimulus.n1 stimulus.n2
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 Summary
 Module definitions contain various components.
 Ports provide the module with a means to
communicate with other modules or its
environment.
 Ports can be connected by name or by ordered
list.
 Each identifier in the design has a unique
hierarchical name.

Electronic Engineering, NKFUST 18