BANGLADESH UNIVERSITY OF ENGINEERING AND TECHNOLOGY
Department of Electrical and Electronic Engineering
EEE 102: Electrical Circuits I Laboratory
Experiment No: 02
Experiment Name: Simulating Circuits with Dependent Sources in PSpice.
Name : RAFIA AKTER Student ID : 2306118
Partner’s Student ID : 2306117
Level : 1
Term : 1
Section : B2
Date of Experiment : 03.11.2024
Date of submission : 01.12.2024
Objective
Main objectives of this experiments are to–
•Demonstrate the DC transient analysis of RL circuits.
•Demonstrate the DC transient analysis of RC circuits.
All parts are executed by computer simulation using PSPICE. Simulation is done by both
creating netlist and using schematics.
Theory
Energy delivered by a source can be stored in an inductor or capacitor. Once initial
conditions are known, a voltage in a capacitor (V0) and current in an inductor (I0), the
application of Kirchhoff’s laws results in the circuit equations that will yield the voltage
and current relationships with time. The definitions of the current/voltage relationships
are applied for the storage elements and for resistors (Ohm’s Law) and again, first order
ordinary differential equations result.
The solution leads to equations that define an exponential build up with time of any
energy that is stored.
In both instances, the growth in current and voltage is exponential with time to a final
value determined by the circuit.
The time constant τ is defined as shown to characterize the exponential growth in
current/voltage in the inductor/capacitor. It does this through the factor .After a
time-interval of 5 time-constants, the factor is within 1% of its final value.
Procedures
#Netlist
1.“PSpice AD” was run, then went to File > New > Text File.
[Link] the new window, the required code for circuit construction was typed.
[Link] description of Inductor is written as:
L<name> N+ N- L_value IC = <value>(Initial Condition)
[Link] description of Capacitor is written as:
C<name> N+ N- C_value IC = <value>(Initial Condition)
[Link] of .TRAN command for Transient Analysis:
.TRAN prt_stp t_max prt_dly max_stp UIC
•prt_stp =Frequency with which data is saved
•t_max =Time when simulation to be ended
•prt_dly =Marker to a time from when simulation will be shown
•max_ stp=Maximum time step PSpice allowed to take in the simulation
•UIC =For applying initial conditions
#Schematic
1.“PSpice design manager” was run, then went to “Run Schematics”.
2.A new window appeared. There the given circuit diagram was created as a circuit
Schematic.
[Link] conditions and values for inductor(s), capacitor(s) and switch(s)were set.
[Link] analysis was checked in setup analysis.
[Link] step, final time, no print delay and step ceiling were set accordingly.
[Link] circuit was simulated and necessary traces were added.
Part 1
Circuit Diagram:
Theoretical values:
Netlist Simulation Input:
Netlist Simulation Result:
Current vs time graph for the inductor:
From the above graph,
Current through the inductor becomes 63.2% of maximum current after 1ms.
∴Time constant, τ= 1ms
Here, time constant is exactly same as I got from theoretical calculation.
Voltage vs time graph for the inductor:
Power vs time graph for the inductor:
Energy vs time graph for the inductor:
Schematic Circuit Diagram:
Schematic Simulation Result:
Current vs time graph for the inductor:
Voltage vs time graph for the inductor:
Power vs time graph for the inductor:
Energy vs time graph for the inductor:
After setting Inductance to 1mH
Theoretical values:
Netlist Simulation Input:
Netlist Simulation Result:
Current vs time graph for the inductor:
From the above graph,
Current through the inductor becomes 63.2% of maximum current after 1μs.
∴Time constant, τ= 1μs
Here, time constant is exactly same as I got from theoretical calculation.
Voltage vs time graph for the inductor:
Power vs time graph for the inductor:
Energy vs time graph for the inductor:
Schematic Circuit Diagram:
Schematic Simulation Result:
Current vs time graph for the inductor:
Voltage vs time graph for the inductor:
Power vs time graph for the inductor:
Energy vs time graph for the inductor:
After setting Initial Condition to 5mA
Theoretical values:
Netlist Simulation Input:
Netlist Simulation Result:
From the above graph,
Final current of the inductor = 9.996 mA
90% of this current is = 8.97 mA
This current is obtained when time ≈ 1.6ms
∴After 1.6ms, inductor current rises to 90% of its final value which is equal to the value
obtained from theoretical analysis.
Schematic Circuit Diagram:
Schematic Simulation Result:
Part 2
Circuit Diagram:
Theoretical values:
Netlist Simulation Input:
Netlist Simulation Result:
Voltage vs time graph for the capacitor:
From the above graph,
Voltage across the inductor becomes 63.2% of maximum voltage after 1ms.
∴Time constant, τ= 1ms
Here, time constant is exactly same as I got from theoretical calculation.
Current vs time graph for the capacitor:
Power vs time graph for the capacitor:
Schematic Circuit Diagram:
Schematic Simulation Result:
Voltage vs time graph for the capacitor:
Current vs time graph for the capacitor:
Power vs time graph for the capacitor:
Energy vs time graph for the capacitor:
After settingCapacitanceto10μF:
Theoretical values:
When time approaches infinity,
R = 1 kΩ, C = 10μF
∴Time constant, τ= RC
= 1 kΩ × 10μF
= 10ms
Netlist Simulation Input:
Netlist Simulation Result:
Voltage vs time graph for the capacitor:
From the above graph,
Voltage across the inductor becomes 63.2% of maximum voltage after 1ms.
∴Time constant, τ= 10ms
Here, time constant is exactly same as I got from theoretical calculation.
Current vs time graph for the capacitor:
Power vs time graph for the capacitor:
Energy vs time graph for the capacitor:
Schematic Circuit Diagram:
Schematic Simulation Result:
Voltage vs time graph for the capacitor:
Current vs time graph for the capacitor:
Power vs time graph for the capacitor:
Energy vs time graph for the capacitor:
After setting Initial Condition to 5V
Theoretical values:
Netlist Simulation Input:
Netlist Simulation Result:
From the above graph,
Final capacitor voltage= 9.966V
90% of this voltage is = 8.97V
This voltage is obtained when time ≈ 1.6ms
∴After 1.6ms, capacitor voltage rises to 90% of its final value which is equal to the value
obtained from theoretical analysis.
Schematic Circuit Diagram:
Schematic Simulation Result:
Discussion:
In this experiment, we plotted necessary traces after transient analysis of RL and RC
circuit with DC current and voltage source.
In this experiment, we got perfect curvature in graphs of each scenario. That’s what is
expected as we used transient sin voltage source. In PSpice, we can use internal
resistance free ammeter, voltmeter with infinite internal resistance and internal
resistance free voltage source. That’s why we can see a perfect sinusoidal wave shape.
Practically such a thing does not happen. We have neither ideal ammeter nor ideal
voltmeter nor internal resistance free voltage source. That’s why, some deviations are
found in the results of real life experiments. Thus, this is an advantage to use PSpice. We
can get the exact and absolute result.