CHAPTER 1
VLSI DESIGN
1.1 Introduction to VLSI
Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by
combining thousands of transistors into a single chip.
VLSI began in the 1970s when complex semiconductor and communication technologies were
being developed.
The microprocessor is a VLSI device.
Before the introduction of VLSI technology, most ICs had a limited set of functions they could
perform.
An electronic circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI lets IC
designers add all of these into one chip.
The electronics industry has achieved a phenomenal growth over the last few decades, mainly
due to the rapid advances in large scale integration technologies and system design
applications.
With the advent of very large scale integration (VLSI) designs, the number of applications of
integrated circuits (ICs) in high-performance computing, controls, telecommunications, image
and video processing, and consumer electronics has been rising at a very fast pace.
The current cutting-edge technologies such as high resolution and low bit-rate video and
cellular communications provide the end-users a marvelous amount of applications, processing
power and portability. This trend is expected to grow rapidly, with very important implications
on VLSI design and systems design.
1.2 VLSI Design Flow
The VLSI IC circuits design flow is shown in the figure below. The various levels of design
are numbered and the blocks show processes in the design flow.
Fig.1 : Simplified VLSI Design Flow
1. Specifications comes first, they describe abstractly, the functionality, interface, and
the architecture of the digital IC circuit to be designed.
2. Behavioral description is then created to analyze the design in terms of
functionality, performance, compliance to given standards, and other
specifications.
3. RTL description is done using HDLs. This RTL description is simulated to test
functionality. From here onwards we need the help of EDA tools.
4. RTL description is then converted to a gate-level net list using logic synthesis tools.
A gate level net list is a description of the circuit in terms of gates and connections
between them, which are made in such a way that they meet the timing, power and
area specifications.
5. Finally, a physical layout is made, which will be verified and then sent to
fabrication.
1.3 Y Chart
The Gajski-Kuhn Y-chart is a model, which captures the considerations in designing
semiconductor [Link] three domains of the Gajski-Kuhn Y-chart are on radial axes.
CHAPTER 2
HDL Coding Concepts
2.1 Hardware Description Language (HDL)
In electronics, a hardware description language or HDL is any language from a class of
computer languages and/or programming languages for formal description of digital logic
and electronic circuits. It can describe the circuit's operation, its design and organization, and
tests to verify its operation by means of simulation. HDLs are standard text-based expressions
of the spatial and temporal structure and behaviour of electronic systems. In contrast to a
software programming language, HDL syntax and semantics include explicit notations for
expressing time and concurrency, which are the primary attributes of hardware. Languages
whose only characteristic is to express circuit connectivity between hierarchies of blocks are
properly classified as netlist languages used on electric computer-aided design (CAD). HDLs
are used to write executable specifications of some piece of hardware. A simulation program,
designed to implement the underlying semantics of the language statements, coupled with
simulating the progress of time, provides the hardware designer with the ability to model a
piece of hardware before it is created physically. It is this executability that gives HDLs the
illusion of being programming languages. Simulators capable of supporting discreteevent
(digital) and continuous-time (analog) modeling exist, and HDLs targeted for each are
available.
2.2 Design using HDL
The vast majority of modern digital circuit design revolves around an HDL description of the
desired circuit, device, or subsystem. Most designs begin as a written set of requirements or a
high-level architectural diagram. The process of writing the HDL description is highly
dependent on the designer's background and the circuit's nature. The HDL is merely the
'capture language'—often begin with a high-level algorithmic description such as MATLAB
or a C++ mathematical model. Control and decision structures are often prototyped in
flowchart applications, or entered in a state-diagram editor. Designers even use scripting
languages (such as Perl) to automatically generate repetitive circuit structures in the HDL
language. Advanced text editors (such as Emacs) offer editor templates for automatic
indentation, syntaxdependent coloration, and macro-based expansion of
entity/architecture/signal declaration.
As the design's implementation is fleshed out, the HDL code invariably must undergo code
review, or auditing. In preparation for synthesis, the HDL description is subject to an array of
automated checkers. The checkers enforce standardized code a guideline, identifying
ambiguous code constructs before they can cause misinterpretation by downstream synthesis,
and check for common logical coding errors, such as dangling ports or shorted [Link]
industry parlance, HDL design generally ends at the synthesis stage. Once the synthesis tool
has mapped the HDL description into a gate netlist, this netlist is passed off to the back-end
stage. Depending on the physical technology (FPGA, ASIC gate-array, ASIC standard-cell),
HDLs may or may not play a significant role in the back-end flow. In general, as the design
flow progresses toward a physically realizable form, the design database becomes
progressively more laden with technology-specific information, which cannot be stored in a
generic HDL-description. Finally, a silicon chip is manufactured in a fab.
2.3 HDL and programming languages
A HDL is analogous to a software programming language, but with major differences.
Programming languages are inherently procedural (single-threaded), with limited syntactical
and semantic support to handle concurrency. HDLs, on the other hand, can model multiple
parallel processes (such as flipflops, adders, etc.) that automatically execute independently of
one another. Any change to the process's input automatically triggers an update in the
simulator's process stack. Both programming languages and HDLs are processed by a
compiler (usually called a synthesizer in the HDL case), but with different goals. For HDLs,
'compiler' refers to synthesis, a process of transforming the HDL code listing into a physically
realizable gate netlist. The netlist output can take any of many forms: a "simulation" netlist
with gate-delay information, a "handoff" netlist for post-synthesis place and route, or a
generic industry-standard EDIF format (for subsequent conversion to a JEDEC-format file).
On the other hand, a software compiler converts the source-code listing into a
microprocessor-specific objectcode, for execution on the target microprocessor. As HDLs and
programming languages borrow concepts and features from each other, the boundary between
them is becoming less distinct. However, pure HDLs are unsuitable for general purpose
software application development, just as general-purpose programming languages are
undesirable for modeling hardware. Yet as electronic systems grow increasingly complex, and
reconfigurable systems become increasingly mainstream, there is growing desire in the
industry for a single language that can perform some tasks of both hardware design and
software programming. SystemC is an example of such—embedded system hardware can be
modeled as non-detailed architectural blocks (blackboxes with modeled signal inputs and
output drivers). The target application is written in C/C++, and natively compiled for the
host-development system (as opposed to targeting the embedded CPU, which requires host-
simulation of the embedded CPU). The high level of abstraction of SystemC models is well
suited to early architecture exploration, as architectural modifications can be easily evaluated
with little concern for signal-level implementation issues. In an attempt to reduce the
complexity of designing in HDLs, which have been compared to the equivalent of assembly
languages, there are moves to raise the abstraction level of the design. Companies such as
Cadence, Synopsys and Agility Design Solutions are promoting SystemC as a way to
combine high level languages with concurrency models to allow faster design cycles for
FPGAs than is possible using traditional HDLs. Approaches based on standard C or C++
(with libraries or other extensions allowing parallel programming) are found in the Catapult
C tools from Mentor Graphics, and in the Impulse C tools from Impulse Accelerated
Technologies. Annapolis Micro Systems, Inc.'s CoreFire Design Suite and National
Instruments LabVIEW FPGA provide a graphical dataflow approach to high-level design
entry. Languages such as SystemVerilog, SystemVHDL, and Handel-C seek to accomplish
the same goal, but are aimed at making existing hardware engineers more productive versus
making FPGAs more accessible to existing software engineers. Thus SystemVerilog is more
quickly and widely adopted than SystemC. There is more information on C to HDL and Flow
to HDL in their respective articles.
CHAPTER 3
COMBINATIONAL CIRCUITS
3.1 WHAT ARE COMBINATIONAL CIRCUITS
Combinational circuit is a circuit in which we combine the different gates in the circuit, for
example encoder, decoder, multiplexer and demultiplexer. Some of the characteristics of
combinational circuits are following −
The output of combinational circuit at any instant of time, depends only on the levels
present at input terminals.
The combinational circuit do not use any memory. The previous state of input does
not have any effect on the present state of the circuit.
A combinational circuit can have an n number of inputs and m number of outputs.
Block diagram
We're going to elaborate few important combinational circuits as follows.
3.2 Half Adder
Half adder is a combinational logic circuit with two inputs and two outputs. The half adder
circuit is designed to add two single bit binary number A and B. It is the basic building block
for addition of two single bit numbers. This circuit has two outputs carry and sum.
Block diagram
Truth Table
Circuit Diagram
3.3 Full Adder
Full adder is developed to overcome the drawback of Half Adder circuit. It can add two one-
bit numbers A and B, and carry c. The full adder is a three input and two output
combinational circuit.
Block diagram
Truth Table
Circuit Diagram
3.4 Half Subtractors
Half subtractor is a combination circuit with two inputs and two outputs (difference and
borrow). It produces the difference between the two binary bits at the input and also produces
an output (Borrow) to indicate if a 1 has been borrowed. In the subtraction (A-B), A is called
as Minuend bit and B is called as Subtrahend bit.
Truth Table
Circuit Diagram
3.5 Full Subtractors
The disadvantage of a half subtractor is overcome by full subtractor. The full subtractor is a
combinational circuit with three inputs A,B,C and two output D and C'. A is the 'minuend', B
is 'subtrahend', C is the 'borrow' produced by the previous stage, D is the difference output
and C' is the borrow output.
Truth Table
Circuit Diagram
Chapter 4
FINITE STATE MACHINES
The finite state machines (FSMs) are significant for understanding the decision making logic
as well as control the digital systems. In the FSM, the outputs, as well as the next state, are a
present state and the input function. This means that the selection of the next state mainly
depends on the input value and strength lead to more compound system performance. As in
sequential logic, we require the past inputs history for deciding the output. Therefore FSM
proves very cooperative in understanding sequential logic roles. Basically, there are two
methods for arranging a sequential logic design namely mealy machine as well as more
machine. This article discusses the theory and implementation of a finite state machine or FSM,
types, finite state machine examples, advantages, and disadvantages.
The definition of a finite state machine is, the term finite state machine (FSM) is also known
as finite state automation. FSM is a calculation model that can be executed with the help of
hardware otherwise software. This is used for creating sequential logic as well as a few
computer programs. FSMs are used to solve the problems in fields like mathematics, games,
linguistics, and artificial intelligence. In a system where specific inputs can cause specific
changes in state that can be signified with the help of FSMs.
This finite state machine diagram explains the various conditions of a turnstile. Whenever
placing a coin into a turnstile will unbolt it, and after the turnstile has been pressed, it bolts
gain. Placing a coin into an unbolted turnstile, otherwise pressing against a bolted turnstile will
not alter its state.
CHAPTER 5
SYSTEM DESIGN USING FPGA
5.1 INTRODUCTION
5.1.1 BACKGROUND
In the realm of digital system design, Field-Programmable Gate Arrays (FPGAs) have
emerged as a powerful and flexible solution. Unlike traditional Application-Specific
Integrated Circuits (ASICs), FPGAs allow for the dynamic reprogramming of logic functions,
making them ideal for prototyping, rapid development, and applications where customization
is crucial.
5.1.2 OBJECTIVE
The objectives of system design using FPGA encompass leveraging the reconfigurability of
FPGAs to implement custom digital circuits efficiently. This includes understanding the
FPGA architecture, employing hardware description languages (HDLs) for design, and
optimizing the system for performance and resource utilization.
5.2 FPGA Technology Overview:
FPGAs consist of an array of programmable logic blocks interconnected through
programmable routing resources. This section explains the basic building blocks, including
look-up tables (LUTs), configurable logic blocks (CLBs), and programmable
[Link] the programming paradigm of FPGAs, focusing on the configuration
bitstream that defines the logic functionality. The reprogrammability of FPGAs allows
iterative design refinement without the need for hardware redesign. Highlighting the
advantages of FPGAs, such as parallelism, customization, and rapid prototyping. Their ability
to handle diverse applications, from digital signal processing to cryptographic algorithms,
makes them versatile in various domains. Define the targeted system, outlining its purpose,
key features, and expected performance. This phase involves collaboration with stakeholders
to ensure alignment with project goals. Discussing the overall architecture of the system,
identifying major functional blocks, and determining which components can benefit from
hardware acceleration on the FPGA. Partitioning tasks between FPGA hardware and software
running on embedded processors is crucial at this stage.
5.3FPGA Design Flow:
An in-depth look into hardware description languages, such as Verilog or VHDL, used to
define the system's behavior. Describing how the high-level design is translated into HDL
code and how the code reflects the intended hardware [Link] the synthesis
process, where the HDL code is translated into a netlist representing the circuit.
Subsequently, the place-and-route step maps the design onto the physical resources of the
FPGA. Tools like Xilinx Vivado or Intel Quartus are commonly used in this phase.
Addressing timing considerations, including clock domains, setup and hold times, and critical
paths. Discussing techniques for ensuring that the design meets timing requirements.
Exploring the utilization of Intellectual Property (IP) cores and pre-designed libraries to
expedite the design process. These cores can include processors, memory blocks,
communication interfaces, and more. Detailing the simulation process to verify the
correctness of the design before implementation on the FPGA. This involves creating
testbenches and using simulation tools to validate the HDL code. Discussing strategies for
testing the implemented design on the physical FPGA, including debugging techniques and
tools.