CHAPTER 5
INPUT/OUTPUT
SYSTEMS
Introduction
• I/O Module is the third key element of a
computer system.
• It is the responsibility of the module to control
the external devices and the transfer of data
between those devices and memory and/or
CPU registers
Input/output Problems
• Reasons why peripherals can’t directly connect
to the system bus are:
– Wide variety of peripherals with various
method of operation.
– The data transfer rate is much slower than
memory or CPU.
– Use different data formats and word length.
• Thus Input/output Module is required:
– Interface to CPU and Memory via system bus.
– Interface to one or more peripherals by data
links.
External Devices
• I/O operations are accomplished by external devices that
provide a means of exchanging data between the
external environment and the computer.
• External Devices connected to I/O module are called
peripherals. Three categories are:
Human readable: for communicating with computer
user. Ex. Screen, printer, keyboard
Machine readable: for communicating with (Monitoring
and control) equipments. Ex. Disk drive, sensors.
Communication: for communicating with remote
devices. Ex. Modem, Network Interface Card (NIC)
Control signals
determine the function
that the device will
perform, such as:
Send data to the I/O
module (INPUT or
READ), accept data
from the I/O module
(OUTPUT or WRITE),
Report status, or
Perform some control
function particular to
the device (e.g.,
position a disk head).
Data are in the form of a set of bits to be sent to
or received from the I/O module.
Status signals indicate the state of the device.
Examples are READY/NOT-READY
Control logic controls the device’s operation in
response to direction from the I/O module.
Transducer converts data from electrical to other
forms of energy during output and from other
forms to electrical during input.
Buffer is associated with the transducer to
temporarily hold data being transferred between
the I/O module and the external environment.
I/O Module Functions:
Control & Timing: coordinates the flow of data
between internal resources and external devices
CPU Communication: involves command decoding,
data, status reporting, and address recognition.
Device Communication: involves commands, data, and
status information.
Data Buffering: essential task. Data transfer rate is
quite different. The I/O module operate at both
devices and memory speed.
Error Detection: errors including mechanical and
electrical malfunctions (reported by device) report to
CPU. Ex. Paper jam, bad disk track
I/O Steps
CPU checks I/O module device status
I/O module returns status
If ready, CPU requests data transfer
I/O module gets/transfers data from/to device
I/O module transfers/gets data to/from CPU
I/O module structure
General I/O module block diagram
• Signal lines (system bus) connect it to computer.
• Data registers buffer data transfer to and from
the module.
• Status registers provide current status
information.
• Control registers accept detailed control
information from CPU.
• I/O logic receives commands from CPU for the
module through the control lines.
– Each module has a unique (set of) address
– The module must recognize and generate address
(set of addresses) for the device(s)
Two possible addressing modes, since main
memory, CPU, and I/O share common bus:
1. Memory-mapped I/O:
a single address space for memory and I/O
device.
CPU treats I/O module as memory locations
and use the same machine instructions.
Ex. With 10 address lines 210 memory
locations and I/O addresses can be supported.
2. Isolated I/O:
I/O address space is isolated from memory.
Bus is equipped with memory read/write and
input/output command lines.
The command line specifies whether the
address refers to a memory location or I/O
device
Full range of address is available for both.
Ex. With 10 address lines, 1024 memory
location and 1024 I/O addresses are supported.
Input Output Techniques
• Three techniques are possible for I/O
operations:
– Programmed
– Interrupt driven
– Direct Memory Access (DMA)
Programmed I/O
• CPU executes a program to directly control I/O
operation including:
– Sensing device status
– Sending Read/write commands
– Transferring data
• Does not interrupt CPU, but periodically checks
the status of I/O module.
• CPU waits for I/O module to complete operation
• Wastes CPU time
Programmed I/O – operation
• CPU requests I/O operation
• I/O module performs the operation and sets
status bits but does not take further action to
alert CPU
• CPU checks status bits periodically until
operation is complete.
• I/O module does not interrupt CPU
Interrupt driven I/O
• Overcomes CPU waiting in programmed I/O
• No repeated CPU checking of device
• I/O module interrupts when ready
Basic Operation
• CPU issues read command
• I/O module gets data from peripheral whilst CPU
does other work
• I/O module interrupts CPU
• CPU requests data
• I/O module transfers data
CPU Viewpoint
• Issue read command
• Do other work
• Check for interrupt at the end of each
instruction-cycle
• If interrupted:-
– Save context (registers) of current program
– Process interrupt
• Fetch data & store
I/O module viewpoint
• Receives read command
• Proceed to read data from associated peripheral
to data register of the module
• Signals an interrupt to CPU through control lines
• Wait until requested by CPU
• If requested, it places the data on data bus and
is ready for another I/O operation
Direct Memory Access
• Interrupt driven and programmed I/O require
active CPU intervention
– Transfer rate is limited
– CPU is tied up in managing an I/O transfer
• DMA is more efficient technique to transfer large
volume of data
DMA Function:
• Additional Module (hardware) is involved on bus
• DMA controller takes over system control from
CPU for I/O
DMA Module Diagram
DMA Operation
• CPU issue commands to DMA controller :-
– Read/Write
– Device address
– Starting address of memory block for data
– Amount of data to be transferred
• CPU carries on with other work
• DMA controller deals with transfer of data with
out going through the CPU
• DMA controller sends interrupt when finished
• CPU is involved only at the beginning and end
of data transfer
• Cycle-stealing: DMA forces the CPU to
temporarily suspend operation (data transfer)
to take control of the bus