Jadavpur University
Department of Electronics and Tele-Communication Engineering
Faculty of Engineering and Technology
IC Design Lab Report
Name : Adway Paul
Roll No : 002110701102
Class :UG-III Sem-6
Group : G2
1
INDEX
Sl. No. Name of experiments
1 Dataflow modeling of half adder
2 Behavioral modeling of half adder
3 Dataflow modeling of 2-to-4 decoder
4 Behavioural modeling of 2-to-4 decoder
5 1 bit full adder using half adder
6 3-to-8 decoder using 2-to-4 decoder
7 2-to-4 decoder
8 4-bit up counter
9 4-bit left shift register
10 Multiplexed 7-segment display
11 Resistive Load Inverter with NMOS
12 CMOS Inverter
13 NAND Using CMOS
14 NOR Using CMOS
15 PMOS Load Inverter (DC)
16 PMOS Load Inverter (AC)
17 CMOS Load Inverter
18 CMOS NAND gate
19 CMOS NOR gate
20 FSM Design using Synopsys Tools
2
VERILOG BASED EXPERIMENTS
1. Dataflow modeling of half adder :
● Circuit Diagram :
● Program :
module HA_DF(input A,B,output S,C);
assign S=A^B;
assign C=A&B;
endmodule
● Output :
2. Behavioral modeling of half adder :
● Circuit Diagram :
● Program :
3
module HA_BEHV(input A,B,output reg S,C);
always @(A,B)
begin
if(A!=B)
S=1;
else S=0;
end
always @(A,B)
begin
if(A==1 && B==1)
C=1;
else C=0;
end
endmodule
● Output :
3. Dataflow modeling of 2-to-4 decoder :
● Circuit Diagarm :
● Program :
module DEC24_DF(input E,[1:0]A, output[3:0]Y);
4
assign Y[3] = E&A[1]&A[0];
assign Y[2] = E&A[1]&(~A[0]);
assign Y[1] = E&(~A[1])&A[0];
assign Y[0] = E&(~A[1])&(~A[0]);
endmodule
● Output :
4. Behavioral modeling of 2-to-4 decoder :
● Circuit Diagram :
● Program :
module DEC24_BEHV(input E,[1:0]A, output reg [3:0]Y);
always @(E,A)
begin
if(E==1 && A==0)
Y=4'b0001;
5
else if(E==1 && A==1)
Y=4'b0010;
else if(E==1 && A==2)
Y=4'b0100;
else if(E==1 && A==3)
Y=4'b1000;
else Y=4'b0000;
end
endmodule
● Output :
5. 1 bit full adder using half adder :
● Circuit Diagram :
● Program :
module FA_HA(input cin,[1:0]X,output sum,cout);
wire s_w;
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wire[1:0]c_w;
HA_DF u0(.a(X[0]) , .b(X[1]) , .c(c_w[0]) , .s(s_w));
HA_DF u1(.a(s_w) , .b(cin) , .c(c_w[1]) , .s(sum));
assign cout = c_w[1] | c_w[0];
endmodule
● Output :
6. 3-to-8 decoder using 2-to-4 decoder :
● Program :
module DEC38(input [2:0]A1,output [7:0]Y1);
DEC24_DF u0(.E(A1[2]), .A(A1[1:0]), .Y(Y1[7:4]));
DEC24_DF u1(.E(~A1[2]), .A(A1[1:0]), .Y(Y1[3:0]));
endmodule
● Output :
VERILOG IMPLEMENTATION IN FPGA
Field Programmable Gate Arrays (FPGAs) are semiconductor devices that are based around a
matrix of configurable logic blocks (CLBs) connected via programmable interconnects. FPGAs
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can be reprogrammed to desired application or functionality requirements after
manufacturing.
In our experiments, we have used the Nexys A7 board. The Nexys A7 board is a complete,
ready-to-use digital circuit development platform based on the latest Artix-7TM Field
Programmable Gate Array (FPGA) from Xilinx®.
Family : Artix 7
Package : CSG324
Speed : -1
Device : XC7A100TCSG324-1
Clock Speed : 100 MHz
1. 2-to-4 decoder :
● Program :
8
module dec24(
input [1:0] A,
input E,
output [3:0] Y
);
assign Y[3]=E&A[1]&A[0];
assign Y[2]=E&A[1]&(~A[0]);
assign Y[1]=E&(~A[1])&A[0];
assign Y[0]=E&(~A[1])&(~A[0]);
endmodule
● Pin Connection :
set_property PACKAGE_PIN L16 [get_ports {A[1]}]
set_property PACKAGE_PIN J15 [get_ports {A[0]}]
set_property PACKAGE_PIN M13 [get_ports E]
set_property PACKAGE_PIN N14 [get_ports {Y[3]}]
set_property PACKAGE_PIN J13 [get_ports {Y[2]}]
set_property PACKAGE_PIN K15 [get_ports {Y[1]}]
set_property PACKAGE_PIN H17 [get_ports {Y[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports E]
set_property IOSTANDARD LVCMOS33 [get_ports {Y[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Y[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Y[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Y[0]}]
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2. 4 bit up counter :
● Program :
module counter(
input clk,
output reg[3:0] Y=4'b0000
);
reg clk1=0;
integer c=0;
always@(posedge clk)
begin
c=c+1;
if(c==25000000)
begin
c=0;
clk1=~clk1;
end
end
always@(posedge clk1)
begin
Y=Y+1'b1;
end
endmodule
● Pin Connection :
set_property PACKAGE_PIN E3 [get_ports CLK]
set_property PACKAGE_PIN N14 [get_ports {Y[3]}]
set_property PACKAGE_PIN J13 [get_ports{Y[2]}]
set_property PACKAGE_PIN K15 [get_ports {Y[1]}]
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set_property PACKAGE_PIN H17 [get_ports {Y[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Y[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Y[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Y[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Y[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports CLK]
● Output
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3. 4 bit left shift register :
● Program :
module Left_shift(
input clk,
output reg[3:0] Y=4'b0001
);
reg clk1=0;
integer c=0;
always@(posedge clk)
begin
c=c+1;
if(c==25000000)
begin
c=0;
clk1=~clk1;
end
end
always@(posedge clk1)
begin
Y={Y[2:0],Y[3]};
end
endmodule
● Pin Connection :
set_property PACKAGE_PIN E3 [get_ports CLK]
set_property PACKAGE_PIN N14 [get_ports {Y[3]}]
set_property PACKAGE_PIN J13 [get_ports{Y[2]}]
set_property PACKAGE_PIN K15 [get_ports {Y[1]}]
set_property PACKAGE_PIN H17 [get_ports {Y[0]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {Y[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Y[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Y[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Y[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports CLK]
● Output :
13
4. Multiplexed Seven Segment Display :
● Circuit Diagram :
● Program :
module Seg7(
input clk,
output reg[7:0] D=8'hFE,
reg[7:0] seg
);
reg clk1=0;
integer c=0;
reg[2:0]n=0;
always@(posedge clk)
begin
c=c+1;
if(c==100000)
begin
c=0;
clk1=~clk1;
end
end
always@(posedge clk1)
begin
n=n+ 1'b1;
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D={D[6:0],D[7]};
end
always@(n)
begin
case(n)
0:seg=8'h03;
1:seg=8'h9F;
2:seg=8'h25;
3:seg=8'h0D;
4:seg=8'h99;
5:seg=8'h49;
6:seg=8'h41;
7:seg=8'h1F;
default:seg=8'hFF;
endcase
end
endmodule
● Pin Connection :
set_property IOSTANDARD LVCMOS33 [get_ports {D[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {D[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {D[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {D[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {D[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {D[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {D[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {D[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {SEG[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports CLK]
set_property PACKAGE_PIN E3 [get_ports CLK]
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set_property PACKAGE_PIN U13 [get_ports {D[7]}]
set_property PACKAGE_PIN K2 [get_ports{D[6]}]
set_property PACKAGE_PIN T14 [get_ports {D[5]}]
set_property PACKAGE_PIN P14 [get_ports{D[4]}]
set_property PACKAGE_PIN J14 [get_ports {D[3]}]
set_property PACKAGE_PIN T9 [get_ports{D[2]}]
set_property PACKAGE_PIN J18 [get_ports {D[1]}]
set_property PACKAGE_PIN J17 [get_ports{D[0]}]
set_property PACKAGE_PIN T10 [get_ports {SEG[7]}]
set_property PACKAGE_PIN R10 [get_ports {SEG[6]}]
set_property PACKAGE_PIN K16 [get_ports {SEG[5]}]
set_property PACKAGE_PIN K13 [get_ports {SEG[4]}]
set_property PACKAGE_PIN P15 [get_ports {SEG[3]}]
set_property PACKAGE_PIN T11 [get_ports {SEG[2]}]
set_property PACKAGE_PIN L18 [get_ports {SEG[1]}]
set_property PACKAGE_PIN H15 [get_ports {SEG[0]}]
● Output :
When viewed through thelens of a camera with reduced exposure, we can see how the displays are activated
and deactivated clearly
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EXPERIMENTS BASED ON SPICE
In these experiments, we design schematic circuits, write netlist programs and view the
waveforms. All these have been done using the Tanner EDA software. Tanner EDA is a suite
of tools for the design of integrated circuits. These tools allow you to enter. schematics,
perform SPICE simulations, do physical design (i.e., chip layout) and perform design rules.
1. Resistive Load Inverter with NMOS :
● Schematic :
● Netlist :
RR1 Vdd Y R=10k $ $x=15 $y=400 $w=150 $h=600 $r=90
MNMOS_1 Out In Gnd 0 NMOS W=2500n L=250n AS=405f PS=2.7u AD=405f
PD=2.7u $ $x=-200 $y=-400 $w=400 h=600
VV2 Vdd Gnd DC 5 $ $x=1700 $y=200 $w=400 $h=600
VA In Gnd BIT ({0100101111} lt=10n ht=10n on=5 rt=0.1n ft=0.1n)
.include "C:\Users\Snehasish\Desktop\model lib\[Link]"
.tran 1n 400n
.print V(In) V(Out)
.end
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Waveform :
2. CMOS Inverter :
● Schematic :
● Netlist :
MNMOS_1 Y A Gnd 0 NMOS W=450n L=150n AS=405f PS=2.7u AD=405f
PD=2.7u $ $x=100 $y=100 $w=400 $h=600
MPMOS_1 Y A Vdd Vdd PMOS W=900n L=150n AS=810f PS=3.6u AD=810f
PD=3.6u $ $x=100 $y=1000 $w=400 $h=600
VV2 Vdd Gnd DC 5 $ $x=1500 $y=1100 $w=400 $h=600
VA A Gnd BIT ({0100101111} lt=10n ht=10n on=5 rt=0.1n ft=0.1n
.include "C:\Users\Snehasish\Desktop\model lib\[Link]"
.tran 1n 400n
.print V(In) V(Y)
.end
● Waveform :
18
3. NAND Using CMOS :
● Schematic :
● Netlist :
19
MNMOS_3 Y A N_1 0 NMOS W=450n L=150n AS=360f PS=2.6u AD=360f
PD=2.6u $ $x=-200 $y=-700 $w=400 $h=600
MNMOS_4 N_1 B Gnd 0 NMOS W=450n L=150n AS=360f PS=2.6u AD=360f
PD=2.6u $ $x=200 $y=-1600 $w=400 $h=600 $m
MPMOS_3 Y A Vdd Vdd PMOS W=900n L=150n AS=810f PS=3.6u AD=810f
PD=3.6u $ $x=-1200 $y=600 $w=400 $h=600
MPMOS_4 Y B Vdd Vdd PMOS W=900n L=150n AS=810f PS=3.6u AD=810f
PD=3.6u $ $x=1200 $y=600 $w=400 $h=600 $m
VV3 Vdd Gnd DC 5 $ $x=3000 $y=800 $w=400 $h=600
VA A Gnd BIT ({1110} lt=100n ht=100n on=5 rt=0.1n ft=0.1n)
VB B Gnd BIT ({0110} lt=100n ht=100n on=5 rt=0.1n ft=0.1n)
.include "C:\Users\Snehasish\Desktop\model lib\[Link]"
.tran 1n 400n
.print V(A) V(B) V(Y)
.end
● Waveform :
20
4. NOR Using CMOS :
● Schematic :
● Netlist :
MNMOS_1 Y A N_1 0 NMOS W=450n L=150n AS=360f PS=2.6u AD=360f
PD=2.6u $ $x=-200 $y=-700 $w=400 $h=600
MNMOS_2 N_1 B Gnd 0 NMOS W=450n L=150n AS=360f PS=2.6u AD=360f
PD=2.6u $ $x=200 $y=-1600 $w=400 $h=600 $m
MPMOS_1 Y A Vdd Vdd PMOS W=900n L=150n AS=810f PS=3.6u AD=810f
PD=3.6u $ $x=-1200 $y=600 $w=400 $h=600
MPMOS_2 Y B Vdd Vdd PMOS W=900n L=150n AS=810f PS=3.6u AD=810f
PD=3.6u $ $x=1200 $y=600 $w=400 $h=600 $m
VV3 Vdd Gnd DC 5 $ $x=3000 $y=800 $w=400 $h=600
VA A Gnd BIT ({1110} lt=100n ht=100n on=5 rt=0.1n ft=0.1n)
VB B Gnd BIT ({0110} lt=100n ht=100n on=5 rt=0.1n ft=0.1n)
.include "C:\Users\Snehasish\Desktop\model lib\[Link]"
.tran 1n 400n
.print V(A) V(B) V(Y)
.end
● Waveform :
21
5. PMOS Load Inverter (DC) :
● Schematic :
● Netlist :
MNMOS_1 out in Gnd 0 NMOS W=450n L=150n AS=405f PS=2.7u
AD=405f PD=2.7u $ $x=4700 $y=2700 $w=400 $h=600
MPMOS_1 out out Vdd Vdd PMOS W=900n L=150n AS=810f PS=3.6u
AD=810f PD=3.6u $ $x=4700 $y=3300 $w=400 $h=600
VVdd Vdd Gnd DC 5 $ $x=6200 $y=2700 $w=400 $h=600
VVin in Gnd DC 5 $ $x=3900 $y=2400 $w=400 $h=600
.include "C:\Users\am_ju\Desktop\[Link]"
.dc lin VVin 0 5 0.01
.print V(out)
.end
● Waveform :
22
6. PMOS Load Inverter (AC) :
● Schematic :
● Netlist :
23
MNMOS_1 Vout Vin Gnd 0 NMOS W=1.5u L=250n AS-1.35p PS=4.8u AD=1.35p PD=4.8u $
$x=-1400 $y=-500 $w=400 $h=600
MPMOS_1 Vout Vout Vdd Vdd PMOS W-3u L=250n AS-2.7p PS=7.8u AD-2.7p PD=7.8u $
$x=-1400 $y=600 Sw=400 $h=600
Vin Vdd Gnd DC 5 $ $x=600 $y=-200 Sw=400 $h=600
VV1 Vin Gnd DC 2.5 AC 1 0 $ $x=-2200 $y=-900 Sw=400 $h=600
.include "C:\Users\user1\Desktop\[Link]"
.AC dec 101 10 100Meg
.end
● Waveform :
24
7. CMOS Load Inverter :
● Schematic :
● Netlist :
MNMOS_1 Out In Gnd N_2 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $
$x=4500 $y=4300 $w=400 $h=600
MPMOS_1 Out In Vdd N_1 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u $
$x=4500 $y=5200 $w=400 $h=600
VVDD Vdd Gnd DC 5 $ $x=1800 $y=3800 $w=400 $h=600
VVin In Gnd DC 5 $ $x=3200 $y=3800 $w=400 $h=600
.include "C:\Users\am_ju\Desktop\dual - [Link]"
.dc VVoltageSource_2 0 5 0.0001
.print v(In) v(Out)
.end
● Waveform :
25
LAYOUT DESIGN USING SOFTWARE
In these experiments, we design the layout circuits and view the waveform. The software
that is used is Microwind. Microwind is an integrated EDA software encompassing IC
designs. It allows the designer to simulate and design an integrated circuit at physical
description level.
1. CMOS NAND :
● Schematic :
● Waveform :
26
2. CMOS NOR :
● Schematic :
● Waveform :
27
USE OF SYNOPSYS TOOLS FOR DIGITAL
CIRCUIT DESIGN
1. Synplify_Pro :
a. Writing the Verilog code for the Finite State Machine
(FSM) module in Synpilfy_Pro IDE.
b. Viewing the RTL Design, Pre-map Output View and
Technology View from the design.
c. For checking the Timing Report of the design with a
standard clock of 5MHz.
d. Can also be used for checking area placement and power
consumption reports.
● FSM Verilog Program :
module seq_detector_1010(input bit clk, rst_n, x, output z);
parameter A = 4'h1;
parameter B = 4'h2;
parameter C = 4'h3;
parameter D = 4'h4;
bit [3:0] state, next_state;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
state <= A;
end
else state <= next_state;
end
always @(state or x) begin
28
case(state)
A: begin
if(x == 0) next_state = A;
else next_state = B;
end
B: begin
if(x == 0) next_state = C;
else next_state = B;
end
C: begin
if(x == 0) next_state = A;
else next_state = D;
end
D: begin
if(x == 0) next_state = A; //This state only differs when
compared with Mealy Overlaping Machine
else next_state = B;
end
default: next_state = A;
endcase
end
assign z = (state == D) && (x == 0)? 1:0;
endmodule
● FSM Testbench:
module TB;
reg clk, rst_n, x;
wire z;
29
seq_detector_1010 sd(clk, rst_n, x, z);
initial clk = 0;
always #2 clk = ~clk;
initial begin
x = 0;
#1 rst_n = 0;
#2 rst_n = 1;
#3 x = 1;
#4 x = 1;
#4 x = 0;
#4 x = 1;
#4 x = 0;
#4 x = 1;
#4 x = 0;
#4 x = 1;
#4 x = 1;
#4 x = 1;
#4 x = 0;
#4 x = 1;
#4 x = 0;
#4 x = 1;
#4 x = 0;
#10;
$finish;
30
end
initial begin
// Dump waves
$dumpfile("[Link]");
$dumpvars(0);
end
endmodule
● RTL Design :
● Pre-map Output View:
31
● Technology View:
2. VCS and Verdi :
a. Viewing the Block Diagram.
b. Viewing Simulation Report.
c. Viewing the State Diagram.
d. Viewing the TIming Diagram.
● Block Diagram :
32
● State Diagram:
● Timing Diagram:
33
Conclusion :
From the above experiments, we have learnt primarily four sets of skills.
1. Digital Hardware designing using Verilog as a language and Modelsim as the
platform. We designed basic circuits such as adders, multiplexers etc.
2. FPGA implementation of Verilog using the Vivado platform. We have implemented
various counters, left shifting algorithms as well as learnt how seven segment
displays work in FPGA boards.
3. Design of digital circuits such as NAND and NOR gates using CMOS logic as well as
other implementations such as resistive load etc, on SPICE.
4. Understanding the Layout design of CMOS NAND and NOR gates using MIcrowinds
software
34